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[/] [xgate/] [trunk/] [bench/] [verilog/] [ram.v] - Blame information for rev 94

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1 37 rehayes
////////////////////////////////////////////////////////////////////////////////
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//
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//  WISHBONE revB.2 compliant Xgate Coprocessor - test bench ram
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//
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//  Author: Bob Hayes
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//          rehayes@opencores.org
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//
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//  Downloaded from: http://www.opencores.org/projects/xgate.....
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//
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2009, Robert Hayes
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// Supplemental terms.
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//     * Redistributions of source code must retain the above copyright
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//       notice, this list of conditions and the following disclaimer.
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//     * Neither the name of the <organization> nor the
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//       names of its contributors may be used to endorse or promote products
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//       derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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module ram #(parameter AWIDTH = 16,          // Address Bus width
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             parameter DWIDTH = 16)          // Data bus width
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  (
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  // Wishbone Slave Signals
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  output    [DWIDTH-1:0] ram_out,       // databus output
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  input     [AWIDTH-1:0] address,       // lower address bits
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  input     [DWIDTH-1:0] ram_in,        // databus input
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  input                  we,            // write enable input
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  input                  ce,            // Chip Enable
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  input                  stb,           // stobe/core select signal
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  input  [DWIDTH/8 -1:0] sel            // Select byte in word bus transaction
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  );
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  // Name Address Locations
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  parameter XGATE_XGMCTL   = 16'h0000;
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  //
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  // wires && regs
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  //
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  reg       [  7:0] ram_8 [65535:0];    // Testbench memory for holding XGATE test code
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  // Write memory interface to RAM
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  always @(posedge stb)
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    begin
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      if (ce && sel[0] && !sel[1] && we)
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        ram_8[address] <= ram_in[7:0];
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      if (ce && sel[1] && !sel[0] && we)
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        ram_8[address] <= ram_in[7:0];
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      if (ce && sel[1] && sel[0] && we)
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        begin
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          ram_8[address]   <= ram_in[15:8];
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          ram_8[address+1] <= ram_in[ 7:0];
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        end
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    end
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  // BIGENDIAN
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  assign ram_out = {DWIDTH{ce}} & {ram_8[address], ram_8[address+1]};
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  task dump_ram;
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    input [AWIDTH-1:0] start_address;
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    reg   [AWIDTH-1:0] dump_address;
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    integer i, j;
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    begin
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        $display("Dumping RAM - Starting Address #%h", start_address);
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        dump_address = start_address;
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        while (dump_address <= start_address + 16'h0080)
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          begin
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            $write("Address = %h", dump_address);
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            for (i = 0; i < 16; i = i + 1)
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              begin
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                $write(" %h", ram_8[dump_address]);
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                dump_address = dump_address + 1;
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              end
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            $write("\n");
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          end
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    end
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  endtask
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endmodule  // ram
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