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////////////////////////////////////////////////////////////////////////////////
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//
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// WISHBONE revB.2 compliant Xgate Coprocessor - Test Bench
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//
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// Author: Bob Hayes
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// rehayes@opencores.org
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//
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// Downloaded from: http://www.opencores.org/projects/xgate.....
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//
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2009, Robert Hayes
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// Supplemental terms.
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Neither the name of the <organization> nor the
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// names of its contributors may be used to endorse or promote products
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// derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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`include "timescale.v"
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module tst_bench_top();
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parameter MAX_CHANNEL = 127; // Max XGATE Interrupt Channel Number
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parameter STOP_ON_ERROR = 1'b0;
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parameter MAX_VECTOR = 22_000;
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parameter L_BYTE = 2'b01;
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parameter H_BYTE = 2'b10;
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parameter WORD = 2'b11;
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parameter TB_ADDR_WIDTH = 24; // Testbench address bus width
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parameter TB_DATA_WIDTH = 16;
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// Name Address Locations
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parameter XGATE_BASE = 24'h1000;
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parameter XGATE_XGMCTL = XGATE_BASE + 6'h00;
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parameter XGATE_XGCHID = XGATE_BASE + 6'h02;
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parameter XGATE_XGISPHI = XGATE_BASE + 6'h04;
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parameter XGATE_XGISPLO = XGATE_BASE + 6'h06;
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parameter XGATE_XGVBR = XGATE_BASE + 6'h08;
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parameter XGATE_XGIF_7 = XGATE_BASE + 6'h0a;
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parameter XGATE_XGIF_6 = XGATE_BASE + 6'h0c;
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parameter XGATE_XGIF_5 = XGATE_BASE + 6'h0e;
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parameter XGATE_XGIF_4 = XGATE_BASE + 6'h10;
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parameter XGATE_XGIF_3 = XGATE_BASE + 6'h12;
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parameter XGATE_XGIF_2 = XGATE_BASE + 6'h14;
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parameter XGATE_XGIF_1 = XGATE_BASE + 6'h16;
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parameter XGATE_XGIF_0 = XGATE_BASE + 6'h18;
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parameter XGATE_XGSWT = XGATE_BASE + 6'h1a;
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parameter XGATE_XGSEM = XGATE_BASE + 6'h1c;
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parameter XGATE_RES1 = XGATE_BASE + 6'h1e;
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parameter XGATE_XGCCR = XGATE_BASE + 6'h20;
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parameter XGATE_XGPC = XGATE_BASE + 6'h22;
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parameter XGATE_RES2 = XGATE_BASE + 6'h24;
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parameter XGATE_XGR1 = XGATE_BASE + 6'h26;
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parameter XGATE_XGR2 = XGATE_BASE + 6'h28;
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parameter XGATE_XGR3 = XGATE_BASE + 6'h2a;
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parameter XGATE_XGR4 = XGATE_BASE + 6'h2c;
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parameter XGATE_XGR5 = XGATE_BASE + 6'h2e;
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parameter XGATE_XGR6 = XGATE_BASE + 6'h30;
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parameter XGATE_XGR7 = XGATE_BASE + 6'h32;
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// Define bits in XGATE Control Register
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parameter XGMCTL_XGEM = 16'h8000;
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parameter XGMCTL_XGFRZM = 16'h4000;
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parameter XGMCTL_XGDBGM = 15'h2000;
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parameter XGMCTL_XGSSM = 15'h1000;
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parameter XGMCTL_XGFACTM = 15'h0800;
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parameter XGMCTL_XGBRKIEM = 15'h0400;
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parameter XGMCTL_XGSWEIFM = 15'h0200;
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parameter XGMCTL_XGIEM = 15'h0100;
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parameter XGMCTL_XGE = 16'h0080;
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parameter XGMCTL_XGFRZ = 16'h0040;
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parameter XGMCTL_XGDBG = 15'h0020;
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parameter XGMCTL_XGSS = 15'h0010;
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parameter XGMCTL_XGFACT = 15'h0008;
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parameter XGMCTL_XGBRKIE = 15'h0004;
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parameter XGMCTL_XGSWEIF = 15'h0002;
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parameter XGMCTL_XGIE = 15'h0001;
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// Define Address locations used by the testbench
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parameter CHECK_POINT = 16'h8000;
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parameter CHANNEL_ACK = CHECK_POINT + 2;
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parameter CHANNEL_ERR = CHECK_POINT + 4;
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parameter DEBUG_CNTRL = CHECK_POINT + 6;
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parameter TB_SEMPHORE = CHECK_POINT + 10;
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parameter CHANNEL_XGIRQ_0 = CHECK_POINT + 16;
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parameter CHANNEL_XGIRQ_1 = CHECK_POINT + 18;
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parameter CHANNEL_XGIRQ_2 = CHECK_POINT + 20;
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parameter CHANNEL_XGIRQ_3 = CHECK_POINT + 22;
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parameter CHANNEL_XGIRQ_4 = CHECK_POINT + 24;
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parameter CHANNEL_XGIRQ_5 = CHECK_POINT + 26;
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parameter CHANNEL_XGIRQ_6 = CHECK_POINT + 28;
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parameter CHANNEL_XGIRQ_7 = CHECK_POINT + 30;
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parameter BREAK_CAPT_0 = CHECK_POINT + 64;
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parameter BREAK_CAPT_1 = CHECK_POINT + 66;
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parameter BREAK_CAPT_2 = CHECK_POINT + 68;
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parameter BREAK_CAPT_3 = CHECK_POINT + 70;
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parameter BREAK_CAPT_4 = CHECK_POINT + 72;
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parameter BREAK_CAPT_5 = CHECK_POINT + 74;
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parameter BREAK_CAPT_6 = CHECK_POINT + 76;
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parameter BREAK_CAPT_7 = CHECK_POINT + 78;
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parameter SYS_RAM_BASE = 24'h00_0000;
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parameter RAM_WAIT_STATES = 1; // Number between 0 and 15
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parameter SYS_READ_DELAY = 10;
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parameter XGATE_ACCESS_DELAY = SYS_READ_DELAY + RAM_WAIT_STATES;
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parameter XGATE_SS_DELAY = XGATE_ACCESS_DELAY + RAM_WAIT_STATES;
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parameter IRQ_BASE = XGATE_BASE + 64;
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parameter IRQ_BYPS_0 = IRQ_BASE + 0;
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parameter IRQ_BYPS_1 = IRQ_BASE + 2;
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parameter IRQ_BYPS_2 = IRQ_BASE + 4;
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parameter IRQ_BYPS_3 = IRQ_BASE + 6;
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parameter IRQ_BYPS_4 = IRQ_BASE + 8;
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parameter IRQ_BYPS_5 = IRQ_BASE + 10;
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parameter IRQ_BYPS_6 = IRQ_BASE + 12;
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parameter IRQ_BYPS_7 = IRQ_BASE + 14;
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//
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// wires && regs
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//
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reg mstr_test_clk;
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reg [19:0] vector;
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reg [15:0] error_count;
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reg [ 7:0] test_num;
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reg [15:0] q, qq;
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reg rstn;
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reg sync_reset;
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reg scantestmode;
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reg [MAX_CHANNEL:1] channel_req; // XGATE Interrupt inputs
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wire [MAX_CHANNEL:1] xgif; // XGATE Interrupt outputs
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wire [ 7:0] xgswt; // XGATE Software Trigger outputs
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wire xg_sw_irq; // Xgate Software Error interrupt
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wire [15:0] brkpt_cntl; //
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wire [15:0] wbm_dat_o; // WISHBONE Master Mode data output from XGATE
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wire [15:0] wbm_dat_i; // WISHBONE Master Mode data input to XGATE
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wire [15:0] wbm_adr_o; // WISHBONE Master Mode address output from XGATE
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wire [ 1:0] wbm_sel_o;
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reg mem_wait_state_enable;
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wire [15:0] tb_ram_out;
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wire [15:0] tb_slave_dout; // WISHBONE data bus output from testbench slave module
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wire error_pulse; // Error detected output pulse from the testbench slave module
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wire tb_slave_ack; // WISHBONE ack from testbench slave module
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wire ack_pulse; // Thread ack output pulse from testbench slave module
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wire wbm_cyc_o;
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wire wbm_stb_o;
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wire wbm_we_o;
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wire wbs_err_o;
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// Registers used to mirror internal registers
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reg [15:0] data_xgmctl;
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reg [15:0] data_xgchid;
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reg [15:0] data_xgvbr;
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reg [15:0] data_xgswt;
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reg [15:0] data_xgsem;
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wire sys_cyc;
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wire sys_stb;
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wire sys_we;
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wire [ 1:0] sys_sel;
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wire [23:0] sys_adr;
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wire [15:0] sys_dout;
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wire [15:0] sys_din;
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wire host_ack;
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wire [15:0] host_dout;
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wire host_cyc;
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wire host_stb;
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wire host_we;
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wire [ 1:0] host_sel;
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wire [23:0] host_adr;
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wire [15:0] host_din;
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wire xgate_ack;
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wire [15:0] xgate_dout;
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wire xgate_cyc;
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wire xgate_stb;
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wire xgate_we;
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wire [ 1:0] xgate_sel;
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wire [15:0] xgate_adr;
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wire [15:0] xgate_din;
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wire xgate_s_stb;
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wire xgate_s_ack;
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wire [15:0] xgate_s_dout;
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wire slv2_stb;
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wire ram_sel;
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wire [15:0] ram_dout;
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// initial values and testbench setup
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initial
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begin
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mstr_test_clk = 0;
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vector = 0;
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test_num = 0;
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scantestmode = 0;
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error_count = 0;
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mem_wait_state_enable = 0;
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// channel_req = 0;
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`ifdef WAVES
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$shm_open("waves");
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$shm_probe("AS", tst_bench_top, "AS");
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$display("\nINFO: Signal dump enabled ...\n\n");
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`endif
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`ifdef WAVES_V
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$dumpfile ("xgate_wave_dump.lxt");
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$dumpvars (0, tst_bench_top);
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$dumpon;
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$display("\nINFO: VCD Signal dump enabled ...\n\n");
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`endif
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//-------------------------------------------------------
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// Enable Debussy dumping of simulation
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`ifdef FSDB
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$fsdbDumpfile("verilog.fsdb");
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$fsdbDumpvars(0, tst_bench_top);
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`endif
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end
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// generate clock
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always #20 mstr_test_clk = ~mstr_test_clk;
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// Keep a count of how many clocks we've simulated
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always @(posedge mstr_test_clk)
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begin
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vector <= vector + 1;
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if (vector > MAX_VECTOR)
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begin
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error_count <= error_count + 1;
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$display("\n ------ !!!!! Simulation Timeout at vector=%d\n -------", vector);
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wrap_up;
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end
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end
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2 |
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// Add up errors that come from WISHBONE read compares
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36 |
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always @host.cmp_error_detect
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21 |
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begin
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error_count <= error_count + 1;
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end
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11 |
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282 |
54 |
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always @(posedge error_pulse) //channel_ack_wrt
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2 |
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begin
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54 |
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#1;
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5 |
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error_count = error_count + 1;
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if (STOP_ON_ERROR == 1'b1)
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wrap_up;
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end
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2 |
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wire [ 6:0] current_active_channel = xgate.risc.xgchid;
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291 |
54 |
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always @(posedge ack_pulse) //channel_ack_wrt
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2 |
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clear_channel(current_active_channel);
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21 |
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294 |
2 |
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295 |
62 |
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296 |
36 |
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// Testbench RAM for Xgate program storage and Load/Store instruction tests
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ram p_ram
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(
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// Outputs
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300 |
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.ram_out( ram_dout ),
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// inputs
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302 |
54 |
rehayes |
.address( sys_adr[15:0] ),
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303 |
36 |
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.ram_in( sys_dout ),
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.we( sys_we ),
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305 |
54 |
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.ce( ram_sel ),
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36 |
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.stb( mstr_test_clk ),
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307 |
54 |
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.sel( sys_sel )
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36 |
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);
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309 |
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// hookup wishbone master model
|
311 |
94 |
rehayes |
wb_master_model #(.dwidth(TB_DATA_WIDTH), .awidth(TB_ADDR_WIDTH))
|
312 |
36 |
rehayes |
host(
|
313 |
|
|
// Outputs
|
314 |
|
|
.cyc( host_cyc ),
|
315 |
|
|
.stb( host_stb ),
|
316 |
|
|
.we( host_we ),
|
317 |
|
|
.sel( host_sel ),
|
318 |
|
|
.adr( host_adr ),
|
319 |
|
|
.dout( host_dout ),
|
320 |
|
|
// inputs
|
321 |
68 |
rehayes |
.din( sys_din ),
|
322 |
|
|
.clk( mstr_test_clk ),
|
323 |
|
|
.ack( host_ack ),
|
324 |
|
|
.rst( rstn ),
|
325 |
|
|
.err( 1'b0 ),
|
326 |
|
|
.rty( 1'b0 )
|
327 |
36 |
rehayes |
);
|
328 |
|
|
|
329 |
94 |
rehayes |
bus_arbitration #(.dwidth(TB_DATA_WIDTH),
|
330 |
|
|
.awidth(TB_ADDR_WIDTH),
|
331 |
89 |
rehayes |
.ram_base(0),
|
332 |
|
|
.ram_size(17'h10000),
|
333 |
|
|
.slv1_base(XGATE_BASE),
|
334 |
|
|
.slv1_size(128),
|
335 |
|
|
.slv2_base(CHECK_POINT),
|
336 |
|
|
.slv2_size(32),
|
337 |
|
|
.ram_wait_states(RAM_WAIT_STATES)
|
338 |
65 |
rehayes |
)
|
339 |
36 |
rehayes |
arb(
|
340 |
|
|
// System bus I/O
|
341 |
|
|
.sys_cyc( sys_cyc ),
|
342 |
|
|
.sys_stb( sys_stb ),
|
343 |
|
|
.sys_we( sys_we ),
|
344 |
|
|
.sys_sel( sys_sel ),
|
345 |
|
|
.sys_adr( sys_adr ),
|
346 |
|
|
.sys_dout( sys_dout ),
|
347 |
54 |
rehayes |
.sys_din( sys_din ),
|
348 |
36 |
rehayes |
// Host bus I/O
|
349 |
|
|
.host_ack( host_ack ),
|
350 |
|
|
.host_dout( host_din ),
|
351 |
|
|
.host_cyc( host_cyc ),
|
352 |
|
|
.host_stb( host_stb ),
|
353 |
|
|
.host_we( host_we ),
|
354 |
|
|
.host_sel( host_sel ),
|
355 |
|
|
.host_adr( host_adr ),
|
356 |
|
|
.host_din( host_dout ),
|
357 |
|
|
// Alternate Bus Master #1 Bus I/O
|
358 |
|
|
.alt1_ack( xgate_ack ),
|
359 |
|
|
.alt1_cyc( wbm_cyc_o ),
|
360 |
|
|
.alt1_stb( wbm_stb_o ),
|
361 |
|
|
.alt1_we( wbm_we_o ),
|
362 |
|
|
.alt1_sel( wbm_sel_o ),
|
363 |
54 |
rehayes |
.alt1_adr( {8'h00, wbm_adr_o} ),
|
364 |
36 |
rehayes |
.alt1_din( wbm_dat_o ),
|
365 |
54 |
rehayes |
// RAM
|
366 |
|
|
.ram_sel( ram_sel ),
|
367 |
|
|
.ram_dout( ram_dout ),
|
368 |
36 |
rehayes |
// Slave #1 Bus I/O
|
369 |
|
|
.slv1_stb( xgate_s_stb ),
|
370 |
|
|
.slv1_ack( xgate_s_ack ),
|
371 |
|
|
.slv1_din( xgate_s_dout ),
|
372 |
|
|
// Slave #2 Bus I/O
|
373 |
|
|
.slv2_stb( slv2_stb ),
|
374 |
68 |
rehayes |
.slv2_ack( tb_slave_ack ),
|
375 |
62 |
rehayes |
.slv2_din( tb_slave_dout ),
|
376 |
36 |
rehayes |
// Miscellaneous
|
377 |
|
|
.host_clk( mstr_test_clk ),
|
378 |
|
|
.risc_clk( mstr_test_clk ),
|
379 |
|
|
.rst( rstn ), // No Connect
|
380 |
|
|
.err( 1'b0 ), // No Connect
|
381 |
|
|
.rty( 1'b0 ) // No Connect
|
382 |
|
|
);
|
383 |
62 |
rehayes |
|
384 |
5 |
rehayes |
// hookup XGATE core - Parameters take all default values
|
385 |
54 |
rehayes |
xgate_top #(.SINGLE_CYCLE(1'b0),
|
386 |
68 |
rehayes |
.WB_RD_DEFAULT(1'b0),
|
387 |
89 |
rehayes |
.MAX_CHANNEL(MAX_CHANNEL)) // Max XGATE Interrupt Channel Number
|
388 |
|
|
xgate(
|
389 |
|
|
// Wishbone slave interface
|
390 |
|
|
.wbs_clk_i( mstr_test_clk ),
|
391 |
94 |
rehayes |
.wbs_rst_i( sync_reset ), // sync_reset
|
392 |
|
|
.arst_i( rstn ), // async resetn
|
393 |
89 |
rehayes |
.wbs_adr_i( sys_adr[6:1] ),
|
394 |
|
|
.wbs_dat_i( sys_dout ),
|
395 |
|
|
.wbs_dat_o( xgate_s_dout ),
|
396 |
|
|
.wbs_we_i( sys_we ),
|
397 |
|
|
.wbs_stb_i( xgate_s_stb ),
|
398 |
|
|
.wbs_cyc_i( sys_cyc ),
|
399 |
|
|
.wbs_sel_i( sys_sel ),
|
400 |
|
|
.wbs_ack_o( xgate_s_ack ),
|
401 |
|
|
.wbs_err_o( wbs_err_o ),
|
402 |
2 |
rehayes |
|
403 |
89 |
rehayes |
// Wishbone master Signals
|
404 |
|
|
.wbm_dat_o( wbm_dat_o ),
|
405 |
|
|
.wbm_we_o( wbm_we_o ),
|
406 |
|
|
.wbm_stb_o( wbm_stb_o ),
|
407 |
|
|
.wbm_cyc_o( wbm_cyc_o ),
|
408 |
|
|
.wbm_sel_o( wbm_sel_o ),
|
409 |
|
|
.wbm_adr_o( wbm_adr_o ),
|
410 |
|
|
.wbm_dat_i( sys_din ),
|
411 |
|
|
.wbm_ack_i( xgate_ack ),
|
412 |
5 |
rehayes |
|
413 |
89 |
rehayes |
.xgif( xgif ), // XGATE Interrupt Flag output
|
414 |
|
|
.xg_sw_irq( xg_sw_irq ), // XGATE Software Error Interrupt Flag output
|
415 |
|
|
.xgswt( xgswt ),
|
416 |
|
|
.risc_clk( mstr_test_clk ),
|
417 |
|
|
.chan_req_i( {channel_req[MAX_CHANNEL:40], xgswt, channel_req[31:1]} ),
|
418 |
|
|
.debug_mode_i( 1'b0 ),
|
419 |
|
|
.secure_mode_i( 1'b0 ),
|
420 |
|
|
.scantestmode( scantestmode )
|
421 |
2 |
rehayes |
);
|
422 |
|
|
|
423 |
54 |
rehayes |
tb_slave #(.DWIDTH(16),
|
424 |
89 |
rehayes |
.SINGLE_CYCLE(1'b1),
|
425 |
|
|
.MAX_CHANNEL(MAX_CHANNEL))
|
426 |
|
|
tb_slave_regs(
|
427 |
|
|
// wishbone interface
|
428 |
|
|
.wb_clk_i( mstr_test_clk ),
|
429 |
|
|
.wb_rst_i( 1'b0 ),
|
430 |
|
|
.arst_i( rstn ),
|
431 |
|
|
.wb_adr_i( sys_adr[4:1] ),
|
432 |
|
|
.wb_dat_i( sys_dout ),
|
433 |
|
|
.wb_dat_o( tb_slave_dout),
|
434 |
|
|
.wb_we_i( sys_we ),
|
435 |
|
|
.wb_stb_i( slv2_stb ),
|
436 |
|
|
.wb_cyc_i( sys_cyc ),
|
437 |
|
|
.wb_sel_i( sys_sel ),
|
438 |
|
|
.wb_ack_o( tb_slave_ack ),
|
439 |
2 |
rehayes |
|
440 |
89 |
rehayes |
.ack_pulse( ack_pulse ),
|
441 |
82 |
rehayes |
.brkpt_cntl( brkpt_cntl ),
|
442 |
89 |
rehayes |
.error_pulse( error_pulse ),
|
443 |
|
|
.brk_pt( ),
|
444 |
|
|
.x_address( wbm_adr_o ),
|
445 |
|
|
.xgif( xgif ),
|
446 |
|
|
.vector( vector )
|
447 |
54 |
rehayes |
);
|
448 |
2 |
rehayes |
|
449 |
89 |
rehayes |
tb_debug #(.DWIDTH(16), // Data bus width
|
450 |
82 |
rehayes |
.BREAK_CAPT_0(BREAK_CAPT_0),
|
451 |
|
|
.BREAK_CAPT_1(BREAK_CAPT_1),
|
452 |
|
|
.BREAK_CAPT_2(BREAK_CAPT_2),
|
453 |
|
|
.BREAK_CAPT_3(BREAK_CAPT_3),
|
454 |
|
|
.BREAK_CAPT_4(BREAK_CAPT_4),
|
455 |
|
|
.BREAK_CAPT_5(BREAK_CAPT_5),
|
456 |
|
|
.BREAK_CAPT_6(BREAK_CAPT_6),
|
457 |
|
|
.BREAK_CAPT_7(BREAK_CAPT_7))
|
458 |
|
|
debugger(
|
459 |
89 |
rehayes |
.arst_i( rstn ),
|
460 |
|
|
.risc_clk( mstr_test_clk ),
|
461 |
|
|
.brkpt_cntl( brkpt_cntl )
|
462 |
82 |
rehayes |
);
|
463 |
54 |
rehayes |
|
464 |
|
|
|
465 |
2 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
466 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
467 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
468 |
|
|
|
469 |
54 |
rehayes |
// Main Test Program
|
470 |
2 |
rehayes |
initial
|
471 |
|
|
begin
|
472 |
36 |
rehayes |
$display("\nstatus at time: %t Testbench started", $time);
|
473 |
2 |
rehayes |
|
474 |
36 |
rehayes |
// reset system
|
475 |
94 |
rehayes |
rstn <= 1'b0; // negate reset
|
476 |
|
|
channel_req <= 1; //
|
477 |
|
|
sync_reset <= 1'b0; // Don't do sync reset
|
478 |
|
|
#5; // Keep the async reset pulse with less than a clock cycle
|
479 |
|
|
rstn = 1'b1; // negate async reset
|
480 |
100 |
rehayes |
channel_req = 0; //
|
481 |
36 |
rehayes |
repeat(1) @(posedge mstr_test_clk);
|
482 |
2 |
rehayes |
|
483 |
36 |
rehayes |
$display("\nstatus at time: %t done reset", $time);
|
484 |
21 |
rehayes |
|
485 |
100 |
rehayes |
pc_rollover;
|
486 |
|
|
|
487 |
89 |
rehayes |
test_skipjack;
|
488 |
100 |
rehayes |
wrap_up;
|
489 |
89 |
rehayes |
|
490 |
36 |
rehayes |
test_inst_set;
|
491 |
21 |
rehayes |
|
492 |
36 |
rehayes |
test_debug_mode;
|
493 |
2 |
rehayes |
|
494 |
36 |
rehayes |
test_debug_bit;
|
495 |
21 |
rehayes |
|
496 |
36 |
rehayes |
test_chid_debug;
|
497 |
21 |
rehayes |
|
498 |
41 |
rehayes |
reg_test_16;
|
499 |
89 |
rehayes |
|
500 |
68 |
rehayes |
reg_irq;
|
501 |
41 |
rehayes |
|
502 |
94 |
rehayes |
sync_reset_test;
|
503 |
100 |
rehayes |
|
504 |
68 |
rehayes |
// host_ram;
|
505 |
54 |
rehayes |
|
506 |
36 |
rehayes |
// End testing
|
507 |
|
|
wrap_up;
|
508 |
2 |
rehayes |
end
|
509 |
|
|
|
510 |
36 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
511 |
21 |
rehayes |
// Test CHID Debug mode operation
|
512 |
|
|
task test_chid_debug;
|
513 |
|
|
begin
|
514 |
|
|
test_num = test_num + 1;
|
515 |
|
|
$display("\nTEST #%d Starts at vector=%d, test_chid_debug", test_num, vector);
|
516 |
36 |
rehayes |
$readmemh("../../../bench/verilog/debug_test.v", p_ram.ram_8);
|
517 |
21 |
rehayes |
|
518 |
68 |
rehayes |
// Enable interrupts to RISC
|
519 |
|
|
host.wb_write(0, IRQ_BYPS_0, 16'h0000, WORD);
|
520 |
|
|
|
521 |
21 |
rehayes |
data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
|
522 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable interrupt on BRK instruction
|
523 |
65 |
rehayes |
$display("BRK Software Error Interrupt enabled at vector=%d", vector);
|
524 |
21 |
rehayes |
|
525 |
|
|
activate_thread_sw(3);
|
526 |
|
|
|
527 |
|
|
wait_debug_set; // Debug Status bit is set by BRK instruction
|
528 |
|
|
|
529 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGPC, 16'h20c6, WORD); // See Program code (BRK).
|
530 |
|
|
host.wb_cmp(0, XGATE_XGR3, 16'h0001, WORD); // See Program code.R3 = 1
|
531 |
|
|
host.wb_cmp(0, XGATE_XGCHID, 16'h0003, WORD); // Check for Correct CHID
|
532 |
65 |
rehayes |
$display("Debug entry detected at vector=%d", vector);
|
533 |
21 |
rehayes |
|
534 |
|
|
channel_req[5] = 1'b1; //
|
535 |
|
|
repeat(7) @(posedge mstr_test_clk);
|
536 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGCHID, 16'h0003, WORD); // Check for Correct CHID
|
537 |
21 |
rehayes |
|
538 |
89 |
rehayes |
host.wb_write(0, XGATE_XGCHID, 16'h000f, H_BYTE); // Check byte select lines
|
539 |
41 |
rehayes |
repeat(4) @(posedge mstr_test_clk);
|
540 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGCHID, 16'h0003, WORD); // Verify CHID is unchanged
|
541 |
21 |
rehayes |
|
542 |
89 |
rehayes |
host.wb_write(0, XGATE_XGCHID, 16'h000f, L_BYTE); // Change CHID
|
543 |
|
|
host.wb_cmp(0, XGATE_XGCHID, 16'h000f, WORD); // Check for Correct CHID
|
544 |
21 |
rehayes |
|
545 |
89 |
rehayes |
host.wb_write(0, XGATE_XGCHID, 16'h0000, WORD); // Change CHID to 00, RISC should go to IDLE state
|
546 |
62 |
rehayes |
|
547 |
21 |
rehayes |
repeat(1) @(posedge mstr_test_clk);
|
548 |
|
|
|
549 |
89 |
rehayes |
host.wb_write(0, XGATE_XGCHID, 16'h0004, WORD); // Change CHID
|
550 |
21 |
rehayes |
|
551 |
|
|
repeat(8) @(posedge mstr_test_clk);
|
552 |
65 |
rehayes |
$display("Channel ID changed at vector=%d", vector);
|
553 |
21 |
rehayes |
|
554 |
89 |
rehayes |
|
555 |
21 |
rehayes |
data_xgmctl = XGMCTL_XGDBGM;
|
556 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit
|
557 |
21 |
rehayes |
|
558 |
89 |
rehayes |
wait_debug_set; // Debug Status bit is set by BRK instruction
|
559 |
|
|
host.wb_cmp(0, XGATE_XGCHID, 16'h0004, WORD); // Check for Correct CHID
|
560 |
|
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit (Excape from Break State and run)
|
561 |
21 |
rehayes |
|
562 |
|
|
wait_debug_set; // Debug Status bit is set by BRK instruction
|
563 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGCHID, 16'h0005, WORD); // Check for Correct CHID
|
564 |
21 |
rehayes |
activate_channel(6);
|
565 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit (Excape from Break State and run)
|
566 |
21 |
rehayes |
|
567 |
89 |
rehayes |
wait_debug_set; // Debug Status bit is set by BRK instruction
|
568 |
|
|
host.wb_cmp(0, XGATE_XGCHID, 16'h0006, WORD); // Check for Correct CHID
|
569 |
|
|
host.wb_cmp(0, XGATE_XGPC, 16'h211c, WORD); // See Program code (BRK)
|
570 |
21 |
rehayes |
data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
|
571 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step
|
572 |
65 |
rehayes |
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
|
573 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGPC, 16'h211e, WORD); // See Program code (BRA)
|
574 |
|
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step
|
575 |
65 |
rehayes |
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
|
576 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGPC, 16'h2122, WORD); // See Program code ()
|
577 |
21 |
rehayes |
|
578 |
|
|
repeat(20) @(posedge mstr_test_clk);
|
579 |
|
|
|
580 |
|
|
data_xgmctl = XGMCTL_XGDBGM;
|
581 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit
|
582 |
21 |
rehayes |
|
583 |
|
|
repeat(50) @(posedge mstr_test_clk);
|
584 |
|
|
|
585 |
36 |
rehayes |
p_ram.dump_ram(0);
|
586 |
|
|
|
587 |
68 |
rehayes |
read_ram_cmp(16'h0000, 16'h7b55);
|
588 |
|
|
read_ram_cmp(16'h0004, 16'h7faa);
|
589 |
|
|
read_ram_cmp(16'h0006, 16'h6f55);
|
590 |
|
|
read_ram_cmp(16'h0008, 16'h00c3);
|
591 |
|
|
read_ram_cmp(16'h000a, 16'h5f66);
|
592 |
|
|
read_ram_cmp(16'h000c, 16'h0003);
|
593 |
|
|
read_ram_cmp(16'h0022, 16'hccxx);
|
594 |
|
|
read_ram_cmp(16'h0026, 16'hxx99);
|
595 |
|
|
read_ram_cmp(16'h0032, 16'h1fcc);
|
596 |
|
|
read_ram_cmp(16'h0038, 16'h2f99);
|
597 |
|
|
read_ram_cmp(16'h0042, 16'h33xx);
|
598 |
|
|
read_ram_cmp(16'h0046, 16'hxx55);
|
599 |
|
|
read_ram_cmp(16'h0052, 16'hxx66);
|
600 |
|
|
read_ram_cmp(16'h0058, 16'h99xx);
|
601 |
|
|
read_ram_cmp(16'h0062, 16'h1faa);
|
602 |
|
|
read_ram_cmp(16'h0068, 16'h2fcc);
|
603 |
41 |
rehayes |
|
604 |
21 |
rehayes |
end
|
605 |
|
|
endtask
|
606 |
|
|
|
607 |
36 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
608 |
11 |
rehayes |
// Test Debug bit operation
|
609 |
|
|
task test_debug_bit;
|
610 |
2 |
rehayes |
begin
|
611 |
11 |
rehayes |
test_num = test_num + 1;
|
612 |
21 |
rehayes |
$display("\nTEST #%d Starts at vector=%d, test_debug_bit", test_num, vector);
|
613 |
36 |
rehayes |
$readmemh("../../../bench/verilog/debug_test.v", p_ram.ram_8);
|
614 |
21 |
rehayes |
|
615 |
68 |
rehayes |
// Enable interrupts to RISC
|
616 |
|
|
host.wb_write(0, IRQ_BYPS_0, 16'h0000, WORD);
|
617 |
|
|
|
618 |
11 |
rehayes |
data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
|
619 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable interrupt on BRK instruction
|
620 |
11 |
rehayes |
|
621 |
|
|
activate_thread_sw(2);
|
622 |
21 |
rehayes |
|
623 |
65 |
rehayes |
// Approxmatly 12 instructions need to be done before activating Debug Mode
|
624 |
|
|
repeat(12 + RAM_WAIT_STATES*12) @(posedge mstr_test_clk);
|
625 |
11 |
rehayes |
|
626 |
|
|
data_xgmctl = XGMCTL_XGDBGM | XGMCTL_XGDBG;
|
627 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Set Debug Mode Control Bit
|
628 |
21 |
rehayes |
repeat(5) @(posedge mstr_test_clk);
|
629 |
65 |
rehayes |
$display("DEBUG bit set at vector=%d", vector);
|
630 |
21 |
rehayes |
|
631 |
36 |
rehayes |
host.wb_read(1, XGATE_XGR3, q, WORD);
|
632 |
21 |
rehayes |
data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
|
633 |
|
|
qq = q;
|
634 |
|
|
|
635 |
89 |
rehayes |
// The Xgate test program is in an infinite loop incrementing R3
|
636 |
21 |
rehayes |
while (qq == q) // Look for change in R3 register
|
637 |
|
|
begin
|
638 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step
|
639 |
|
|
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
|
640 |
|
|
host.wb_read(1, XGATE_XGR3, q, WORD);
|
641 |
21 |
rehayes |
end
|
642 |
|
|
if (q != (qq+1))
|
643 |
|
|
begin
|
644 |
89 |
rehayes |
$display("Error! - Unexpected value of R3 at vector=%d", vector);
|
645 |
|
|
error_count = error_count + 1;
|
646 |
21 |
rehayes |
end
|
647 |
|
|
|
648 |
|
|
|
649 |
89 |
rehayes |
host.wb_write(1, XGATE_XGPC, 16'h2094, WORD); // Write to PC to force exit from infinite loop
|
650 |
54 |
rehayes |
repeat(10) @(posedge mstr_test_clk);
|
651 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGPC, 16'h2094, WORD); // Verify Proram Counter was changed
|
652 |
65 |
rehayes |
$display("Program Counter changed at vector=%d", vector);
|
653 |
21 |
rehayes |
|
654 |
|
|
data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
|
655 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load ADDL instruction)
|
656 |
65 |
rehayes |
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
|
657 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGR4, 16'h0002, WORD); // See Program code.(R4 <= R4 + 1)
|
658 |
21 |
rehayes |
|
659 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load ADDL instruction)
|
660 |
65 |
rehayes |
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
|
661 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGR4, 16'h0003, WORD); // See Program code.(R4 <= R4 + 1)
|
662 |
21 |
rehayes |
|
663 |
|
|
data_xgmctl = XGMCTL_XGDBGM;
|
664 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit
|
665 |
|
|
// Should be back in Run Mode
|
666 |
21 |
rehayes |
|
667 |
|
|
// data_xgmctl = XGMCTL_XGSWEIFM | XGMCTL_XGSWEIF | XGMCTL_XGBRKIEM;
|
668 |
36 |
rehayes |
// host.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Clear Software Interrupt and BRK Interrupt Enable Bit
|
669 |
11 |
rehayes |
repeat(15) @(posedge mstr_test_clk);
|
670 |
21 |
rehayes |
|
671 |
2 |
rehayes |
end
|
672 |
|
|
endtask
|
673 |
|
|
|
674 |
36 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
675 |
11 |
rehayes |
// Test Debug mode operation
|
676 |
|
|
task test_debug_mode;
|
677 |
2 |
rehayes |
begin
|
678 |
11 |
rehayes |
test_num = test_num + 1;
|
679 |
|
|
$display("\nTEST #%d Starts at vector=%d, test_debug_mode", test_num, vector);
|
680 |
36 |
rehayes |
$readmemh("../../../bench/verilog/debug_test.v", p_ram.ram_8);
|
681 |
21 |
rehayes |
|
682 |
68 |
rehayes |
// Enable interrupts to RISC
|
683 |
|
|
host.wb_write(0, IRQ_BYPS_0, 16'h0000, WORD);
|
684 |
|
|
|
685 |
11 |
rehayes |
data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
|
686 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable interrupt on BRK instruction
|
687 |
11 |
rehayes |
|
688 |
|
|
activate_thread_sw(1);
|
689 |
21 |
rehayes |
|
690 |
11 |
rehayes |
wait_debug_set; // Debug Status bit is set by BRK instruction
|
691 |
|
|
|
692 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGPC, 16'h203a, WORD); // See Program code (BRK).
|
693 |
|
|
host.wb_cmp(0, XGATE_XGR3, 16'h0001, WORD); // See Program code.R3 = 1
|
694 |
11 |
rehayes |
|
695 |
|
|
data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
|
696 |
|
|
|
697 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load ADDL instruction)
|
698 |
65 |
rehayes |
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
|
699 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGPC, 16'h203c, WORD); // PC + 2.
|
700 |
11 |
rehayes |
|
701 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load NOP instruction)
|
702 |
|
|
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk); // Execute ADDL instruction
|
703 |
|
|
host.wb_cmp(0, XGATE_XGR3, 16'h0002, WORD); // See Program code.(R3 <= R3 + 1)
|
704 |
|
|
host.wb_cmp(0, XGATE_XGCCR, 16'h0000, WORD); // See Program code.
|
705 |
|
|
host.wb_cmp(0, XGATE_XGPC, 16'h203e, WORD); // PC + 2.
|
706 |
65 |
rehayes |
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
|
707 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGPC, 16'h203e, WORD); // Still no change.
|
708 |
11 |
rehayes |
|
709 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load BRA instruction)
|
710 |
|
|
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk); // Execute NOP instruction
|
711 |
|
|
host.wb_cmp(0, XGATE_XGPC, 16'h2040, WORD); // See Program code.
|
712 |
11 |
rehayes |
|
713 |
|
|
|
714 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step
|
715 |
|
|
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk); // Execute BRA instruction
|
716 |
|
|
host.wb_cmp(0, XGATE_XGPC, 16'h2064, WORD); // PC = Branch destination.
|
717 |
|
|
// Load ADDL instruction
|
718 |
21 |
rehayes |
|
719 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load LDW R7 instruction)
|
720 |
|
|
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk); // Execute ADDL instruction
|
721 |
|
|
host.wb_cmp(0, XGATE_XGPC, 16'h2066, WORD); // PC + 2.
|
722 |
|
|
host.wb_cmp(0, XGATE_XGR3, 16'h0003, WORD); // See Program code.(R3 <= R3 + 1)
|
723 |
11 |
rehayes |
|
724 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (LDW R7)
|
725 |
65 |
rehayes |
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
|
726 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGPC, 16'h2068, WORD); // PC + 2.
|
727 |
|
|
host.wb_cmp(0, XGATE_XGR7, 16'h00c3, WORD); // See Program code
|
728 |
11 |
rehayes |
|
729 |
|
|
repeat(1) @(posedge mstr_test_clk);
|
730 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (BRA)
|
731 |
65 |
rehayes |
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
|
732 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGPC, 16'h2048, WORD); // See Program code.
|
733 |
11 |
rehayes |
|
734 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (STW R3)
|
735 |
65 |
rehayes |
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
|
736 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGPC, 16'h204a, WORD); // PC + 2.
|
737 |
|
|
host.wb_cmp(0, XGATE_XGR3, 16'h0003, WORD); // See Program code.(R3 <= R3 + 1)
|
738 |
11 |
rehayes |
|
739 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (R3 <= R3 + 1)
|
740 |
65 |
rehayes |
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
|
741 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGPC, 16'h204c, WORD); // PC + 2.
|
742 |
11 |
rehayes |
|
743 |
65 |
rehayes |
repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
|
744 |
11 |
rehayes |
|
745 |
|
|
data_xgmctl = XGMCTL_XGDBGM;
|
746 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit
|
747 |
|
|
// Should be back in Run Mode
|
748 |
11 |
rehayes |
wait_irq_set(1);
|
749 |
36 |
rehayes |
host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);
|
750 |
21 |
rehayes |
|
751 |
11 |
rehayes |
data_xgmctl = XGMCTL_XGSWEIFM | XGMCTL_XGSWEIF | XGMCTL_XGBRKIEM;
|
752 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Software Interrupt and BRK Interrupt Enable Bit
|
753 |
11 |
rehayes |
repeat(15) @(posedge mstr_test_clk);
|
754 |
21 |
rehayes |
|
755 |
2 |
rehayes |
end
|
756 |
|
|
endtask
|
757 |
|
|
|
758 |
36 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
759 |
11 |
rehayes |
// Test instruction set
|
760 |
|
|
task test_inst_set;
|
761 |
|
|
begin
|
762 |
36 |
rehayes |
$readmemh("../../../bench/verilog/inst_test.v", p_ram.ram_8);
|
763 |
11 |
rehayes |
test_num = test_num + 1;
|
764 |
65 |
rehayes |
$display("\nTEST #%d Starts at vector=%d, test_inst_set", test_num, vector);
|
765 |
21 |
rehayes |
repeat(1) @(posedge mstr_test_clk);
|
766 |
89 |
rehayes |
|
767 |
100 |
rehayes |
// Enable XGATE SW interrupt for error detection of bad instructions
|
768 |
|
|
// There should not be any!
|
769 |
|
|
data_xgmctl = XGMCTL_XGIEM | XGMCTL_XGIE;
|
770 |
|
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);
|
771 |
|
|
|
772 |
68 |
rehayes |
// Enable interrupts to RISC
|
773 |
|
|
host.wb_write(0, IRQ_BYPS_0, 16'h0000, WORD);
|
774 |
11 |
rehayes |
|
775 |
94 |
rehayes |
// Test Shift instructions
|
776 |
11 |
rehayes |
activate_thread_sw(1);
|
777 |
|
|
wait_irq_set(1);
|
778 |
36 |
rehayes |
host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);
|
779 |
21 |
rehayes |
|
780 |
94 |
rehayes |
// Test Logical Byte wide instructions
|
781 |
11 |
rehayes |
activate_thread_sw(2);
|
782 |
|
|
wait_irq_set(2);
|
783 |
36 |
rehayes |
host.wb_write(1, XGATE_XGIF_0, 16'h0004, WORD);
|
784 |
11 |
rehayes |
|
785 |
94 |
rehayes |
// Test Logical Word Wide instructions
|
786 |
11 |
rehayes |
activate_thread_sw(3);
|
787 |
|
|
wait_irq_set(3);
|
788 |
36 |
rehayes |
host.wb_write(1, XGATE_XGIF_0, 16'h0008, WORD);
|
789 |
21 |
rehayes |
|
790 |
94 |
rehayes |
// Test Bit Field instructions
|
791 |
11 |
rehayes |
activate_thread_sw(4);
|
792 |
|
|
wait_irq_set(4);
|
793 |
36 |
rehayes |
host.wb_write(1, XGATE_XGIF_0, 16'h0010, WORD);
|
794 |
21 |
rehayes |
|
795 |
94 |
rehayes |
// Test Branch instructions
|
796 |
11 |
rehayes |
activate_thread_sw(5);
|
797 |
|
|
wait_irq_set(5);
|
798 |
36 |
rehayes |
host.wb_write(1, XGATE_XGIF_0, 16'h0020, WORD);
|
799 |
21 |
rehayes |
|
800 |
94 |
rehayes |
// Test Subroutine Call and return instructions
|
801 |
11 |
rehayes |
activate_thread_sw(6);
|
802 |
|
|
wait_irq_set(6);
|
803 |
36 |
rehayes |
host.wb_write(1, XGATE_XGIF_0, 16'h0040, WORD);
|
804 |
21 |
rehayes |
|
805 |
94 |
rehayes |
// Test 16 bit Addition and Substract instructions
|
806 |
11 |
rehayes |
activate_thread_sw(7);
|
807 |
|
|
wait_irq_set(7);
|
808 |
36 |
rehayes |
host.wb_write(1, XGATE_XGIF_0, 16'h0080, WORD);
|
809 |
21 |
rehayes |
|
810 |
94 |
rehayes |
// Test 8 bit Addition and Substract instructions
|
811 |
11 |
rehayes |
activate_thread_sw(8);
|
812 |
|
|
wait_irq_set(8);
|
813 |
36 |
rehayes |
host.wb_write(1, XGATE_XGIF_0, 16'h0100, WORD);
|
814 |
21 |
rehayes |
|
815 |
94 |
rehayes |
// Test Load and Store instructions
|
816 |
11 |
rehayes |
activate_thread_sw(9);
|
817 |
|
|
wait_irq_set(9);
|
818 |
36 |
rehayes |
host.wb_write(1, XGATE_XGIF_0, 16'h0200, WORD);
|
819 |
21 |
rehayes |
|
820 |
94 |
rehayes |
// Test Semaphore instructions
|
821 |
36 |
rehayes |
host.wb_write(1, XGATE_XGSEM, 16'h5050, WORD);
|
822 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGSEM, 16'h0050, WORD); //
|
823 |
11 |
rehayes |
activate_thread_sw(10);
|
824 |
|
|
wait_irq_set(10);
|
825 |
36 |
rehayes |
host.wb_write(1, XGATE_XGIF_0, 16'h0400, WORD);
|
826 |
21 |
rehayes |
|
827 |
36 |
rehayes |
host.wb_write(1, XGATE_XGSEM, 16'hff00, WORD); // clear the old settings
|
828 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGSEM, 16'h0000, WORD); //
|
829 |
36 |
rehayes |
host.wb_write(1, XGATE_XGSEM, 16'ha0a0, WORD); // Verify that bits were unlocked by RISC
|
830 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGSEM, 16'h00a0, WORD); // Verify bits were set
|
831 |
36 |
rehayes |
host.wb_write(1, XGATE_XGSEM, 16'hff08, WORD); // Try to set the bit that was left locked by the RISC
|
832 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGSEM, 16'h0000, WORD); // Verify no bits were set
|
833 |
21 |
rehayes |
|
834 |
11 |
rehayes |
repeat(20) @(posedge mstr_test_clk);
|
835 |
|
|
|
836 |
36 |
rehayes |
p_ram.dump_ram(0);
|
837 |
62 |
rehayes |
|
838 |
89 |
rehayes |
read_ram_cmp(16'h0000, 16'haa55);
|
839 |
|
|
read_ram_cmp(16'h0004, 16'h7faa);
|
840 |
|
|
read_ram_cmp(16'h0006, 16'h6f55);
|
841 |
|
|
read_ram_cmp(16'h000a, 16'h5f66);
|
842 |
|
|
read_ram_cmp(16'h0032, 16'h1fcc);
|
843 |
|
|
read_ram_cmp(16'h0038, 16'h2f99);
|
844 |
|
|
read_ram_cmp(16'h0062, 16'h1faa);
|
845 |
|
|
read_ram_cmp(16'h0068, 16'h2fcc);
|
846 |
|
|
read_ram_cmp(16'h0022, 16'hccxx);
|
847 |
|
|
read_ram_cmp(16'h0026, 16'hxx99);
|
848 |
|
|
read_ram_cmp(16'h0052, 16'hxx66);
|
849 |
|
|
read_ram_cmp(16'h0058, 16'h99xx);
|
850 |
|
|
read_ram_cmp(16'h0080, 16'h9966);
|
851 |
|
|
read_ram_cmp(16'h0086, 16'h7533);
|
852 |
62 |
rehayes |
|
853 |
100 |
rehayes |
// All the tested instructions should have been legal
|
854 |
|
|
if (xg_sw_irq)
|
855 |
|
|
begin
|
856 |
|
|
error_count = error_count + 1;
|
857 |
|
|
$display("SW IRQ active after instruction test, vector=%d", vector);
|
858 |
|
|
clear_sw_irq; // Don't let error state propogate into following tests
|
859 |
|
|
end
|
860 |
|
|
|
861 |
50 |
rehayes |
data_xgmctl = 16'hff00;
|
862 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Disable XGATE
|
863 |
50 |
rehayes |
|
864 |
11 |
rehayes |
end
|
865 |
|
|
endtask
|
866 |
|
|
|
867 |
36 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
868 |
100 |
rehayes |
// check pc rollover error detection
|
869 |
|
|
task pc_rollover;
|
870 |
|
|
integer i, j, k;
|
871 |
|
|
begin
|
872 |
|
|
$readmemh("../../../bench/verilog/pc_rollover.v", p_ram.ram_8);
|
873 |
|
|
test_num = test_num + 1;
|
874 |
|
|
$display("\nTEST #%d Starts at vector=%d, pc_rollover", test_num, vector);
|
875 |
|
|
|
876 |
|
|
data_xgmctl = XGMCTL_XGIEM | XGMCTL_XGIE;
|
877 |
|
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable XGATE SW interrupt for error detection
|
878 |
|
|
|
879 |
|
|
host.wb_write(0, XGATE_XGVBR, 16'h8800, WORD); // set vector table address to match test code
|
880 |
|
|
repeat(4) @(posedge mstr_test_clk);
|
881 |
|
|
|
882 |
|
|
// Enable interrupts to RISC
|
883 |
|
|
host.wb_write(0, IRQ_BYPS_0, 16'h0000, WORD);
|
884 |
|
|
|
885 |
|
|
// Test #1 - single step past the end of memory space
|
886 |
|
|
// Test #2 - branch past the end of memory space
|
887 |
|
|
// Test #3 - branch past the begining of memory space
|
888 |
|
|
for (i = 1; i <= 3; i = i + 1)
|
889 |
|
|
begin
|
890 |
|
|
$display(" -- Subtest %0d Starts at vector = %0d, pc over/underrun", i, vector);
|
891 |
|
|
activate_thread_sw(i);
|
892 |
|
|
|
893 |
|
|
wait_sw_irq_set(8'd100);
|
894 |
|
|
clear_sw_irq;
|
895 |
|
|
channel_req[i] = 1'b0; //
|
896 |
|
|
repeat(1) @(posedge mstr_test_clk);
|
897 |
|
|
host.wb_cmp(0, XGATE_XGMCTL, 16'h00A1, WORD); // verify Debug mode
|
898 |
|
|
data_xgmctl = XGMCTL_XGEM | XGMCTL_XGDBGM; // Clear Debug mode and XGATE Enable
|
899 |
|
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);
|
900 |
|
|
repeat(14) @(posedge mstr_test_clk);
|
901 |
|
|
end
|
902 |
|
|
|
903 |
|
|
|
904 |
|
|
end
|
905 |
|
|
endtask
|
906 |
|
|
|
907 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
908 |
94 |
rehayes |
// Test skipjack encription - test subset of instruction set on a real problem
|
909 |
82 |
rehayes |
task test_skipjack;
|
910 |
|
|
begin
|
911 |
|
|
$readmemh("../../../bench/verilog/skipjack.v", p_ram.ram_8);
|
912 |
|
|
test_num = test_num + 1;
|
913 |
|
|
$display("\nTEST #%d Starts at vector=%d, test_skipjack", test_num, vector);
|
914 |
|
|
repeat(1) @(posedge mstr_test_clk);
|
915 |
89 |
rehayes |
|
916 |
82 |
rehayes |
host.wb_write(0, DEBUG_CNTRL, 16'hFFFF, WORD);
|
917 |
|
|
|
918 |
100 |
rehayes |
host.wb_write(0, XGATE_XGVBR, 16'hFE00, WORD); // set vector table address to match test code
|
919 |
|
|
repeat(4) @(posedge mstr_test_clk);
|
920 |
|
|
|
921 |
82 |
rehayes |
// Enable interrupts to RISC
|
922 |
|
|
host.wb_write(0, IRQ_BYPS_0, 16'h0000, WORD);
|
923 |
|
|
|
924 |
|
|
activate_thread_sw(2);
|
925 |
|
|
wait_irq_set(2);
|
926 |
|
|
host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);
|
927 |
|
|
|
928 |
|
|
|
929 |
|
|
repeat(20) @(posedge mstr_test_clk);
|
930 |
|
|
|
931 |
|
|
p_ram.dump_ram(16'h2000);
|
932 |
|
|
// repeat(2) @(posedge mstr_test_clk);
|
933 |
|
|
// p_ram.dump_ram(16'h9000);
|
934 |
|
|
|
935 |
|
|
data_xgmctl = 16'hff00;
|
936 |
89 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Disable XGATE
|
937 |
82 |
rehayes |
|
938 |
|
|
end
|
939 |
|
|
endtask
|
940 |
|
|
|
941 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
942 |
2 |
rehayes |
// check register bits - reset, read/write
|
943 |
|
|
task reg_test_16;
|
944 |
|
|
begin
|
945 |
65 |
rehayes |
test_num = test_num + 1;
|
946 |
|
|
$display("\nTEST #%d Starts at vector=%d, reg_test_16", test_num, vector);
|
947 |
41 |
rehayes |
|
948 |
65 |
rehayes |
system_reset;
|
949 |
2 |
rehayes |
|
950 |
89 |
rehayes |
host.wb_cmp(0, XGATE_XGMCTL, 16'h0000, WORD); // verify reset
|
951 |
|
|
host.wb_cmp(0, XGATE_XGCHID, 16'h0000, WORD); // verify reset
|
952 |
|
|
host.wb_cmp(0, XGATE_XGISPHI, 16'h0000, WORD); // verify reset
|
953 |
|
|
host.wb_cmp(0, XGATE_XGISPLO, 16'h0000, WORD); // verify reset
|
954 |
|
|
host.wb_cmp(0, XGATE_XGVBR, 16'hfe00, WORD); // verify reset
|
955 |
|
|
host.wb_cmp(0, XGATE_XGIF_7, 16'h0000, WORD); // verify reset
|
956 |
|
|
host.wb_cmp(0, XGATE_XGIF_6, 16'h0000, WORD); // verify reset
|
957 |
|
|
host.wb_cmp(0, XGATE_XGIF_5, 16'h0000, WORD); // verify reset
|
958 |
|
|
host.wb_cmp(0, XGATE_XGIF_4, 16'h0000, WORD); // verify reset
|
959 |
|
|
host.wb_cmp(0, XGATE_XGIF_3, 16'h0000, WORD); // verify reset
|
960 |
|
|
host.wb_cmp(0, XGATE_XGIF_2, 16'h0000, WORD); // verify reset
|
961 |
|
|
host.wb_cmp(0, XGATE_XGIF_1, 16'h0000, WORD); // verify reset
|
962 |
|
|
host.wb_cmp(0, XGATE_XGIF_0, 16'h0000, WORD); // verify reset
|
963 |
|
|
host.wb_cmp(0, XGATE_XGSWT, 16'h0000, WORD); // verify reset
|
964 |
|
|
host.wb_cmp(0, XGATE_XGSEM, 16'h0000, WORD); // verify reset
|
965 |
|
|
host.wb_cmp(0, XGATE_XGCCR, 16'h0000, WORD); // verify reset
|
966 |
|
|
host.wb_cmp(0, XGATE_XGPC, 16'h0000, WORD); // verify reset
|
967 |
|
|
host.wb_cmp(0, XGATE_XGR1, 16'h0000, WORD); // verify reset
|
968 |
|
|
host.wb_cmp(0, XGATE_XGR2, 16'h0000, WORD); // verify reset
|
969 |
|
|
host.wb_cmp(0, XGATE_XGR3, 16'h0000, WORD); // verify reset
|
970 |
|
|
host.wb_cmp(0, XGATE_XGR4, 16'h0000, WORD); // verify reset
|
971 |
|
|
host.wb_cmp(0, XGATE_XGR5, 16'h0000, WORD); // verify reset
|
972 |
|
|
host.wb_cmp(0, XGATE_XGR6, 16'h0000, WORD); // verify reset
|
973 |
|
|
host.wb_cmp(0, XGATE_XGR7, 16'h0000, WORD); // verify reset
|
974 |
62 |
rehayes |
|
975 |
89 |
rehayes |
// Test bits in the Xgate Control Register (XGMCTL)
|
976 |
65 |
rehayes |
data_xgmctl = XGMCTL_XGEM | XGMCTL_XGFRZM | XGMCTL_XGFACTM | XGMCTL_XGFRZ | XGMCTL_XGFACT | XGMCTL_XGE;
|
977 |
|
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); //
|
978 |
|
|
data_xgmctl = XGMCTL_XGFRZ | XGMCTL_XGFACT | XGMCTL_XGE;
|
979 |
|
|
host.wb_cmp( 0, XGATE_XGMCTL, data_xgmctl, WORD);
|
980 |
2 |
rehayes |
|
981 |
65 |
rehayes |
data_xgmctl = XGMCTL_XGEM;
|
982 |
|
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); //
|
983 |
|
|
data_xgmctl = XGMCTL_XGFRZ | XGMCTL_XGFACT;
|
984 |
|
|
host.wb_cmp( 0, XGATE_XGMCTL, data_xgmctl, WORD);
|
985 |
2 |
rehayes |
|
986 |
65 |
rehayes |
data_xgmctl = XGMCTL_XGFRZM | XGMCTL_XGFACTM;
|
987 |
|
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); //
|
988 |
|
|
data_xgmctl = 16'h0000;
|
989 |
|
|
host.wb_cmp( 0, XGATE_XGMCTL, data_xgmctl, WORD);
|
990 |
41 |
rehayes |
|
991 |
65 |
rehayes |
data_xgmctl = 16'hffff;
|
992 |
94 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, H_BYTE); //
|
993 |
65 |
rehayes |
data_xgmctl = 16'h0000;
|
994 |
|
|
host.wb_cmp( 0, XGATE_XGMCTL, data_xgmctl, WORD);
|
995 |
41 |
rehayes |
|
996 |
65 |
rehayes |
data_xgmctl = 16'hffff;
|
997 |
94 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, L_BYTE); //
|
998 |
65 |
rehayes |
data_xgmctl = 16'h0000;
|
999 |
|
|
host.wb_cmp( 0, XGATE_XGMCTL, data_xgmctl, WORD);
|
1000 |
41 |
rehayes |
|
1001 |
65 |
rehayes |
// Test the Xgate Vector Base Address Register (XGVBR)
|
1002 |
|
|
host.wb_write(0, XGATE_XGVBR, 16'h5555, WORD);
|
1003 |
|
|
host.wb_cmp(0, XGATE_XGVBR, 16'h5554, WORD);
|
1004 |
41 |
rehayes |
|
1005 |
65 |
rehayes |
host.wb_write(0, XGATE_XGVBR, 16'hAAAA, WORD);
|
1006 |
|
|
host.wb_cmp(0, XGATE_XGVBR, 16'hAAAA, WORD);
|
1007 |
41 |
rehayes |
|
1008 |
65 |
rehayes |
host.wb_write(0, XGATE_XGVBR, 16'hFF55, L_BYTE);
|
1009 |
|
|
host.wb_cmp(0, XGATE_XGVBR, 16'hAA54, WORD);
|
1010 |
62 |
rehayes |
|
1011 |
65 |
rehayes |
host.wb_write(0, XGATE_XGVBR, 16'h55AA, H_BYTE);
|
1012 |
|
|
host.wb_cmp(0, XGATE_XGVBR, 16'h5554, WORD);
|
1013 |
62 |
rehayes |
|
1014 |
65 |
rehayes |
data_xgmctl = XGMCTL_XGEM | XGMCTL_XGE;
|
1015 |
|
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); //
|
1016 |
|
|
data_xgmctl = XGMCTL_XGE;
|
1017 |
|
|
host.wb_cmp( 0, XGATE_XGMCTL, data_xgmctl, WORD);
|
1018 |
|
|
host.wb_write(0, XGATE_XGVBR, 16'hFFFF, WORD);
|
1019 |
|
|
host.wb_cmp(0, XGATE_XGVBR, 16'h5554, WORD);
|
1020 |
41 |
rehayes |
|
1021 |
65 |
rehayes |
data_xgmctl = XGMCTL_XGEM;
|
1022 |
|
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); //
|
1023 |
41 |
rehayes |
|
1024 |
65 |
rehayes |
// Test the Xgate Software Trigger Register (XGSWT)
|
1025 |
|
|
host.wb_write(0, XGATE_XGSWT, 16'hFFFF, WORD);
|
1026 |
|
|
host.wb_cmp(0, XGATE_XGSWT, 16'h00FF, WORD);
|
1027 |
|
|
host.wb_write(0, XGATE_XGSWT, 16'hFF00, WORD);
|
1028 |
|
|
host.wb_cmp(0, XGATE_XGSWT, 16'h0000, WORD);
|
1029 |
41 |
rehayes |
|
1030 |
65 |
rehayes |
host.wb_write(0, XGATE_XGSWT, 16'hFF55, L_BYTE);
|
1031 |
|
|
host.wb_cmp(0, XGATE_XGSWT, 16'h0000, WORD);
|
1032 |
|
|
host.wb_write(0, XGATE_XGSWT, 16'hFF55, H_BYTE);
|
1033 |
|
|
host.wb_cmp(0, XGATE_XGSWT, 16'h0000, WORD);
|
1034 |
41 |
rehayes |
|
1035 |
65 |
rehayes |
// Test the Xgate Semaphore Register (XGSEM)
|
1036 |
|
|
host.wb_write(0, XGATE_XGSEM, 16'hFFFF, WORD);
|
1037 |
|
|
host.wb_cmp(0, XGATE_XGSEM, 16'h00FF, WORD);
|
1038 |
|
|
host.wb_write(0, XGATE_XGSEM, 16'hFF00, WORD);
|
1039 |
|
|
host.wb_cmp(0, XGATE_XGSEM, 16'h0000, WORD);
|
1040 |
41 |
rehayes |
|
1041 |
65 |
rehayes |
host.wb_write(0, XGATE_XGSEM, 16'hFFFF, L_BYTE);
|
1042 |
|
|
host.wb_cmp(0, XGATE_XGSEM, 16'h0000, WORD);
|
1043 |
|
|
host.wb_write(0, XGATE_XGSEM, 16'hFFFF, H_BYTE);
|
1044 |
|
|
host.wb_cmp(0, XGATE_XGSEM, 16'h0000, WORD);
|
1045 |
41 |
rehayes |
|
1046 |
65 |
rehayes |
// Test the Xgate Condition Code Register (XGCCR)
|
1047 |
|
|
host.wb_write(0, XGATE_XGCCR, 16'hFFFF, L_BYTE);
|
1048 |
|
|
host.wb_cmp(0, XGATE_XGCCR, 16'h000F, WORD);
|
1049 |
|
|
host.wb_write(0, XGATE_XGCCR, 16'hFFF0, WORD);
|
1050 |
|
|
host.wb_cmp(0, XGATE_XGCCR, 16'h0000, WORD);
|
1051 |
41 |
rehayes |
|
1052 |
65 |
rehayes |
// Test the Xgate Program Counter Register (XGPC)
|
1053 |
|
|
host.wb_write(0, XGATE_XGPC, 16'hFF55, L_BYTE);
|
1054 |
|
|
host.wb_cmp(0, XGATE_XGPC, 16'h0055, WORD);
|
1055 |
|
|
host.wb_write(0, XGATE_XGPC, 16'hAAFF, H_BYTE);
|
1056 |
|
|
host.wb_cmp(0, XGATE_XGPC, 16'hAA55, WORD);
|
1057 |
|
|
host.wb_write(0, XGATE_XGPC, 16'h9966, WORD);
|
1058 |
|
|
host.wb_cmp(0, XGATE_XGPC, 16'h9966, WORD);
|
1059 |
41 |
rehayes |
|
1060 |
65 |
rehayes |
// Test the Xgate Register #1 (XGR1)
|
1061 |
|
|
host.wb_write(0, XGATE_XGR1, 16'hFF33, L_BYTE);
|
1062 |
|
|
host.wb_cmp(0, XGATE_XGR1, 16'h0033, WORD);
|
1063 |
|
|
host.wb_write(0, XGATE_XGR1, 16'hccFF, H_BYTE);
|
1064 |
|
|
host.wb_cmp(0, XGATE_XGR1, 16'hcc33, WORD);
|
1065 |
|
|
host.wb_write(0, XGATE_XGR1, 16'hf11f, WORD);
|
1066 |
|
|
host.wb_cmp(0, XGATE_XGR1, 16'hf11f, WORD);
|
1067 |
41 |
rehayes |
|
1068 |
65 |
rehayes |
// Test the Xgate Register #2 (XGR2)
|
1069 |
|
|
host.wb_write(0, XGATE_XGR2, 16'hFF11, L_BYTE);
|
1070 |
|
|
host.wb_cmp(0, XGATE_XGR2, 16'h0011, WORD);
|
1071 |
|
|
host.wb_write(0, XGATE_XGR2, 16'h22FF, H_BYTE);
|
1072 |
|
|
host.wb_cmp(0, XGATE_XGR2, 16'h2211, WORD);
|
1073 |
|
|
host.wb_write(0, XGATE_XGR2, 16'hddee, WORD);
|
1074 |
|
|
host.wb_cmp(0, XGATE_XGR2, 16'hddee, WORD);
|
1075 |
41 |
rehayes |
|
1076 |
65 |
rehayes |
// Test the Xgate Register #3 (XGR3)
|
1077 |
|
|
host.wb_write(0, XGATE_XGR3, 16'hFF43, L_BYTE);
|
1078 |
|
|
host.wb_cmp(0, XGATE_XGR3, 16'h0043, WORD);
|
1079 |
|
|
host.wb_write(0, XGATE_XGR3, 16'h54FF, H_BYTE);
|
1080 |
|
|
host.wb_cmp(0, XGATE_XGR3, 16'h5443, WORD);
|
1081 |
|
|
host.wb_write(0, XGATE_XGR3, 16'habbc, WORD);
|
1082 |
|
|
host.wb_cmp(0, XGATE_XGR3, 16'habbc, WORD);
|
1083 |
41 |
rehayes |
|
1084 |
65 |
rehayes |
// Test the Xgate Register #4 (XGR4)
|
1085 |
|
|
host.wb_write(0, XGATE_XGR4, 16'hFF54, L_BYTE);
|
1086 |
|
|
host.wb_cmp(0, XGATE_XGR4, 16'h0054, WORD);
|
1087 |
|
|
host.wb_write(0, XGATE_XGR4, 16'h65FF, H_BYTE);
|
1088 |
|
|
host.wb_cmp(0, XGATE_XGR4, 16'h6554, WORD);
|
1089 |
|
|
host.wb_write(0, XGATE_XGR4, 16'h9aab, WORD);
|
1090 |
|
|
host.wb_cmp(0, XGATE_XGR4, 16'h9aab, WORD);
|
1091 |
41 |
rehayes |
|
1092 |
65 |
rehayes |
// Test the Xgate Register #5 (XGR5)
|
1093 |
|
|
host.wb_write(0, XGATE_XGR5, 16'hFF65, L_BYTE);
|
1094 |
|
|
host.wb_cmp(0, XGATE_XGR5, 16'h0065, WORD);
|
1095 |
|
|
host.wb_write(0, XGATE_XGR5, 16'h76FF, H_BYTE);
|
1096 |
|
|
host.wb_cmp(0, XGATE_XGR5, 16'h7665, WORD);
|
1097 |
|
|
host.wb_write(0, XGATE_XGR5, 16'h899a, WORD);
|
1098 |
|
|
host.wb_cmp(0, XGATE_XGR5, 16'h899a, WORD);
|
1099 |
41 |
rehayes |
|
1100 |
65 |
rehayes |
// Test the Xgate Register #6 (XGR6)
|
1101 |
|
|
host.wb_write(0, XGATE_XGR6, 16'hFF76, L_BYTE);
|
1102 |
|
|
host.wb_cmp(0, XGATE_XGR6, 16'h0076, WORD);
|
1103 |
|
|
host.wb_write(0, XGATE_XGR6, 16'h87FF, H_BYTE);
|
1104 |
|
|
host.wb_cmp(0, XGATE_XGR6, 16'h8776, WORD);
|
1105 |
|
|
host.wb_write(0, XGATE_XGR6, 16'h7889, WORD);
|
1106 |
|
|
host.wb_cmp(0, XGATE_XGR6, 16'h7889, WORD);
|
1107 |
41 |
rehayes |
|
1108 |
65 |
rehayes |
// Test the Xgate Register #7 (XGR7)
|
1109 |
|
|
host.wb_write(0, XGATE_XGR7, 16'hFF87, L_BYTE);
|
1110 |
|
|
host.wb_cmp(0, XGATE_XGR7, 16'h0087, WORD);
|
1111 |
|
|
host.wb_write(0, XGATE_XGR7, 16'h98FF, H_BYTE);
|
1112 |
|
|
host.wb_cmp(0, XGATE_XGR7, 16'h9887, WORD);
|
1113 |
|
|
host.wb_write(0, XGATE_XGR7, 16'h6778, WORD);
|
1114 |
|
|
host.wb_cmp(0, XGATE_XGR7, 16'h6778, WORD);
|
1115 |
41 |
rehayes |
|
1116 |
65 |
rehayes |
host.wb_cmp(0, XGATE_XGPC, 16'h9966, WORD);
|
1117 |
|
|
host.wb_cmp(0, XGATE_XGR1, 16'hf11f, WORD);
|
1118 |
|
|
host.wb_cmp(0, XGATE_XGR2, 16'hddee, WORD);
|
1119 |
|
|
host.wb_cmp(0, XGATE_XGR3, 16'habbc, WORD);
|
1120 |
|
|
host.wb_cmp(0, XGATE_XGR4, 16'h9aab, WORD);
|
1121 |
|
|
host.wb_cmp(0, XGATE_XGR5, 16'h899a, WORD);
|
1122 |
|
|
host.wb_cmp(0, XGATE_XGR6, 16'h7889, WORD);
|
1123 |
|
|
host.wb_cmp(0, XGATE_XGR7, 16'h6778, WORD);
|
1124 |
41 |
rehayes |
|
1125 |
2 |
rehayes |
end
|
1126 |
|
|
endtask
|
1127 |
|
|
|
1128 |
68 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
1129 |
73 |
rehayes |
// check irq register bits - reset, read/write
|
1130 |
68 |
rehayes |
task reg_irq;
|
1131 |
94 |
rehayes |
integer i, j, k;
|
1132 |
|
|
reg [15:0] irq_clear;
|
1133 |
|
|
reg [TB_ADDR_WIDTH-1:0] irq_ack_addr; // Address to clear irq request
|
1134 |
68 |
rehayes |
begin
|
1135 |
|
|
test_num = test_num + 1;
|
1136 |
|
|
$display("\nTEST #%d Starts at vector=%d, reg_irq", test_num, vector);
|
1137 |
|
|
$readmemh("../../../bench/verilog/irq_test.v", p_ram.ram_8);
|
1138 |
2 |
rehayes |
|
1139 |
68 |
rehayes |
system_reset;
|
1140 |
|
|
|
1141 |
89 |
rehayes |
host.wb_cmp(0, IRQ_BYPS_0, 16'hFFFE, WORD); // verify reset
|
1142 |
|
|
host.wb_cmp(0, IRQ_BYPS_1, 16'hFFFF, WORD); // verify reset
|
1143 |
|
|
host.wb_cmp(0, IRQ_BYPS_2, 16'hFFFF, WORD); // verify reset
|
1144 |
|
|
host.wb_cmp(0, IRQ_BYPS_3, 16'hFFFF, WORD); // verify reset
|
1145 |
|
|
host.wb_cmp(0, IRQ_BYPS_4, 16'hFFFF, WORD); // verify reset
|
1146 |
|
|
host.wb_cmp(0, IRQ_BYPS_5, 16'hFFFF, WORD); // verify reset
|
1147 |
|
|
host.wb_cmp(0, IRQ_BYPS_6, 16'hFFFF, WORD); // verify reset
|
1148 |
|
|
host.wb_cmp(0, IRQ_BYPS_7, 16'hFFFF, WORD); // verify reset
|
1149 |
68 |
rehayes |
|
1150 |
|
|
|
1151 |
|
|
// Test the Xgate IRQ Bypass Registers (IRQ_BYPS)
|
1152 |
|
|
host.wb_write(0, IRQ_BYPS_0, 16'hAAAA, WORD);
|
1153 |
|
|
host.wb_cmp(0, IRQ_BYPS_0, 16'hAAAA, WORD);
|
1154 |
|
|
host.wb_write(0, IRQ_BYPS_0, 16'h5555, WORD);
|
1155 |
73 |
rehayes |
host.wb_cmp(0, IRQ_BYPS_0, 16'h5554, WORD);
|
1156 |
68 |
rehayes |
|
1157 |
|
|
host.wb_write(0, IRQ_BYPS_0, 16'hFF66, L_BYTE);
|
1158 |
|
|
host.wb_cmp(0, IRQ_BYPS_0, 16'h5566, WORD);
|
1159 |
|
|
host.wb_write(0, IRQ_BYPS_0, 16'h33FF, H_BYTE);
|
1160 |
|
|
host.wb_cmp(0, IRQ_BYPS_0, 16'h3366, WORD);
|
1161 |
|
|
host.wb_write(0, IRQ_BYPS_0, 16'hFFFF, H_BYTE);
|
1162 |
|
|
|
1163 |
|
|
channel_req[17] = 1'b1; //
|
1164 |
|
|
repeat(4) @(posedge mstr_test_clk);
|
1165 |
|
|
host.wb_cmp(0, CHANNEL_XGIRQ_1, 16'h0002, WORD);
|
1166 |
|
|
channel_req[17] = 1'b0; //
|
1167 |
|
|
repeat(4) @(posedge mstr_test_clk);
|
1168 |
|
|
host.wb_cmp(0, CHANNEL_XGIRQ_1, 16'h0000, WORD);
|
1169 |
|
|
|
1170 |
94 |
rehayes |
host.wb_write(0, TB_SEMPHORE, 16'h0000, WORD);
|
1171 |
68 |
rehayes |
host.wb_write(0, IRQ_BYPS_0, 16'h0000, WORD);
|
1172 |
94 |
rehayes |
host.wb_write(0, IRQ_BYPS_1, 16'h0000, WORD);
|
1173 |
|
|
host.wb_write(0, IRQ_BYPS_2, 16'h0000, WORD);
|
1174 |
|
|
host.wb_write(0, IRQ_BYPS_3, 16'h0000, WORD);
|
1175 |
|
|
host.wb_write(0, IRQ_BYPS_4, 16'h0000, WORD);
|
1176 |
|
|
host.wb_write(0, IRQ_BYPS_5, 16'h0000, WORD);
|
1177 |
|
|
host.wb_write(0, IRQ_BYPS_6, 16'h0000, WORD);
|
1178 |
|
|
host.wb_write(0, IRQ_BYPS_7, 16'h0000, WORD);
|
1179 |
68 |
rehayes |
data_xgmctl = XGMCTL_XGEM | XGMCTL_XGE;
|
1180 |
|
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable XGATE
|
1181 |
|
|
repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
|
1182 |
|
|
|
1183 |
94 |
rehayes |
//channel_req[8:1] = 8'b1_1111_111; // Activate the interrupt inputs
|
1184 |
|
|
channel_req = {MAX_CHANNEL{1'b1}}; // Activate the interrupt inputs
|
1185 |
89 |
rehayes |
|
1186 |
94 |
rehayes |
for (i = 1; i <= MAX_CHANNEL; i = i + 1)
|
1187 |
|
|
begin
|
1188 |
|
|
j = i % 16;
|
1189 |
|
|
k = i / 16;
|
1190 |
|
|
irq_ack_addr = XGATE_XGIF_0 - (2 * k);
|
1191 |
|
|
$display("Testing interrupt %d.", i);
|
1192 |
|
|
q = 0;
|
1193 |
|
|
// The Xgate test program is in an infinite loop looking for the test bench semaphore register to be changed
|
1194 |
|
|
while (q == 0) // Look for change in test bench semapore register
|
1195 |
|
|
begin
|
1196 |
|
|
host.wb_read(1, TB_SEMPHORE, q, WORD);
|
1197 |
|
|
end
|
1198 |
89 |
rehayes |
|
1199 |
94 |
rehayes |
if (q != i)
|
1200 |
|
|
begin
|
1201 |
|
|
error_count = error_count + 1;
|
1202 |
|
|
$display("IRQ test failure, Wrong interrupt being processed! Interrupt=%d, vector=%d", q, vector);
|
1203 |
|
|
end
|
1204 |
68 |
rehayes |
|
1205 |
94 |
rehayes |
channel_req[i] = 1'b0; // Clear the active interrupt input
|
1206 |
|
|
repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
|
1207 |
|
|
host.wb_write(0, TB_SEMPHORE, 16'h0000, WORD);
|
1208 |
|
|
repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
|
1209 |
89 |
rehayes |
|
1210 |
94 |
rehayes |
irq_clear = 16'h0001 << j;
|
1211 |
|
|
// host.wb_cmp(0, CHANNEL_XGIRQ_0, irq_clear, WORD); // Verify Xgate output interrupt flag set
|
1212 |
|
|
// host.wb_cmp(0, XGATE_XGIF_0, irq_clear, WORD); // Verify Xgate interrupt status bit set
|
1213 |
|
|
host.wb_write(1, irq_ack_addr, irq_clear, WORD); // Clear Interrupt Flag from Xgate
|
1214 |
|
|
// host.wb_cmp(0, XGATE_XGIF_0, 16'h0000, WORD); // Verify flag cleared
|
1215 |
|
|
end
|
1216 |
89 |
rehayes |
|
1217 |
94 |
rehayes |
end
|
1218 |
|
|
endtask // reg_irq
|
1219 |
89 |
rehayes |
|
1220 |
|
|
|
1221 |
94 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
1222 |
|
|
task sync_reset_test; // reset system
|
1223 |
|
|
begin
|
1224 |
|
|
test_num = test_num + 1;
|
1225 |
|
|
$display("\nTEST #%d Starts at vector=%d, reg_irq", test_num, vector);
|
1226 |
89 |
rehayes |
|
1227 |
94 |
rehayes |
// Write some registers so a change in state can be verified after reset
|
1228 |
|
|
host.wb_write(1, XGATE_XGVBR, 16'h01ff, WORD); //
|
1229 |
|
|
host.wb_write(0, IRQ_BYPS_0, 16'h0000, WORD);
|
1230 |
89 |
rehayes |
|
1231 |
94 |
rehayes |
repeat(1) @(posedge mstr_test_clk);
|
1232 |
|
|
sync_reset <= 1'b1; //
|
1233 |
|
|
repeat(1) @(posedge mstr_test_clk);
|
1234 |
|
|
sync_reset <= 1'b0;
|
1235 |
89 |
rehayes |
|
1236 |
94 |
rehayes |
host.wb_cmp(0, XGATE_XGVBR, 16'hfe00, WORD); // verify reset
|
1237 |
|
|
host.wb_cmp(0, IRQ_BYPS_0, 16'hFFFE, WORD); // verify reset
|
1238 |
89 |
rehayes |
|
1239 |
68 |
rehayes |
end
|
1240 |
|
|
endtask
|
1241 |
|
|
|
1242 |
|
|
|
1243 |
36 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
1244 |
94 |
rehayes |
// End Main test program tasks
|
1245 |
|
|
// Begin test program helper tasks and functions
|
1246 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
1247 |
|
|
|
1248 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
1249 |
36 |
rehayes |
// check RAM Read/Write from host
|
1250 |
|
|
task host_ram;
|
1251 |
|
|
begin
|
1252 |
|
|
test_num = test_num + 1;
|
1253 |
65 |
rehayes |
$display("\nTEST #%d Starts at vector=%d, host_ram", test_num, vector);
|
1254 |
36 |
rehayes |
|
1255 |
|
|
host.wb_write(1, SYS_RAM_BASE, 16'h5555, WORD);
|
1256 |
|
|
host.wb_cmp( 0, SYS_RAM_BASE, 16'h5555, WORD);
|
1257 |
|
|
|
1258 |
|
|
repeat(5) @(posedge mstr_test_clk);
|
1259 |
|
|
p_ram.dump_ram(0);
|
1260 |
|
|
|
1261 |
|
|
end
|
1262 |
|
|
endtask
|
1263 |
|
|
|
1264 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
1265 |
11 |
rehayes |
// Poll for XGATE Interrupt set
|
1266 |
|
|
task wait_irq_set;
|
1267 |
|
|
input [ 6:0] chan_val;
|
1268 |
|
|
begin
|
1269 |
|
|
while(!xgif[chan_val])
|
1270 |
|
|
@(posedge mstr_test_clk); // poll it until it is set
|
1271 |
|
|
$display("XGATE Interrupt Request #%d set detected at vector =%d", chan_val, vector);
|
1272 |
|
|
end
|
1273 |
|
|
endtask
|
1274 |
2 |
rehayes |
|
1275 |
36 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
1276 |
100 |
rehayes |
// Poll for XGATE SW Interrupt set
|
1277 |
|
|
task wait_sw_irq_set;
|
1278 |
|
|
input [ 7:0] wait_timeout;
|
1279 |
|
|
reg [7:0]timeout_count;
|
1280 |
|
|
begin
|
1281 |
|
|
timeout_count = 0;
|
1282 |
|
|
while(!xg_sw_irq & (timeout_count <= wait_timeout))
|
1283 |
|
|
begin
|
1284 |
|
|
@(posedge mstr_test_clk); // poll it until it is set
|
1285 |
|
|
timeout_count = timeout_count + 1;
|
1286 |
|
|
end
|
1287 |
|
|
|
1288 |
|
|
if (timeout_count >= wait_timeout)
|
1289 |
|
|
begin
|
1290 |
|
|
error_count = error_count + 1;
|
1291 |
|
|
$display("SW IRQ not detected in the alloted time, vector=%d", vector);
|
1292 |
|
|
end
|
1293 |
|
|
else
|
1294 |
|
|
$display("XGATE SW Interrupt Request set detected at vector =%d", vector);
|
1295 |
|
|
|
1296 |
|
|
end
|
1297 |
|
|
endtask
|
1298 |
|
|
|
1299 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
1300 |
|
|
// Clear XGATE SW Interrupt
|
1301 |
|
|
task clear_sw_irq;
|
1302 |
|
|
begin
|
1303 |
|
|
host.wb_write(0, XGATE_XGMCTL, 16'h0202, WORD); // Clear SW interrupt
|
1304 |
|
|
repeat(4) @(posedge mstr_test_clk);
|
1305 |
|
|
if (xg_sw_irq)
|
1306 |
|
|
begin
|
1307 |
|
|
error_count = error_count + 1;
|
1308 |
|
|
$display("SW IRQ not cleared after command write, vector=%d", vector);
|
1309 |
|
|
end
|
1310 |
|
|
|
1311 |
|
|
end
|
1312 |
|
|
endtask
|
1313 |
|
|
|
1314 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
1315 |
11 |
rehayes |
// Poll for debug bit set
|
1316 |
|
|
task wait_debug_set;
|
1317 |
|
|
begin
|
1318 |
36 |
rehayes |
host.wb_read(1, XGATE_XGMCTL, q, WORD);
|
1319 |
11 |
rehayes |
while(~|(q & XGMCTL_XGDBG))
|
1320 |
36 |
rehayes |
host.wb_read(1, XGATE_XGMCTL, q, WORD); // poll it until it is set
|
1321 |
11 |
rehayes |
$display("DEBUG Flag set detected at vector =%d", vector);
|
1322 |
|
|
end
|
1323 |
|
|
endtask
|
1324 |
2 |
rehayes |
|
1325 |
11 |
rehayes |
|
1326 |
36 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
1327 |
2 |
rehayes |
task system_reset; // reset system
|
1328 |
|
|
begin
|
1329 |
89 |
rehayes |
repeat(1) @(posedge mstr_test_clk);
|
1330 |
|
|
#2; // move the async reset away from the clock edge
|
1331 |
|
|
rstn = 1'b0; // assert async reset
|
1332 |
|
|
#5; // Keep the async reset pulse with less than a clock cycle
|
1333 |
|
|
rstn = 1'b1; // negate async reset
|
1334 |
|
|
repeat(1) @(posedge mstr_test_clk);
|
1335 |
2 |
rehayes |
|
1336 |
89 |
rehayes |
$display("\nstatus: %t System Reset Task Done", $time);
|
1337 |
|
|
test_num = test_num + 1;
|
1338 |
94 |
rehayes |
channel_req = 0; // Clear all the testbench inpterrupt inputs to the xgate
|
1339 |
2 |
rehayes |
|
1340 |
89 |
rehayes |
repeat(2) @(posedge mstr_test_clk);
|
1341 |
|
|
end
|
1342 |
2 |
rehayes |
endtask
|
1343 |
|
|
|
1344 |
|
|
|
1345 |
36 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
1346 |
2 |
rehayes |
task activate_channel;
|
1347 |
|
|
input [ 6:0] chan_val;
|
1348 |
|
|
begin
|
1349 |
21 |
rehayes |
$display("Activating Channel %d", chan_val);
|
1350 |
2 |
rehayes |
|
1351 |
21 |
rehayes |
channel_req[chan_val] = 1'b1; //
|
1352 |
|
|
repeat(1) @(posedge mstr_test_clk);
|
1353 |
2 |
rehayes |
end
|
1354 |
|
|
endtask
|
1355 |
|
|
|
1356 |
|
|
|
1357 |
36 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
1358 |
2 |
rehayes |
task clear_channel;
|
1359 |
|
|
input [ 6:0] chan_val;
|
1360 |
|
|
begin
|
1361 |
21 |
rehayes |
$display("Clearing Channel interrupt input #%d", chan_val);
|
1362 |
2 |
rehayes |
|
1363 |
21 |
rehayes |
channel_req[chan_val] = 1'b0; //
|
1364 |
|
|
repeat(1) @(posedge mstr_test_clk);
|
1365 |
|
|
end
|
1366 |
2 |
rehayes |
endtask
|
1367 |
|
|
|
1368 |
|
|
|
1369 |
36 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
1370 |
2 |
rehayes |
task activate_thread_sw;
|
1371 |
|
|
input [ 6:0] chan_val;
|
1372 |
|
|
begin
|
1373 |
50 |
rehayes |
$display("Activating Software Thread - Channel #%d", chan_val);
|
1374 |
2 |
rehayes |
|
1375 |
11 |
rehayes |
data_xgmctl = XGMCTL_XGEM | XGMCTL_XGE;
|
1376 |
36 |
rehayes |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable XGATE
|
1377 |
2 |
rehayes |
|
1378 |
21 |
rehayes |
channel_req[chan_val] = 1'b1; //
|
1379 |
2 |
rehayes |
repeat(1) @(posedge mstr_test_clk);
|
1380 |
|
|
end
|
1381 |
|
|
endtask
|
1382 |
|
|
|
1383 |
36 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
1384 |
41 |
rehayes |
task read_ram_cmp;
|
1385 |
|
|
input [15:0] address;
|
1386 |
|
|
input [15:0] value;
|
1387 |
89 |
rehayes |
reg [15:0] q;
|
1388 |
41 |
rehayes |
begin
|
1389 |
|
|
|
1390 |
|
|
// BIGENDIAN
|
1391 |
|
|
q = {p_ram.ram_8[address], p_ram.ram_8[address+1]};
|
1392 |
|
|
// "X" compares don't work, "X" in value or q always match
|
1393 |
|
|
if (value != q)
|
1394 |
89 |
rehayes |
begin
|
1395 |
|
|
error_count = error_count + 1;
|
1396 |
|
|
$display("RAM Data compare error at address %h. Received %h, expected %h at time %t", address, q, value, $time);
|
1397 |
|
|
end
|
1398 |
41 |
rehayes |
end
|
1399 |
|
|
endtask
|
1400 |
|
|
|
1401 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
1402 |
5 |
rehayes |
task wrap_up;
|
1403 |
|
|
begin
|
1404 |
21 |
rehayes |
test_num = test_num + 1;
|
1405 |
|
|
repeat(10) @(posedge mstr_test_clk);
|
1406 |
5 |
rehayes |
$display("\nSimulation Finished!! - vector =%d", vector);
|
1407 |
|
|
if (error_count == 0)
|
1408 |
|
|
$display("Simulation Passed");
|
1409 |
|
|
else
|
1410 |
21 |
rehayes |
$display("Simulation Failed --- Errors =%d", error_count);
|
1411 |
5 |
rehayes |
|
1412 |
|
|
$finish;
|
1413 |
|
|
end
|
1414 |
|
|
endtask
|
1415 |
|
|
|
1416 |
36 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
1417 |
2 |
rehayes |
function [15:0] four_2_16;
|
1418 |
|
|
input [3:0] vector;
|
1419 |
|
|
begin
|
1420 |
|
|
case (vector)
|
1421 |
|
|
4'h0 : four_2_16 = 16'b0000_0000_0000_0001;
|
1422 |
|
|
4'h1 : four_2_16 = 16'b0000_0000_0000_0010;
|
1423 |
|
|
4'h2 : four_2_16 = 16'b0000_0000_0000_0100;
|
1424 |
|
|
4'h3 : four_2_16 = 16'b0000_0000_0000_1000;
|
1425 |
|
|
4'h4 : four_2_16 = 16'b0000_0000_0001_0000;
|
1426 |
|
|
4'h5 : four_2_16 = 16'b0000_0000_0010_0000;
|
1427 |
|
|
4'h6 : four_2_16 = 16'b0000_0000_0100_0000;
|
1428 |
|
|
4'h7 : four_2_16 = 16'b0000_0000_1000_0000;
|
1429 |
|
|
4'h8 : four_2_16 = 16'b0000_0001_0000_0000;
|
1430 |
|
|
4'h9 : four_2_16 = 16'b0000_0010_0000_0000;
|
1431 |
|
|
4'ha : four_2_16 = 16'b0000_0100_0000_0000;
|
1432 |
|
|
4'hb : four_2_16 = 16'b0000_1000_0000_0000;
|
1433 |
|
|
4'hc : four_2_16 = 16'b0001_0000_0000_0000;
|
1434 |
|
|
4'hd : four_2_16 = 16'b0010_0000_0000_0000;
|
1435 |
|
|
4'he : four_2_16 = 16'b0100_0000_0000_0000;
|
1436 |
|
|
4'hf : four_2_16 = 16'b1000_0000_0000_0000;
|
1437 |
|
|
endcase
|
1438 |
|
|
end
|
1439 |
|
|
endfunction
|
1440 |
|
|
|
1441 |
94 |
rehayes |
|
1442 |
2 |
rehayes |
endmodule // tst_bench_top
|
1443 |
|
|
|
1444 |
36 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
1445 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
1446 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
1447 |
89 |
rehayes |
module bus_arbitration #(parameter dwidth = 16,
|
1448 |
|
|
parameter awidth = 24,
|
1449 |
|
|
parameter ram_base = 0,
|
1450 |
|
|
parameter ram_size = 16'hffff,
|
1451 |
|
|
parameter slv1_base = 0,
|
1452 |
|
|
parameter slv1_size = 1,
|
1453 |
|
|
parameter slv2_base = 0,
|
1454 |
|
|
parameter slv2_size = 1,
|
1455 |
65 |
rehayes |
parameter ram_wait_states = 0) // Number between 0 and 15
|
1456 |
36 |
rehayes |
(
|
1457 |
|
|
// System bus I/O
|
1458 |
89 |
rehayes |
output reg sys_cyc,
|
1459 |
|
|
output reg sys_stb,
|
1460 |
|
|
output reg sys_we,
|
1461 |
54 |
rehayes |
output reg [dwidth/8 -1:0] sys_sel,
|
1462 |
|
|
output reg [awidth -1:0] sys_adr,
|
1463 |
|
|
output reg [dwidth -1:0] sys_dout,
|
1464 |
|
|
output [dwidth -1:0] sys_din,
|
1465 |
62 |
rehayes |
|
1466 |
36 |
rehayes |
// Host bus I/O
|
1467 |
89 |
rehayes |
output host_ack,
|
1468 |
36 |
rehayes |
output [dwidth -1:0] host_dout,
|
1469 |
89 |
rehayes |
input host_cyc,
|
1470 |
|
|
input host_stb,
|
1471 |
|
|
input host_we,
|
1472 |
|
|
input [dwidth/8 -1:0] host_sel,
|
1473 |
|
|
input [awidth -1:0] host_adr,
|
1474 |
|
|
input [dwidth -1:0] host_din,
|
1475 |
62 |
rehayes |
|
1476 |
36 |
rehayes |
// Alternate Bus Master #1 Bus I/O
|
1477 |
89 |
rehayes |
output alt1_ack,
|
1478 |
36 |
rehayes |
output [dwidth -1:0] alt1_dout,
|
1479 |
89 |
rehayes |
input alt1_cyc,
|
1480 |
|
|
input alt1_stb,
|
1481 |
|
|
input alt1_we,
|
1482 |
|
|
input [dwidth/8 -1:0] alt1_sel,
|
1483 |
|
|
input [awidth -1:0] alt1_adr,
|
1484 |
|
|
input [dwidth -1:0] alt1_din,
|
1485 |
62 |
rehayes |
|
1486 |
54 |
rehayes |
// System RAM memory signals
|
1487 |
89 |
rehayes |
output ram_sel,
|
1488 |
|
|
input [dwidth -1:0] ram_dout,
|
1489 |
54 |
rehayes |
|
1490 |
36 |
rehayes |
// Slave #1 Bus I/O
|
1491 |
89 |
rehayes |
output slv1_stb,
|
1492 |
|
|
input slv1_ack,
|
1493 |
|
|
input [dwidth -1:0] slv1_din,
|
1494 |
62 |
rehayes |
|
1495 |
36 |
rehayes |
// Slave #2 Bus I/O
|
1496 |
89 |
rehayes |
output slv2_stb,
|
1497 |
|
|
input slv2_ack,
|
1498 |
|
|
input [dwidth -1:0] slv2_din,
|
1499 |
62 |
rehayes |
|
1500 |
36 |
rehayes |
// Miscellaneous
|
1501 |
89 |
rehayes |
input host_clk,
|
1502 |
|
|
input risc_clk,
|
1503 |
|
|
input rst, // No Connect
|
1504 |
|
|
input err, // No Connect
|
1505 |
|
|
input rty // No Connect
|
1506 |
36 |
rehayes |
);
|
1507 |
62 |
rehayes |
|
1508 |
60 |
rehayes |
// States for bus arbitration
|
1509 |
89 |
rehayes |
parameter [1:0] BUS_IDLE = 2'b00,
|
1510 |
|
|
HOST_OWNS = 2'b10,
|
1511 |
|
|
RISC_OWNS = 2'b11;
|
1512 |
62 |
rehayes |
|
1513 |
89 |
rehayes |
parameter max_bus_hold = 5; // Max number of cycles any bus master can hold the system bus
|
1514 |
36 |
rehayes |
//////////////////////////////////////////////////////////////////////////////
|
1515 |
|
|
//
|
1516 |
|
|
// Local Wires and Registers
|
1517 |
|
|
//
|
1518 |
89 |
rehayes |
wire ram_ack; //
|
1519 |
|
|
wire any_ack; //
|
1520 |
|
|
reg host_wait; // Host bus in wait state, Hold the bus till the transaction complets
|
1521 |
36 |
rehayes |
reg [3:0] host_cycle_cnt; // Used to count the cycle the host and break the lock if the risc needs access
|
1522 |
62 |
rehayes |
|
1523 |
89 |
rehayes |
wire risc_lock; // RISC has the slave bus
|
1524 |
|
|
reg risc_wait; // RISC bus in wait state, Hold the bus till the transaction complets
|
1525 |
36 |
rehayes |
reg [3:0] risc_cycle_cnt; // Used to count the cycle the risc and break the lock if the host needs access
|
1526 |
62 |
rehayes |
|
1527 |
54 |
rehayes |
reg [1:0] owner_state;
|
1528 |
|
|
reg [1:0] owner_ns;
|
1529 |
36 |
rehayes |
|
1530 |
89 |
rehayes |
wire host_timeout;
|
1531 |
|
|
wire risc_timeout;
|
1532 |
62 |
rehayes |
|
1533 |
89 |
rehayes |
wire ram_ack_dly; // Delayed bus ack to simulate bus wait states
|
1534 |
60 |
rehayes |
reg [3:0] ack_dly_cnt; // Counter to delay bus ack to master modules
|
1535 |
54 |
rehayes |
|
1536 |
|
|
|
1537 |
|
|
//
|
1538 |
36 |
rehayes |
always @(posedge host_clk or negedge rst)
|
1539 |
|
|
if (!rst)
|
1540 |
54 |
rehayes |
owner_state <= BUS_IDLE;
|
1541 |
36 |
rehayes |
else
|
1542 |
54 |
rehayes |
owner_state <= owner_ns;
|
1543 |
62 |
rehayes |
|
1544 |
54 |
rehayes |
//
|
1545 |
|
|
always @*
|
1546 |
|
|
case (owner_state)
|
1547 |
|
|
BUS_IDLE :
|
1548 |
89 |
rehayes |
begin
|
1549 |
|
|
if (host_cyc)
|
1550 |
|
|
owner_ns = HOST_OWNS;
|
1551 |
|
|
else if (alt1_cyc)
|
1552 |
|
|
owner_ns = RISC_OWNS;
|
1553 |
|
|
end
|
1554 |
54 |
rehayes |
HOST_OWNS :
|
1555 |
89 |
rehayes |
begin
|
1556 |
|
|
if (!host_cyc && !alt1_cyc)
|
1557 |
|
|
owner_ns = BUS_IDLE;
|
1558 |
|
|
else if (alt1_cyc && (!host_cyc || host_timeout))
|
1559 |
|
|
owner_ns = RISC_OWNS;
|
1560 |
|
|
end
|
1561 |
54 |
rehayes |
RISC_OWNS :
|
1562 |
89 |
rehayes |
begin
|
1563 |
|
|
if (!host_cyc && !alt1_cyc)
|
1564 |
|
|
owner_ns = BUS_IDLE;
|
1565 |
|
|
else if (host_cyc && (!alt1_cyc || risc_timeout))
|
1566 |
|
|
owner_ns = HOST_OWNS;
|
1567 |
|
|
end
|
1568 |
54 |
rehayes |
default : owner_ns = BUS_IDLE;
|
1569 |
|
|
endcase
|
1570 |
36 |
rehayes |
|
1571 |
62 |
rehayes |
|
1572 |
60 |
rehayes |
assign host_timeout = (owner_state == HOST_OWNS) && (host_cycle_cnt > max_bus_hold) && any_ack;
|
1573 |
|
|
assign risc_timeout = (owner_state == RISC_OWNS) && (risc_cycle_cnt > max_bus_hold) && any_ack;
|
1574 |
54 |
rehayes |
|
1575 |
|
|
// Start counting cycles that the host has the bus, if the risc is also requesting the bus
|
1576 |
36 |
rehayes |
always @(posedge host_clk or negedge rst)
|
1577 |
|
|
if (!rst)
|
1578 |
|
|
host_cycle_cnt <= 0;
|
1579 |
54 |
rehayes |
else if ((owner_state != HOST_OWNS) || !alt1_cyc)
|
1580 |
|
|
host_cycle_cnt <= 0;
|
1581 |
89 |
rehayes |
else if (&host_cycle_cnt && !host_timeout) // Don't allow rollover
|
1582 |
54 |
rehayes |
host_cycle_cnt <= host_cycle_cnt;
|
1583 |
|
|
else if ((owner_state == HOST_OWNS) && alt1_cyc)
|
1584 |
|
|
host_cycle_cnt <= host_cycle_cnt + 1'b1;
|
1585 |
36 |
rehayes |
|
1586 |
54 |
rehayes |
// Start counting cycles that the risc has the bus, if the host is also requesting the bus
|
1587 |
36 |
rehayes |
always @(posedge host_clk or negedge rst)
|
1588 |
|
|
if (!rst)
|
1589 |
|
|
risc_cycle_cnt <= 0;
|
1590 |
54 |
rehayes |
else if ((owner_state != RISC_OWNS) || !host_cyc)
|
1591 |
|
|
risc_cycle_cnt <= 0;
|
1592 |
89 |
rehayes |
else if (&risc_cycle_cnt && !risc_timeout) // Don't allow rollover
|
1593 |
54 |
rehayes |
risc_cycle_cnt <= risc_cycle_cnt;
|
1594 |
|
|
else if ((owner_state == RISC_OWNS) && host_cyc)
|
1595 |
|
|
risc_cycle_cnt <= risc_cycle_cnt + 1'b1;
|
1596 |
36 |
rehayes |
|
1597 |
62 |
rehayes |
// Aribartration Logic for System Bus access
|
1598 |
54 |
rehayes |
assign any_ack = slv1_ack || slv2_ack || ram_ack;
|
1599 |
|
|
assign host_ack = (owner_state == HOST_OWNS) && any_ack && host_cyc;
|
1600 |
|
|
assign alt1_ack = (owner_state == RISC_OWNS) && any_ack && alt1_cyc;
|
1601 |
36 |
rehayes |
|
1602 |
54 |
rehayes |
|
1603 |
|
|
// Address decoding for different Slave module instances
|
1604 |
|
|
assign slv1_stb = sys_stb && (sys_adr >= slv1_base) && (sys_adr < (slv1_base + slv1_size));
|
1605 |
|
|
assign slv2_stb = sys_stb && (sys_adr >= slv2_base) && (sys_adr < (slv2_base + slv2_size));
|
1606 |
62 |
rehayes |
|
1607 |
36 |
rehayes |
// Address decoding for Testbench access to RAM
|
1608 |
54 |
rehayes |
assign ram_sel = sys_cyc && sys_stb && !(slv1_stb || slv2_stb) &&
|
1609 |
89 |
rehayes |
(sys_adr >= ram_base) &&
|
1610 |
|
|
(sys_adr < (ram_base + ram_size));
|
1611 |
62 |
rehayes |
|
1612 |
60 |
rehayes |
// Throw in some wait states from the memory
|
1613 |
|
|
always @(posedge host_clk)
|
1614 |
|
|
if ((ack_dly_cnt == ram_wait_states) || !ram_sel)
|
1615 |
|
|
ack_dly_cnt <= 0;
|
1616 |
|
|
else if (ram_sel)
|
1617 |
|
|
ack_dly_cnt <= ack_dly_cnt + 1'b1;
|
1618 |
36 |
rehayes |
|
1619 |
60 |
rehayes |
assign ram_ack_dly = (ack_dly_cnt == ram_wait_states);
|
1620 |
|
|
assign ram_ack = ram_sel && ram_ack_dly;
|
1621 |
36 |
rehayes |
|
1622 |
60 |
rehayes |
|
1623 |
54 |
rehayes |
// Create the System Read Data Bus from the Slave output data buses
|
1624 |
68 |
rehayes |
assign sys_din = ({dwidth{1'b1}} & slv1_din) |
|
1625 |
89 |
rehayes |
({dwidth{slv2_stb}} & slv2_din) |
|
1626 |
|
|
({dwidth{ram_sel}} & ram_dout);
|
1627 |
36 |
rehayes |
|
1628 |
54 |
rehayes |
// Mux for System Bus access
|
1629 |
|
|
always @*
|
1630 |
|
|
case (owner_state)
|
1631 |
|
|
BUS_IDLE :
|
1632 |
89 |
rehayes |
begin
|
1633 |
|
|
sys_cyc = 0;
|
1634 |
|
|
sys_stb = 0;
|
1635 |
|
|
sys_we = 0;
|
1636 |
|
|
sys_sel = 0;
|
1637 |
|
|
sys_adr = 0;
|
1638 |
|
|
sys_dout = 0;
|
1639 |
|
|
end
|
1640 |
54 |
rehayes |
HOST_OWNS :
|
1641 |
89 |
rehayes |
begin
|
1642 |
|
|
sys_cyc = host_cyc;
|
1643 |
|
|
sys_stb = host_stb;
|
1644 |
|
|
sys_we = host_we;
|
1645 |
|
|
sys_sel = host_sel;
|
1646 |
|
|
sys_adr = host_adr;
|
1647 |
|
|
sys_dout = host_din;
|
1648 |
|
|
end
|
1649 |
54 |
rehayes |
RISC_OWNS :
|
1650 |
89 |
rehayes |
begin
|
1651 |
|
|
sys_cyc = alt1_cyc;
|
1652 |
|
|
sys_stb = alt1_stb;
|
1653 |
|
|
sys_we = alt1_we;
|
1654 |
|
|
sys_sel = alt1_sel;
|
1655 |
|
|
sys_adr = alt1_adr;
|
1656 |
|
|
sys_dout = alt1_din;
|
1657 |
|
|
end
|
1658 |
54 |
rehayes |
default :
|
1659 |
89 |
rehayes |
begin
|
1660 |
|
|
sys_cyc = 0;
|
1661 |
|
|
sys_stb = 0;
|
1662 |
|
|
sys_we = 0;
|
1663 |
|
|
sys_sel = 0;
|
1664 |
|
|
sys_adr = 0;
|
1665 |
|
|
sys_dout = 0;
|
1666 |
|
|
end
|
1667 |
54 |
rehayes |
endcase
|
1668 |
36 |
rehayes |
|
1669 |
54 |
rehayes |
endmodule // bus_arbitration
|
1670 |
36 |
rehayes |
|
1671 |
54 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
1672 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
1673 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
1674 |
|
|
module tb_slave #(parameter SINGLE_CYCLE = 1'b0, // No bus wait state added
|
1675 |
89 |
rehayes |
parameter MAX_CHANNEL = 127, // Max XGATE Interrupt Channel Number
|
1676 |
|
|
parameter DWIDTH = 16) // Data bus width
|
1677 |
54 |
rehayes |
(
|
1678 |
|
|
// Wishbone Signals
|
1679 |
89 |
rehayes |
output [DWIDTH-1:0] wb_dat_o, // databus output
|
1680 |
|
|
output wb_ack_o, // bus cycle acknowledge output
|
1681 |
|
|
input wb_clk_i, // master clock input
|
1682 |
|
|
input wb_rst_i, // synchronous active high reset
|
1683 |
|
|
input arst_i, // asynchronous reset
|
1684 |
|
|
input [ 3:0] wb_adr_i, // lower address bits
|
1685 |
|
|
input [DWIDTH-1:0] wb_dat_i, // databus input
|
1686 |
|
|
input wb_we_i, // write enable input
|
1687 |
|
|
input wb_stb_i, // stobe/core select signal
|
1688 |
|
|
input wb_cyc_i, // valid bus cycle input
|
1689 |
|
|
input [ 1:0] wb_sel_i, // Select byte in word bus transaction
|
1690 |
62 |
rehayes |
// Slave unique IO Signals
|
1691 |
89 |
rehayes |
output reg error_pulse, // Error detected output pulse
|
1692 |
|
|
output reg ack_pulse, // Thread ack output pulse
|
1693 |
82 |
rehayes |
output reg [DWIDTH-1:0] brkpt_cntl, // Break Point Control reg
|
1694 |
|
|
|
1695 |
89 |
rehayes |
output brk_pt, // Break point
|
1696 |
|
|
input [15:0] x_address, // XGATE WISHBONE Master bus address
|
1697 |
|
|
input [MAX_CHANNEL:1] xgif, // XGATE Interrupt Flag to Host
|
1698 |
|
|
input [19:0] vector
|
1699 |
54 |
rehayes |
);
|
1700 |
62 |
rehayes |
|
1701 |
89 |
rehayes |
wire async_rst_b; // Asyncronous reset
|
1702 |
|
|
wire sync_reset; // Syncronous reset
|
1703 |
62 |
rehayes |
|
1704 |
54 |
rehayes |
// Wishbone Bus interface
|
1705 |
|
|
// registers
|
1706 |
89 |
rehayes |
reg bus_wait_state; // Holdoff wb_ack_o for one clock to add wait state
|
1707 |
68 |
rehayes |
reg [DWIDTH-1:0] rd_data_mux; // Pseudo Register, WISHBONE Read Data Mux
|
1708 |
|
|
reg [DWIDTH-1:0] rd_data_reg; // Latch for WISHBONE Read Data
|
1709 |
36 |
rehayes |
|
1710 |
68 |
rehayes |
reg [DWIDTH-1:0] check_point_reg;
|
1711 |
|
|
reg [DWIDTH-1:0] channel_ack_reg;
|
1712 |
|
|
reg [DWIDTH-1:0] channel_err_reg;
|
1713 |
36 |
rehayes |
|
1714 |
68 |
rehayes |
reg [DWIDTH-1:0] brkpt_addr_reg; // Break Point Address reg
|
1715 |
65 |
rehayes |
|
1716 |
68 |
rehayes |
reg [DWIDTH-1:0] tb_semaphr_reg; // Test bench semaphore reg
|
1717 |
|
|
|
1718 |
54 |
rehayes |
event check_point_wrt;
|
1719 |
|
|
event channel_ack_wrt;
|
1720 |
|
|
event channel_err_wrt;
|
1721 |
36 |
rehayes |
|
1722 |
54 |
rehayes |
// Wires
|
1723 |
89 |
rehayes |
wire module_sel; // This module is selected for bus transaction
|
1724 |
|
|
wire wb_wacc; // WISHBONE Write Strobe
|
1725 |
|
|
wire wb_racc; // WISHBONE Read Access (Clock gating signal)
|
1726 |
36 |
rehayes |
|
1727 |
54 |
rehayes |
//
|
1728 |
|
|
// module body
|
1729 |
|
|
//
|
1730 |
36 |
rehayes |
|
1731 |
54 |
rehayes |
// generate internal resets
|
1732 |
|
|
|
1733 |
|
|
|
1734 |
|
|
// generate wishbone signals
|
1735 |
|
|
assign module_sel = wb_cyc_i && wb_stb_i;
|
1736 |
|
|
assign wb_wacc = module_sel && wb_we_i && (wb_ack_o || SINGLE_CYCLE);
|
1737 |
|
|
assign wb_racc = module_sel && !wb_we_i;
|
1738 |
|
|
assign wb_ack_o = SINGLE_CYCLE ? module_sel : bus_wait_state;
|
1739 |
|
|
assign wb_dat_o = SINGLE_CYCLE ? rd_data_mux : rd_data_reg;
|
1740 |
|
|
|
1741 |
|
|
// generate acknowledge output signal, By using register all accesses takes two cycles.
|
1742 |
|
|
// Accesses in back to back clock cycles are not possable.
|
1743 |
|
|
always @(posedge wb_clk_i or negedge arst_i)
|
1744 |
|
|
if (!arst_i)
|
1745 |
89 |
rehayes |
bus_wait_state <= 1'b0;
|
1746 |
54 |
rehayes |
else if (wb_rst_i)
|
1747 |
89 |
rehayes |
bus_wait_state <= 1'b0;
|
1748 |
54 |
rehayes |
else
|
1749 |
89 |
rehayes |
bus_wait_state <= module_sel && !bus_wait_state;
|
1750 |
54 |
rehayes |
|
1751 |
|
|
// assign data read bus -- DAT_O
|
1752 |
|
|
always @(posedge wb_clk_i)
|
1753 |
89 |
rehayes |
if ( wb_racc ) // Clock gate for power saving
|
1754 |
54 |
rehayes |
rd_data_reg <= rd_data_mux;
|
1755 |
|
|
|
1756 |
|
|
// WISHBONE Read Data Mux
|
1757 |
|
|
always @*
|
1758 |
|
|
case (wb_adr_i) // synopsys parallel_case
|
1759 |
68 |
rehayes |
4'b0000: rd_data_mux = check_point_reg;
|
1760 |
|
|
4'b0001: rd_data_mux = channel_ack_reg;
|
1761 |
|
|
4'b0010: rd_data_mux = channel_err_reg;
|
1762 |
82 |
rehayes |
4'b0011: rd_data_mux = brkpt_cntl;
|
1763 |
68 |
rehayes |
4'b0100: rd_data_mux = brkpt_addr_reg;
|
1764 |
|
|
4'b0101: rd_data_mux = tb_semaphr_reg;
|
1765 |
73 |
rehayes |
4'b1000: rd_data_mux = {xgif[15: 1], 1'b0};
|
1766 |
68 |
rehayes |
4'b1001: rd_data_mux = xgif[31:16];
|
1767 |
|
|
4'b1010: rd_data_mux = xgif[47:32];
|
1768 |
|
|
4'b1011: rd_data_mux = xgif[63:48];
|
1769 |
|
|
4'b1100: rd_data_mux = xgif[79:64];
|
1770 |
|
|
4'b1101: rd_data_mux = xgif[95:80];
|
1771 |
|
|
4'b1110: rd_data_mux = xgif[111:96];
|
1772 |
|
|
4'b1111: rd_data_mux = xgif[127:112];
|
1773 |
|
|
default: rd_data_mux = {DWIDTH{1'b0}};
|
1774 |
54 |
rehayes |
endcase
|
1775 |
|
|
|
1776 |
|
|
// generate wishbone write register strobes
|
1777 |
|
|
always @(posedge wb_clk_i or negedge arst_i)
|
1778 |
|
|
begin
|
1779 |
|
|
if (!arst_i)
|
1780 |
89 |
rehayes |
begin
|
1781 |
|
|
check_point_reg <= 0;
|
1782 |
|
|
channel_ack_reg <= 0;
|
1783 |
|
|
channel_err_reg <= 0;
|
1784 |
|
|
ack_pulse <= 0;
|
1785 |
|
|
error_pulse <= 0;
|
1786 |
|
|
brkpt_cntl <= 0;
|
1787 |
|
|
brkpt_addr_reg <= 0;
|
1788 |
|
|
tb_semaphr_reg <= 0;
|
1789 |
|
|
end
|
1790 |
54 |
rehayes |
else if (wb_wacc)
|
1791 |
89 |
rehayes |
case (wb_adr_i) // synopsys parallel_case
|
1792 |
|
|
3'b000 :
|
1793 |
|
|
begin
|
1794 |
|
|
check_point_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : check_point_reg[ 7:0];
|
1795 |
|
|
check_point_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : check_point_reg[15:8];
|
1796 |
|
|
-> check_point_wrt;
|
1797 |
|
|
end
|
1798 |
|
|
3'b001 :
|
1799 |
|
|
begin
|
1800 |
|
|
channel_ack_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : channel_ack_reg[ 7:0];
|
1801 |
|
|
channel_ack_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : channel_ack_reg[15:8];
|
1802 |
|
|
ack_pulse <= 1;
|
1803 |
|
|
-> channel_ack_wrt;
|
1804 |
|
|
end
|
1805 |
|
|
3'b010 :
|
1806 |
|
|
begin
|
1807 |
|
|
channel_err_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : channel_err_reg[ 7:0];
|
1808 |
|
|
channel_err_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : channel_err_reg[15:8];
|
1809 |
|
|
error_pulse <= 1'b1;
|
1810 |
|
|
-> channel_err_wrt;
|
1811 |
|
|
end
|
1812 |
|
|
3'b011 :
|
1813 |
|
|
begin
|
1814 |
|
|
brkpt_cntl[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : brkpt_cntl[ 7:0];
|
1815 |
|
|
brkpt_cntl[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : brkpt_cntl[15:8];
|
1816 |
|
|
end
|
1817 |
|
|
3'b100 :
|
1818 |
|
|
begin
|
1819 |
|
|
brkpt_addr_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : brkpt_addr_reg[ 7:0];
|
1820 |
|
|
brkpt_addr_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : brkpt_addr_reg[15:8];
|
1821 |
|
|
end
|
1822 |
|
|
3'b101 :
|
1823 |
|
|
begin
|
1824 |
|
|
tb_semaphr_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : tb_semaphr_reg[ 7:0];
|
1825 |
|
|
tb_semaphr_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : tb_semaphr_reg[15:8];
|
1826 |
|
|
end
|
1827 |
|
|
default: ;
|
1828 |
|
|
endcase
|
1829 |
54 |
rehayes |
else
|
1830 |
89 |
rehayes |
begin
|
1831 |
|
|
ack_pulse <= 0;
|
1832 |
|
|
error_pulse <= 1'b0;
|
1833 |
|
|
end
|
1834 |
54 |
rehayes |
end
|
1835 |
|
|
|
1836 |
|
|
always @check_point_wrt
|
1837 |
|
|
begin
|
1838 |
|
|
#1;
|
1839 |
|
|
$display("\nSoftware Checkpoint #%h -- at vector=%d\n", check_point_reg, vector);
|
1840 |
|
|
end
|
1841 |
|
|
|
1842 |
|
|
always @channel_err_wrt
|
1843 |
|
|
begin
|
1844 |
|
|
#1;
|
1845 |
89 |
rehayes |
$display("\n ------ !!!!! Software Checkpoint Error #%d -- at vector=%d\n -------", channel_err_reg, vector);
|
1846 |
54 |
rehayes |
end
|
1847 |
|
|
|
1848 |
|
|
|
1849 |
|
|
endmodule // tb_slave
|
1850 |
|
|
|
1851 |
82 |
rehayes |
////////////////////////////////////////////////////////////////////////////////
|
1852 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
1853 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
1854 |
89 |
rehayes |
module tb_debug #(parameter DWIDTH = 16, // Data bus width
|
1855 |
82 |
rehayes |
parameter BREAK_CAPT_0 = 0,
|
1856 |
|
|
parameter BREAK_CAPT_1 = 0,
|
1857 |
|
|
parameter BREAK_CAPT_2 = 0,
|
1858 |
|
|
parameter BREAK_CAPT_3 = 0,
|
1859 |
|
|
parameter BREAK_CAPT_4 = 0,
|
1860 |
|
|
parameter BREAK_CAPT_5 = 0,
|
1861 |
|
|
parameter BREAK_CAPT_6 = 0,
|
1862 |
|
|
parameter BREAK_CAPT_7 = 0
|
1863 |
89 |
rehayes |
)
|
1864 |
82 |
rehayes |
(
|
1865 |
|
|
// Wishbone Signals
|
1866 |
89 |
rehayes |
input arst_i, // asynchronous reset
|
1867 |
82 |
rehayes |
input risc_clk,
|
1868 |
89 |
rehayes |
input [DWIDTH-1:0] brkpt_cntl // databus input
|
1869 |
82 |
rehayes |
);
|
1870 |
|
|
|
1871 |
|
|
wire [15:0] next_pc = xgate.risc.program_counter;
|
1872 |
|
|
wire [15:0] x1 = xgate.risc.xgr1;
|
1873 |
|
|
wire [15:0] x2 = xgate.risc.xgr2;
|
1874 |
|
|
wire [15:0] x3 = xgate.risc.xgr3;
|
1875 |
|
|
wire [15:0] x4 = xgate.risc.xgr4;
|
1876 |
|
|
wire [15:0] x5 = xgate.risc.xgr5;
|
1877 |
|
|
wire [15:0] x6 = xgate.risc.xgr6;
|
1878 |
|
|
wire [15:0] x7 = xgate.risc.xgr7;
|
1879 |
89 |
rehayes |
|
1880 |
82 |
rehayes |
reg [15:0] cap_x1;
|
1881 |
|
|
reg [15:0] cap_x2;
|
1882 |
|
|
reg [15:0] cap_x3;
|
1883 |
|
|
reg [15:0] cap_x4;
|
1884 |
|
|
reg [15:0] cap_x5;
|
1885 |
|
|
reg [15:0] cap_x6;
|
1886 |
|
|
reg [15:0] cap_x7;
|
1887 |
89 |
rehayes |
|
1888 |
82 |
rehayes |
reg [15:0] break_addr_0;
|
1889 |
|
|
reg [15:0] break_addr_1;
|
1890 |
|
|
reg [15:0] break_addr_2;
|
1891 |
|
|
reg [15:0] break_addr_3;
|
1892 |
|
|
reg [15:0] break_addr_4;
|
1893 |
|
|
reg [15:0] break_addr_5;
|
1894 |
|
|
reg [15:0] break_addr_6;
|
1895 |
|
|
reg [15:0] break_addr_7;
|
1896 |
89 |
rehayes |
|
1897 |
82 |
rehayes |
reg detect_addr;
|
1898 |
89 |
rehayes |
|
1899 |
82 |
rehayes |
wire trigger, trigger0, trigger1, trigger3, trigger4, trigger5, trigger6, trigger7;
|
1900 |
89 |
rehayes |
|
1901 |
82 |
rehayes |
initial
|
1902 |
|
|
begin
|
1903 |
|
|
break_addr_0 = 0;
|
1904 |
|
|
break_addr_1 = 0;
|
1905 |
|
|
break_addr_2 = 0;
|
1906 |
|
|
break_addr_3 = 0;
|
1907 |
|
|
break_addr_4 = 0;
|
1908 |
|
|
break_addr_5 = 0;
|
1909 |
|
|
break_addr_6 = 0;
|
1910 |
|
|
break_addr_7 = 0;
|
1911 |
89 |
rehayes |
repeat(4) @(posedge risc_clk);
|
1912 |
82 |
rehayes |
break_addr_0 = {p_ram.ram_8[BREAK_CAPT_0], p_ram.ram_8[BREAK_CAPT_0+1]};
|
1913 |
|
|
break_addr_1 = {p_ram.ram_8[BREAK_CAPT_1], p_ram.ram_8[BREAK_CAPT_1+1]};
|
1914 |
|
|
break_addr_2 = {p_ram.ram_8[BREAK_CAPT_2], p_ram.ram_8[BREAK_CAPT_2+1]};
|
1915 |
|
|
break_addr_3 = {p_ram.ram_8[BREAK_CAPT_3], p_ram.ram_8[BREAK_CAPT_3+1]};
|
1916 |
|
|
break_addr_4 = {p_ram.ram_8[BREAK_CAPT_4], p_ram.ram_8[BREAK_CAPT_4+1]};
|
1917 |
|
|
break_addr_5 = {p_ram.ram_8[BREAK_CAPT_5], p_ram.ram_8[BREAK_CAPT_5+1]};
|
1918 |
|
|
break_addr_6 = {p_ram.ram_8[BREAK_CAPT_6], p_ram.ram_8[BREAK_CAPT_6+1]};
|
1919 |
|
|
break_addr_7 = {p_ram.ram_8[BREAK_CAPT_7], p_ram.ram_8[BREAK_CAPT_7+1]};
|
1920 |
|
|
end
|
1921 |
89 |
rehayes |
|
1922 |
82 |
rehayes |
assign trigger0 = (next_pc === break_addr_0) && brkpt_cntl[ 8];
|
1923 |
|
|
assign trigger1 = (next_pc === break_addr_1) && brkpt_cntl[ 9];
|
1924 |
|
|
assign trigger2 = (next_pc === break_addr_2) && brkpt_cntl[10];
|
1925 |
|
|
assign trigger3 = (next_pc === break_addr_3) && brkpt_cntl[11];
|
1926 |
|
|
assign trigger4 = (next_pc === break_addr_4) && brkpt_cntl[12];
|
1927 |
|
|
assign trigger5 = (next_pc === break_addr_5) && brkpt_cntl[13];
|
1928 |
|
|
assign trigger6 = (next_pc === break_addr_6) && brkpt_cntl[14];
|
1929 |
|
|
assign trigger7 = (next_pc === break_addr_7) && brkpt_cntl[15];
|
1930 |
89 |
rehayes |
|
1931 |
82 |
rehayes |
assign trigger = brkpt_cntl[0] &
|
1932 |
|
|
(trigger0 | trigger1 | trigger2 | trigger3 | trigger4 | trigger5 | trigger6 | trigger7);
|
1933 |
89 |
rehayes |
|
1934 |
82 |
rehayes |
always @(posedge risc_clk or negedge arst_i)
|
1935 |
|
|
begin
|
1936 |
|
|
if (!arst_i)
|
1937 |
89 |
rehayes |
begin
|
1938 |
|
|
cap_x1 <= 0;
|
1939 |
|
|
cap_x2 <= 0;
|
1940 |
|
|
cap_x3 <= 0;
|
1941 |
|
|
cap_x4 <= 0;
|
1942 |
|
|
cap_x5 <= 0;
|
1943 |
|
|
cap_x6 <= 0;
|
1944 |
|
|
cap_x7 <= 0;
|
1945 |
|
|
end
|
1946 |
82 |
rehayes |
else if (trigger)
|
1947 |
89 |
rehayes |
begin
|
1948 |
|
|
cap_x1 <= x1;
|
1949 |
|
|
cap_x2 <= x2;
|
1950 |
|
|
cap_x3 <= x3;
|
1951 |
|
|
cap_x4 <= x4;
|
1952 |
|
|
cap_x5 <= x5;
|
1953 |
|
|
cap_x6 <= x6;
|
1954 |
|
|
cap_x7 <= x7;
|
1955 |
|
|
end
|
1956 |
82 |
rehayes |
end
|
1957 |
|
|
|
1958 |
|
|
|
1959 |
|
|
endmodule // tb_debug
|
1960 |
|
|
|