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////////////////////////////////////////////////////////////////////////////////

//

//  WISHBONE revB.2 compliant Xgate Coprocessor - Test Bench

//

//  Author: Bob Hayes

//          rehayes@opencores.org

//

//  Downloaded from: http://www.opencores.org/projects/xgate.....

//

////////////////////////////////////////////////////////////////////////////////

// Copyright (c) 2009, Robert Hayes

//

// This source file is free software: you can redistribute it and/or modify

// it under the terms of the GNU Lesser General Public License as published

// by the Free Software Foundation, either version 3 of the License, or

// (at your option) any later version.

//

// Supplemental terms.

//     * Redistributions of source code must retain the above copyright

//       notice, this list of conditions and the following disclaimer.

//     * Neither the name of the <organization> nor the

//       names of its contributors may be used to endorse or promote products

//       derived from this software without specific prior written permission.

//

// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY

// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY

// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

//

// You should have received a copy of the GNU General Public License

// along with this program.  If not, see <http://www.gnu.org/licenses/>.

////////////////////////////////////////////////////////////////////////////////

// 45678901234567890123456789012345678901234567890123456789012345678901234567890

`include "timescale.v"

module tst_bench_top();

  parameter MAX_CHANNEL = 127;    // Max XGATE Interrupt Channel Number

  parameter STOP_ON_ERROR = 1'b0;

  parameter MAX_VECTOR = 2300;

  parameter L_BYTE = 2'b01;

  parameter H_BYTE = 2'b10;

  parameter WORD   = 2'b11;

  // Name Address Locations

  parameter XGATE_BASE     = 32'b0;

  parameter XGATE_XGMCTL   = XGATE_BASE + 6'h00;

  parameter XGATE_XGCHID   = XGATE_BASE + 6'h02;

  parameter XGATE_XGISPHI  = XGATE_BASE + 6'h04;

  parameter XGATE_XGISPLO  = XGATE_BASE + 6'h06;

  parameter XGATE_XGVBR    = XGATE_BASE + 6'h08;

  parameter XGATE_XGIF_7   = XGATE_BASE + 6'h0a;

  parameter XGATE_XGIF_6   = XGATE_BASE + 6'h0c;

  parameter XGATE_XGIF_5   = XGATE_BASE + 6'h0e;

  parameter XGATE_XGIF_4   = XGATE_BASE + 6'h10;

  parameter XGATE_XGIF_3   = XGATE_BASE + 6'h12;

  parameter XGATE_XGIF_2   = XGATE_BASE + 6'h14;

  parameter XGATE_XGIF_1   = XGATE_BASE + 6'h16;

  parameter XGATE_XGIF_0   = XGATE_BASE + 6'h18;

  parameter XGATE_XGSWT    = XGATE_BASE + 6'h1a;

  parameter XGATE_XGSEM    = XGATE_BASE + 6'h1c;

  parameter XGATE_RES1     = XGATE_BASE + 6'h1e;

  parameter XGATE_XGCCR    = XGATE_BASE + 6'h20;

  parameter XGATE_XGPC     = XGATE_BASE + 6'h22;

  parameter XGATE_RES2     = XGATE_BASE + 6'h24;

  parameter XGATE_XGR1     = XGATE_BASE + 6'h26;

  parameter XGATE_XGR2     = XGATE_BASE + 6'h28;

  parameter XGATE_XGR3     = XGATE_BASE + 6'h2a;

  parameter XGATE_XGR4     = XGATE_BASE + 6'h2c;

  parameter XGATE_XGR5     = XGATE_BASE + 6'h2e;

  parameter XGATE_XGR6     = XGATE_BASE + 6'h30;

  parameter XGATE_XGR7     = XGATE_BASE + 6'h32;

  // Define bits in XGATE Control Register

  parameter XGMCTL_XGEM     = 16'h8000;

  parameter XGMCTL_XGFRZM   = 16'h4000;

  parameter XGMCTL_XGDBGM   = 15'h2000;

  parameter XGMCTL_XGSSM    = 15'h1000;

  parameter XGMCTL_XGFACTM  = 15'h0800;

  parameter XGMCTL_XGBRKIEM = 15'h0400;

  parameter XGMCTL_XGSWEIFM = 15'h0200;

  parameter XGMCTL_XGIEM    = 15'h0100;

  parameter XGMCTL_XGE      = 16'h0080;

  parameter XGMCTL_XGFRZ    = 16'h0040;

  parameter XGMCTL_XGDBG    = 15'h0020;

  parameter XGMCTL_XGSS     = 15'h0010;

  parameter XGMCTL_XGFACT   = 15'h0008;

  parameter XGMCTL_XGBRKIE  = 15'h0004;

  parameter XGMCTL_XGSWEIF  = 15'h0002;

  parameter XGMCTL_XGIE     = 15'h0001;

  parameter CHECK_POINT = 16'h8000;

  parameter CHANNEL_ACK = CHECK_POINT + 2;

  parameter CHANNEL_ERR = CHECK_POINT + 4;

  parameter SYS_RAM_BASE = 32'h0002_0000;

  //

  // wires && regs

  //

  reg         mstr_test_clk;

  reg  [19:0] vector;

  reg  [15:0] error_count;

  reg  [ 7:0] test_num;

  reg  [15:0] q, qq;

  reg  [ 7:0] check_point_reg;

  reg  [ 7:0] channel_ack_reg;

  reg  [ 7:0] channel_err_reg;

  event check_point_wrt;

  event channel_ack_wrt;

  event channel_err_wrt;

  reg         rstn;

  reg         sync_reset;

  reg         por_reset_b;

  reg         stop_mode;

  reg         wait_mode;

  reg         debug_mode;

  reg         scantestmode;

  reg         wbm_ack_i;

  wire [15:0] dat_i, dat1_i, dat2_i, dat3_i;

  wire        ack, ack_2, ack_3, ack_4;

  reg  [MAX_CHANNEL:0] channel_req;  // XGATE Interrupt inputs

  wire [MAX_CHANNEL:0] xgif;         // XGATE Interrupt outputs

  wire         [  7:0] xgswt;        // XGATE Software Trigger outputs

  wire                 xg_sw_irq;    // Xgate Software Error interrupt

  wire [15:0] wbm_dat_o;         // WISHBONE Master Mode data output from XGATE

  wire [15:0] wbm_dat_i;         // WISHBONE Master Mode data input to XGATE

  wire [15:0] wbm_adr_o;         // WISHBONE Master Mode address output from XGATE

  wire [ 1:0] wbm_sel_o;

  reg         mem_wait_state_enable;

  wire [15:0] tb_ram_out;

  wire [31:0] sys_addr;

  // Registers used to mirror internal registers

  reg  [15:0] data_xgmctl;

  reg  [15:0] data_xgchid;

  reg  [15:0] data_xgvbr;

  reg  [15:0] data_xgswt;

  reg  [15:0] data_xgsem;

  wire        sys_cyc;

  wire        sys_stb;

  wire        sys_we;

  wire [ 1:0] sys_sel;

  wire [31:0] sys_adr;

  wire [15:0] sys_dout;

  wire        host_ack;

  wire [15:0] host_dout;

  wire        host_cyc;

  wire        host_stb;

  wire        host_we;

  wire [ 1:0] host_sel;

  wire [31:0] host_adr;

  wire [15:0] host_din;

  wire        xgate_ack;

  wire [15:0] xgate_dout;

  wire        xgate_cyc;

  wire        xgate_stb;

  wire        xgate_we;

  wire [ 1:0] xgate_sel;

  wire [15:0] xgate_adr;

  wire [15:0] xgate_din;

  wire        xgate_s_stb;

  wire        xgate_s_ack;

  wire [15:0] xgate_s_dout;

  wire        slv2_stb;

  wire        ram_ack;

  wire [15:0] ram_dout;

  // initial values and testbench setup

  initial

    begin

      mstr_test_clk = 0;

      vector = 0;

      test_num = 0;

      por_reset_b = 0;

      stop_mode  = 0;

      wait_mode  = 0;

      debug_mode = 0;

      scantestmode = 0;

      check_point_reg = 0;

      channel_ack_reg = 0;

      channel_err_reg = 0;

      error_count = 0;

      wbm_ack_i = 1;

      mem_wait_state_enable = 0;

      // channel_req = 0;

      `ifdef WAVES

           $shm_open("waves");

           $shm_probe("AS",tst_bench_top,"AS");

           $display("\nINFO: Signal dump enabled ...\n\n");

      `endif

      `ifdef WAVES_V

           $dumpfile ("xgate_wave_dump.lxt");

           $dumpvars (0, tst_bench_top);

           $dumpon;

           $display("\nINFO: VCD Signal dump enabled ...\n\n");

      `endif

    end

  // generate clock

  always #20 mstr_test_clk = ~mstr_test_clk;

  // Keep a count of how many clocks we've simulated

  always @(posedge mstr_test_clk)

    begin

      vector <= vector + 1;

      if (vector > MAX_VECTOR)

        begin

          error_count <= error_count + 1;

          $display("\n ------ !!!!! Simulation Timeout at vector=%d\n -------", vector);

          wrap_up;

        end

    end

  // Add up errors that come from WISHBONE read compares

  always @host.cmp_error_detect

    begin

      error_count <= error_count + 1;

    end

  // Throw in some wait states from the memory

  always @(posedge mstr_test_clk)

    if (((vector % 5) == 0) && (xgate.risc.load_next_inst || xgate.risc.data_access))

//    if ((vector % 5) == 0)

      wbm_ack_i <= 1'b1;

    else

      wbm_ack_i <= 1'b1;

  // Special Memory Mapped Testbench Registers

  always @(posedge mstr_test_clk or negedge rstn)

    begin

      if (!rstn)

        begin

          check_point_reg <= 0;

          channel_ack_reg <= 0;

          channel_err_reg <= 0;

        end

      if (wbm_sel_o[0] && wbm_ack_i && (wbm_adr_o == CHECK_POINT))

        begin

          check_point_reg <= wbm_dat_o[7:0];

          #1;

          -> check_point_wrt;

        end

      if (wbm_sel_o[0] && wbm_ack_i && (wbm_adr_o == CHANNEL_ACK))

        begin

          channel_ack_reg <= wbm_dat_o[7:0];

          #1;

          -> channel_ack_wrt;

        end

      if (wbm_sel_o[0] && wbm_ack_i && (wbm_adr_o == CHANNEL_ERR))

        begin

          channel_err_reg <= wbm_dat_o[7:0];

          #1;

          -> channel_err_wrt;

        end

    end

  always @check_point_wrt

    $display("\nSoftware Checkpoint #%h -- at vector=%d\n", check_point_reg, vector);

  always @channel_err_wrt

    begin

      $display("\n ------ !!!!! Software Checkpoint Error #%d -- at vector=%d\n  -------", channel_err_reg, vector);

      error_count = error_count + 1;

      if (STOP_ON_ERROR == 1'b1)

        wrap_up;

    end

  wire [ 6:0] current_active_channel = xgate.risc.xgchid;

  always @channel_ack_wrt

    clear_channel(current_active_channel);

  // Address decoding for different XGATE module instances

  wire stb0 = host_stb && ~host_adr[6] && ~host_adr[5] && ~|host_adr[31:16];

  wire stb1 = host_stb && ~host_adr[6] &&  host_adr[5] && ~|host_adr[31:16];

  wire stb2 = host_stb &&  host_adr[6] && ~host_adr[5] && ~|host_adr[31:16];

  wire stb3 = host_stb &&  host_adr[6] &&  host_adr[5] && ~|host_adr[31:16];

  assign dat1_i = 16'h0000;

  assign dat2_i = 16'h0000;

  assign dat3_i = 16'h0000;

  assign ack_2 = 1'b0;

  assign ack_3 = 1'b0;

  assign ack_4 = 1'b0;

  // Create the Read Data Bus

  assign dat_i = ({16{stb0}} & xgate_s_dout) |

                 ({16{stb1}} & dat1_i) |

                 ({16{stb2}} & dat2_i) |

                 ({16{stb3}} & {8'b0, dat3_i[7:0]});

  assign ack = xgate_s_ack || ack_2 || ack_3 || ack_4;

  // Aribartration Logic for Testbench RAM access

  assign sys_addr     = 1'b1 ? {16'b0, wbm_adr_o} : host_adr;

  // Testbench RAM for Xgate program storage and Load/Store instruction tests

  ram p_ram

  (

    // Outputs

    .ram_out( ram_dout ),

    // inputs

    .address( sys_addr[15:0] ),  // sys_addr  sys_adr

    .ram_in( sys_dout ),

    .we( sys_we ),

    .ce( 1'b1 ),

    .stb( mstr_test_clk ),

    .sel( sys_sel ) // wbm_sel_o sys_sel

  );

  // hookup wishbone master model

  wb_master_model #(.dwidth(16), .awidth(32))

    host(

    // Outputs

    .cyc( host_cyc ),

    .stb( host_stb ),

    .we( host_we ),

    .sel( host_sel ),

    .adr( host_adr ),

    .dout( host_dout ),

    // inputs

    .din(host_din),

    .clk(mstr_test_clk),

    .ack(host_ack),

    .rst(rstn),

    .err(1'b0),

    .rty(1'b0)

  );

  bus_arbitration  #(.dwidth(16),

                     .awidth(32))

    arb(

    // System bus I/O

    .sys_cyc( sys_cyc ),

    .sys_stb( sys_stb ),

    .sys_we( sys_we ),

    .sys_sel( sys_sel ),

    .sys_adr( sys_adr ),

    .sys_dout( sys_dout ),

    // Host bus I/O

    .host_ack( host_ack ),

    .host_dout( host_din ),

    .host_cyc( host_cyc ),

    .host_stb( host_stb ),

    .host_we( host_we ),

    .host_sel( host_sel ),

    .host_adr( host_adr ),

    .host_din( host_dout ),

    // Alternate Bus Master #1 Bus I/O

    .alt1_ack( xgate_ack ),

    .alt1_dout( xgate_din ),

    .alt1_cyc( wbm_cyc_o ),

    .alt1_stb( wbm_stb_o ),

    .alt1_we( wbm_we_o ),

    .alt1_sel( wbm_sel_o ),

    .alt1_adr( {16'h0001, wbm_adr_o} ),

    .alt1_din( wbm_dat_o ),

    // Slave #1 Bus I/O

    .slv1_stb( xgate_s_stb ),

    .slv1_ack( xgate_s_ack ),

    .slv1_din( xgate_s_dout ),

    // Slave #2 Bus I/O

    .slv2_stb( slv2_stb ),

    .slv2_ack( wbm_ack_i ),

    .slv2_din( ram_dout ),

    // Miscellaneous

    .host_clk( mstr_test_clk ),

    .risc_clk( mstr_test_clk ),

    .rst( rstn ),  // No Connect

    .err( 1'b0 ),  // No Connect

    .rty( 1'b0 )   // No Connect

  );

  // hookup XGATE core - Parameters take all default values

  //  Async Reset, 16 bit Bus, 8 bit Granularity

  xgate_top  #(.SINGLE_CYCLE(1'b1),

               .MAX_CHANNEL(MAX_CHANNEL))    // Max XGATE Interrupt Channel Number

          xgate(

          // Wishbone slave interface

          .wbs_clk_i( mstr_test_clk ),

          .wbs_rst_i( 1'b0 ),         // sync_reset

          .arst_i( rstn ),            // async resetn

          .wbs_adr_i( sys_adr[5:1] ),

          .wbs_dat_i( sys_dout ),

          .wbs_dat_o( xgate_s_dout ),

          .wbs_we_i( sys_we ),

          .wbs_stb_i( xgate_s_stb ),

          .wbs_cyc_i( sys_cyc ),

          .wbs_sel_i( sys_sel ),

          .wbs_ack_o( xgate_s_ack ),

          // Wishbone master Signals

          .wbm_dat_o( wbm_dat_o ),

          .wbm_we_o( wbm_we_o ),

          .wbm_stb_o( wbm_stb_o ),

          .wbm_cyc_o( wbm_cyc_o ),

          .wbm_sel_o( wbm_sel_o ),

          .wbm_adr_o( wbm_adr_o ),

          .wbm_dat_i( ram_dout ),

          .wbm_ack_i( wbm_ack_i ),

          .xgif( xgif ),             // XGATE Interrupt Flag output

          .xg_sw_irq( xg_sw_irq ),   // XGATE Software Error Interrupt Flag output

          .xgswt( xgswt ),

          .risc_clk( mstr_test_clk ),

          .chan_req_i( {channel_req[MAX_CHANNEL:40], xgswt, channel_req[31:0]} ),

          .scantestmode( scantestmode )

  );

////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////

// Test Program

initial

  begin

    $display("\nstatus at time: %t Testbench started", $time);

    // reset system

    rstn = 1'b1; // negate reset

    channel_req = 1; //

    repeat(1) @(posedge mstr_test_clk);

    sync_reset = 1'b1;  // Make the sync reset 1 clock cycle long

    #2;          // move the async reset away from the clock edge

    rstn = 1'b0; // assert async reset

    #5;          // Keep the async reset pulse with less than a clock cycle

    rstn = 1'b1; // negate async reset

    por_reset_b = 1'b1;

    channel_req = 0; //

    repeat(1) @(posedge mstr_test_clk);

    sync_reset = 1'b0;

    channel_req = 0; //

    $display("\nstatus at time: %t done reset", $time);

    test_inst_set;

    test_debug_mode;

    test_debug_bit;

    test_chid_debug;

    reg_test_16;

    // host_ram;

    // End testing

    wrap_up;

    repeat(10) @(posedge mstr_test_clk);

    wrap_up;

  end

////////////////////////////////////////////////////////////////////////////////

// Test CHID Debug mode operation

task test_chid_debug;

  begin

    test_num = test_num + 1;

    $display("\nTEST #%d Starts at vector=%d, test_chid_debug", test_num, vector);

    $readmemh("../../../bench/verilog/debug_test.v", p_ram.ram_8);

    data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;

    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Enable interrupt on BRK instruction

    activate_thread_sw(3);

    wait_debug_set;   // Debug Status bit is set by BRK instruction

    host.wb_cmp(0, XGATE_XGPC,     16'h20c6, WORD);      // See Program code (BRK).

    host.wb_cmp(0, XGATE_XGR3,     16'h0001, WORD);      // See Program code.R3 = 1

    host.wb_cmp(0, XGATE_XGCHID,   16'h0003, WORD);      // Check for Correct CHID

    channel_req[5] = 1'b1; //

    repeat(7) @(posedge mstr_test_clk);

    host.wb_cmp(0, XGATE_XGCHID,   16'h0003, WORD);      // Check for Correct CHID

    host.wb_write(0, XGATE_XGCHID, 16'h000f, H_BYTE);    // Check byte select lines

    repeat(4) @(posedge mstr_test_clk);

    host.wb_cmp(0, XGATE_XGCHID,   16'h0003, WORD);      // Verify CHID is unchanged

    host.wb_write(0, XGATE_XGCHID, 16'h000f, L_BYTE);    // Change CHID

    host.wb_cmp(0, XGATE_XGCHID,   16'h000f, WORD);      // Check for Correct CHID

    host.wb_write(0, XGATE_XGCHID, 16'h0000, WORD);      // Change CHID to 00, RISC should go to IDLE state

    repeat(1) @(posedge mstr_test_clk);

    host.wb_write(0, XGATE_XGCHID, 16'h0004, WORD);      // Change CHID

    repeat(8) @(posedge mstr_test_clk);

    data_xgmctl = XGMCTL_XGDBGM;

    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Clear Debug Mode Control Bit

    wait_debug_set;   // Debug Status bit is set by BRK instruction

    host.wb_cmp(0, XGATE_XGCHID,   16'h0004, WORD);      // Check for Correct CHID

    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Clear Debug Mode Control Bit (Excape from Break State and run)

    wait_debug_set;   // Debug Status bit is set by BRK instruction

    host.wb_cmp(0, XGATE_XGCHID,   16'h0005, WORD);      // Check for Correct CHID

    activate_channel(6);

    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Clear Debug Mode Control Bit (Excape from Break State and run)

    wait_debug_set;   // Debug Status bit is set by BRK instruction

    host.wb_cmp(0, XGATE_XGCHID,   16'h0006, WORD);      // Check for Correct CHID

    host.wb_cmp(0, XGATE_XGPC,     16'h211c, WORD);      // See Program code (BRK)

    data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;

    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step

    repeat(8) @(posedge mstr_test_clk);

    host.wb_cmp(0, XGATE_XGPC,     16'h211e, WORD);      // See Program code (BRA)

    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step

    repeat(8) @(posedge mstr_test_clk);

    host.wb_cmp(0, XGATE_XGPC,     16'h2122, WORD);      // See Program code ()

    repeat(20) @(posedge mstr_test_clk);

    data_xgmctl = XGMCTL_XGDBGM;

    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Clear Debug Mode Control Bit

    repeat(50) @(posedge mstr_test_clk);

    p_ram.dump_ram(0);

    read_ram_cmp(16'h0000,16'h7b55);

    read_ram_cmp(16'h0004,16'h7faa);

    read_ram_cmp(16'h0006,16'h6f55);

    read_ram_cmp(16'h0008,16'h00c3);

    read_ram_cmp(16'h000a,16'h5f66);

    read_ram_cmp(16'h000c,16'h0003);

    read_ram_cmp(16'h0022,16'hccxx);

    read_ram_cmp(16'h0026,16'hxx99);

    read_ram_cmp(16'h0032,16'h1fcc);

    read_ram_cmp(16'h0038,16'h2f99);

    read_ram_cmp(16'h0042,16'h33xx);

    read_ram_cmp(16'h0046,16'hxx55);

    read_ram_cmp(16'h0052,16'hxx66);

    read_ram_cmp(16'h0058,16'h99xx);

    read_ram_cmp(16'h0062,16'h1faa);

    read_ram_cmp(16'h0068,16'h2fcc);

  end

endtask

////////////////////////////////////////////////////////////////////////////////

// Test Debug bit operation

task test_debug_bit;

  begin

    test_num = test_num + 1;

    $display("\nTEST #%d Starts at vector=%d, test_debug_bit", test_num, vector);

    $readmemh("../../../bench/verilog/debug_test.v", p_ram.ram_8);

    data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;

    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Enable interrupt on BRK instruction

    activate_thread_sw(2);

    repeat(25) @(posedge mstr_test_clk);

    data_xgmctl = XGMCTL_XGDBGM | XGMCTL_XGDBG;

    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Set Debug Mode Control Bit

    repeat(5) @(posedge mstr_test_clk);

    host.wb_read(1, XGATE_XGR3, q, WORD);