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[/] [xgate/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Blame information for rev 93

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1 2 rehayes
////////////////////////////////////////////////////////////////////////////////
2
//
3
//  WISHBONE revB.2 compliant Xgate Coprocessor - Test Bench
4
//
5
//  Author: Bob Hayes
6 89 rehayes
//      rehayes@opencores.org
7 2 rehayes
//
8
//  Downloaded from: http://www.opencores.org/projects/xgate.....
9
//
10
////////////////////////////////////////////////////////////////////////////////
11
// Copyright (c) 2009, Robert Hayes
12
//
13
// This source file is free software: you can redistribute it and/or modify
14
// it under the terms of the GNU Lesser General Public License as published
15
// by the Free Software Foundation, either version 3 of the License, or
16
// (at your option) any later version.
17
//
18
// Supplemental terms.
19
//     * Redistributions of source code must retain the above copyright
20 89 rehayes
//   notice, this list of conditions and the following disclaimer.
21 2 rehayes
//     * Neither the name of the <organization> nor the
22 89 rehayes
//   names of its contributors may be used to endorse or promote products
23
//   derived from this software without specific prior written permission.
24 2 rehayes
//
25
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
26
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28
// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
29
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
31
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35
//
36
// You should have received a copy of the GNU General Public License
37
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
38
////////////////////////////////////////////////////////////////////////////////
39
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
40
 
41
 
42
`include "timescale.v"
43
 
44
module tst_bench_top();
45
 
46 89 rehayes
  parameter MAX_CHANNEL   = 127;    // Max XGATE Interrupt Channel Number
47 5 rehayes
  parameter STOP_ON_ERROR = 1'b0;
48 89 rehayes
  parameter MAX_VECTOR    = 12_000;
49 21 rehayes
 
50 41 rehayes
  parameter L_BYTE = 2'b01;
51
  parameter H_BYTE = 2'b10;
52 36 rehayes
  parameter WORD   = 2'b11;
53 21 rehayes
 
54 2 rehayes
 
55
  // Name Address Locations
56 89 rehayes
  parameter XGATE_BASE     = 24'h1000;
57 41 rehayes
  parameter XGATE_XGMCTL   = XGATE_BASE + 6'h00;
58
  parameter XGATE_XGCHID   = XGATE_BASE + 6'h02;
59
  parameter XGATE_XGISPHI  = XGATE_BASE + 6'h04;
60
  parameter XGATE_XGISPLO  = XGATE_BASE + 6'h06;
61 89 rehayes
  parameter XGATE_XGVBR    = XGATE_BASE + 6'h08;
62 41 rehayes
  parameter XGATE_XGIF_7   = XGATE_BASE + 6'h0a;
63
  parameter XGATE_XGIF_6   = XGATE_BASE + 6'h0c;
64
  parameter XGATE_XGIF_5   = XGATE_BASE + 6'h0e;
65
  parameter XGATE_XGIF_4   = XGATE_BASE + 6'h10;
66
  parameter XGATE_XGIF_3   = XGATE_BASE + 6'h12;
67
  parameter XGATE_XGIF_2   = XGATE_BASE + 6'h14;
68
  parameter XGATE_XGIF_1   = XGATE_BASE + 6'h16;
69
  parameter XGATE_XGIF_0   = XGATE_BASE + 6'h18;
70 89 rehayes
  parameter XGATE_XGSWT    = XGATE_BASE + 6'h1a;
71
  parameter XGATE_XGSEM    = XGATE_BASE + 6'h1c;
72
  parameter XGATE_RES1     = XGATE_BASE + 6'h1e;
73
  parameter XGATE_XGCCR    = XGATE_BASE + 6'h20;
74
  parameter XGATE_XGPC     = XGATE_BASE + 6'h22;
75
  parameter XGATE_RES2     = XGATE_BASE + 6'h24;
76
  parameter XGATE_XGR1     = XGATE_BASE + 6'h26;
77
  parameter XGATE_XGR2     = XGATE_BASE + 6'h28;
78
  parameter XGATE_XGR3     = XGATE_BASE + 6'h2a;
79
  parameter XGATE_XGR4     = XGATE_BASE + 6'h2c;
80
  parameter XGATE_XGR5     = XGATE_BASE + 6'h2e;
81
  parameter XGATE_XGR6     = XGATE_BASE + 6'h30;
82
  parameter XGATE_XGR7     = XGATE_BASE + 6'h32;
83 21 rehayes
 
84 11 rehayes
  // Define bits in XGATE Control Register
85 89 rehayes
  parameter XGMCTL_XGEM     = 16'h8000;
86 11 rehayes
  parameter XGMCTL_XGFRZM   = 16'h4000;
87
  parameter XGMCTL_XGDBGM   = 15'h2000;
88
  parameter XGMCTL_XGSSM    = 15'h1000;
89
  parameter XGMCTL_XGFACTM  = 15'h0800;
90
  parameter XGMCTL_XGBRKIEM = 15'h0400;
91
  parameter XGMCTL_XGSWEIFM = 15'h0200;
92
  parameter XGMCTL_XGIEM    = 15'h0100;
93 89 rehayes
  parameter XGMCTL_XGE      = 16'h0080;
94 11 rehayes
  parameter XGMCTL_XGFRZ    = 16'h0040;
95
  parameter XGMCTL_XGDBG    = 15'h0020;
96 89 rehayes
  parameter XGMCTL_XGSS     = 15'h0010;
97 11 rehayes
  parameter XGMCTL_XGFACT   = 15'h0008;
98
  parameter XGMCTL_XGBRKIE  = 15'h0004;
99
  parameter XGMCTL_XGSWEIF  = 15'h0002;
100 89 rehayes
  parameter XGMCTL_XGIE     = 15'h0001;
101 2 rehayes
 
102 68 rehayes
  parameter CHECK_POINT     = 16'h8000;
103
  parameter CHANNEL_ACK     = CHECK_POINT + 2;
104
  parameter CHANNEL_ERR     = CHECK_POINT + 4;
105 82 rehayes
  parameter DEBUG_CNTRL     = CHECK_POINT + 6;
106 68 rehayes
  parameter TB_SEMPHORE     = CHECK_POINT + 10;
107
  parameter CHANNEL_XGIRQ_0 = CHECK_POINT + 16;
108
  parameter CHANNEL_XGIRQ_1 = CHECK_POINT + 18;
109
  parameter CHANNEL_XGIRQ_2 = CHECK_POINT + 20;
110
  parameter CHANNEL_XGIRQ_3 = CHECK_POINT + 22;
111
  parameter CHANNEL_XGIRQ_4 = CHECK_POINT + 24;
112
  parameter CHANNEL_XGIRQ_5 = CHECK_POINT + 26;
113
  parameter CHANNEL_XGIRQ_6 = CHECK_POINT + 28;
114
  parameter CHANNEL_XGIRQ_7 = CHECK_POINT + 30;
115 36 rehayes
 
116 82 rehayes
  parameter BREAK_CAPT_0    = CHECK_POINT + 64;
117
  parameter BREAK_CAPT_1    = CHECK_POINT + 66;
118
  parameter BREAK_CAPT_2    = CHECK_POINT + 68;
119
  parameter BREAK_CAPT_3    = CHECK_POINT + 70;
120
  parameter BREAK_CAPT_4    = CHECK_POINT + 72;
121
  parameter BREAK_CAPT_5    = CHECK_POINT + 74;
122
  parameter BREAK_CAPT_6    = CHECK_POINT + 76;
123
  parameter BREAK_CAPT_7    = CHECK_POINT + 78;
124
 
125 62 rehayes
  parameter SYS_RAM_BASE = 24'h00_0000;
126 89 rehayes
 
127
  parameter RAM_WAIT_STATES    = 1; // Number between 0 and 15
128
  parameter SYS_READ_DELAY     = 10;
129 65 rehayes
  parameter XGATE_ACCESS_DELAY = SYS_READ_DELAY + RAM_WAIT_STATES;
130 89 rehayes
  parameter XGATE_SS_DELAY     = XGATE_ACCESS_DELAY + RAM_WAIT_STATES;
131 62 rehayes
 
132 89 rehayes
  parameter IRQ_BASE       = XGATE_BASE + 64;
133
  parameter IRQ_BYPS_0     = IRQ_BASE + 0;
134
  parameter IRQ_BYPS_1     = IRQ_BASE + 2;
135
  parameter IRQ_BYPS_2     = IRQ_BASE + 4;
136
  parameter IRQ_BYPS_3     = IRQ_BASE + 6;
137
  parameter IRQ_BYPS_4     = IRQ_BASE + 8;
138
  parameter IRQ_BYPS_5     = IRQ_BASE + 10;
139
  parameter IRQ_BYPS_6     = IRQ_BASE + 12;
140
  parameter IRQ_BYPS_7     = IRQ_BASE + 14;
141 65 rehayes
 
142 36 rehayes
  //
143
  // wires && regs
144
  //
145 89 rehayes
  reg         mstr_test_clk;
146 36 rehayes
  reg  [19:0] vector;
147
  reg  [15:0] error_count;
148
  reg  [ 7:0] test_num;
149 62 rehayes
 
150 36 rehayes
  reg  [15:0] q, qq;
151 21 rehayes
 
152 89 rehayes
  reg       rstn;
153
  reg       sync_reset;
154
  reg       por_reset_b;
155
  reg       scantestmode;
156 21 rehayes
 
157 73 rehayes
  reg  [MAX_CHANNEL:1] channel_req;  // XGATE Interrupt inputs
158 89 rehayes
  wire [MAX_CHANNEL:1] xgif;         // XGATE Interrupt outputs
159
  wire         [  7:0] xgswt;        // XGATE Software Trigger outputs
160
  wire                 xg_sw_irq;    // Xgate Software Error interrupt
161
  wire          [15:0] brkpt_cntl;   //
162 36 rehayes
 
163
 
164 89 rehayes
  wire [15:0] wbm_dat_o;   // WISHBONE Master Mode data output from XGATE
165
  wire [15:0] wbm_dat_i;   // WISHBONE Master Mode data input to XGATE
166
  wire [15:0] wbm_adr_o;   // WISHBONE Master Mode address output from XGATE
167 36 rehayes
  wire [ 1:0] wbm_sel_o;
168
 
169 89 rehayes
  reg       mem_wait_state_enable;
170 36 rehayes
 
171
  wire [15:0] tb_ram_out;
172
 
173 62 rehayes
  wire [15:0] tb_slave_dout; // WISHBONE data bus output from testbench slave module
174 89 rehayes
  wire        error_pulse;   // Error detected output pulse from the testbench slave module
175
  wire        tb_slave_ack;  // WISHBONE ack from testbench slave module
176
  wire        ack_pulse;     // Thread ack output pulse from testbench slave module
177
 
178 62 rehayes
  wire        wbm_cyc_o;
179
  wire        wbm_stb_o;
180
  wire        wbm_we_o;
181
  wire        wbs_err_o;
182
 
183
 
184 11 rehayes
  // Registers used to mirror internal registers
185 36 rehayes
  reg  [15:0] data_xgmctl;
186
  reg  [15:0] data_xgchid;
187
  reg  [15:0] data_xgvbr;
188
  reg  [15:0] data_xgswt;
189
  reg  [15:0] data_xgsem;
190 2 rehayes
 
191 89 rehayes
  wire        sys_cyc;
192
  wire        sys_stb;
193
  wire        sys_we;
194 36 rehayes
  wire [ 1:0] sys_sel;
195 54 rehayes
  wire [23:0] sys_adr;
196 36 rehayes
  wire [15:0] sys_dout;
197 54 rehayes
  wire [15:0] sys_din;
198 62 rehayes
 
199 89 rehayes
  wire        host_ack;
200 36 rehayes
  wire [15:0] host_dout;
201 89 rehayes
  wire        host_cyc;
202
  wire        host_stb;
203
  wire        host_we;
204 36 rehayes
  wire [ 1:0] host_sel;
205 54 rehayes
  wire [23:0] host_adr;
206 36 rehayes
  wire [15:0] host_din;
207 62 rehayes
 
208 89 rehayes
  wire        xgate_ack;
209 36 rehayes
  wire [15:0] xgate_dout;
210 89 rehayes
  wire        xgate_cyc;
211
  wire        xgate_stb;
212
  wire        xgate_we;
213 36 rehayes
  wire [ 1:0] xgate_sel;
214
  wire [15:0] xgate_adr;
215
  wire [15:0] xgate_din;
216 62 rehayes
 
217 89 rehayes
  wire        xgate_s_stb;
218
  wire        xgate_s_ack;
219 36 rehayes
  wire [15:0] xgate_s_dout;
220 62 rehayes
 
221 89 rehayes
  wire        slv2_stb;
222
  wire        ram_sel;
223 36 rehayes
  wire [15:0] ram_dout;
224
 
225 2 rehayes
  // initial values and testbench setup
226
  initial
227
    begin
228
      mstr_test_clk = 0;
229 89 rehayes
      vector        = 0;
230
      test_num      = 0;
231
      por_reset_b   = 0;
232
      scantestmode  = 0;
233
      error_count   = 0;
234 11 rehayes
      mem_wait_state_enable = 0;
235 2 rehayes
      // channel_req = 0;
236
 
237
      `ifdef WAVES
238 89 rehayes
         $shm_open("waves");
239
         $shm_probe("AS", tst_bench_top, "AS");
240
         $display("\nINFO: Signal dump enabled ...\n\n");
241 2 rehayes
      `endif
242
 
243
      `ifdef WAVES_V
244 89 rehayes
         $dumpfile ("xgate_wave_dump.lxt");
245
         $dumpvars (0, tst_bench_top);
246
         $dumpon;
247
         $display("\nINFO: VCD Signal dump enabled ...\n\n");
248 2 rehayes
      `endif
249
 
250 89 rehayes
      //-------------------------------------------------------
251
      // Enable Debussy dumping of simulation
252
      `ifdef FSDB
253
         $fsdbDumpfile("verilog.fsdb");
254
         $fsdbDumpvars(0, tst_bench_top);
255
      `endif
256
 
257 2 rehayes
    end
258
 
259
  // generate clock
260
  always #20 mstr_test_clk = ~mstr_test_clk;
261
 
262 5 rehayes
  // Keep a count of how many clocks we've simulated
263 2 rehayes
  always @(posedge mstr_test_clk)
264 11 rehayes
    begin
265
      vector <= vector + 1;
266
      if (vector > MAX_VECTOR)
267 89 rehayes
        begin
268
          error_count <= error_count + 1;
269
          $display("\n ------ !!!!! Simulation Timeout at vector=%d\n -------", vector);
270
          wrap_up;
271
        end
272 11 rehayes
    end
273 2 rehayes
 
274 50 rehayes
  // Add up errors that come from WISHBONE read compares
275 36 rehayes
  always @host.cmp_error_detect
276 21 rehayes
    begin
277
      error_count <= error_count + 1;
278
    end
279 11 rehayes
 
280 54 rehayes
  always @(posedge error_pulse) //channel_ack_wrt
281 2 rehayes
    begin
282 54 rehayes
      #1;
283 5 rehayes
      error_count = error_count + 1;
284
      if (STOP_ON_ERROR == 1'b1)
285 89 rehayes
        wrap_up;
286 5 rehayes
    end
287
 
288 2 rehayes
  wire [ 6:0] current_active_channel = xgate.risc.xgchid;
289 54 rehayes
  always @(posedge ack_pulse) //channel_ack_wrt
290 2 rehayes
    clear_channel(current_active_channel);
291 21 rehayes
 
292 2 rehayes
 
293 62 rehayes
 
294 36 rehayes
  // Testbench RAM for Xgate program storage and Load/Store instruction tests
295
  ram p_ram
296
  (
297
    // Outputs
298
    .ram_out( ram_dout ),
299
    // inputs
300 54 rehayes
    .address( sys_adr[15:0] ),
301 36 rehayes
    .ram_in( sys_dout ),
302
    .we( sys_we ),
303 54 rehayes
    .ce( ram_sel ),
304 36 rehayes
    .stb( mstr_test_clk ),
305 54 rehayes
    .sel( sys_sel )
306 36 rehayes
  );
307
 
308
  // hookup wishbone master model
309 54 rehayes
  wb_master_model #(.dwidth(16), .awidth(24))
310 36 rehayes
    host(
311
    // Outputs
312
    .cyc( host_cyc ),
313
    .stb( host_stb ),
314
    .we( host_we ),
315
    .sel( host_sel ),
316
    .adr( host_adr ),
317
    .dout( host_dout ),
318
    // inputs
319 68 rehayes
    .din( sys_din ),
320
    .clk( mstr_test_clk ),
321
    .ack( host_ack ),
322
    .rst( rstn ),
323
    .err( 1'b0 ),
324
    .rty( 1'b0 )
325 36 rehayes
  );
326
 
327
  bus_arbitration  #(.dwidth(16),
328 89 rehayes
                     .awidth(24),
329
                     .ram_base(0),
330
                     .ram_size(17'h10000),
331
                     .slv1_base(XGATE_BASE),
332
                     .slv1_size(128),
333
                     .slv2_base(CHECK_POINT),
334
                     .slv2_size(32),
335
                     .ram_wait_states(RAM_WAIT_STATES)
336 65 rehayes
)
337 36 rehayes
    arb(
338
    // System bus I/O
339
    .sys_cyc( sys_cyc ),
340
    .sys_stb( sys_stb ),
341
    .sys_we( sys_we ),
342
    .sys_sel( sys_sel ),
343
    .sys_adr( sys_adr ),
344
    .sys_dout( sys_dout ),
345 54 rehayes
    .sys_din( sys_din ),
346 36 rehayes
    // Host bus I/O
347
    .host_ack( host_ack ),
348
    .host_dout( host_din ),
349
    .host_cyc( host_cyc ),
350
    .host_stb( host_stb ),
351
    .host_we( host_we ),
352
    .host_sel( host_sel ),
353
    .host_adr( host_adr ),
354
    .host_din( host_dout ),
355
    // Alternate Bus Master #1 Bus I/O
356
    .alt1_ack( xgate_ack ),
357
    .alt1_cyc( wbm_cyc_o ),
358
    .alt1_stb( wbm_stb_o ),
359
    .alt1_we( wbm_we_o ),
360
    .alt1_sel( wbm_sel_o ),
361 54 rehayes
    .alt1_adr( {8'h00, wbm_adr_o} ),
362 36 rehayes
    .alt1_din( wbm_dat_o ),
363 54 rehayes
    // RAM
364
    .ram_sel( ram_sel ),
365
    .ram_dout( ram_dout ),
366 36 rehayes
    // Slave #1 Bus I/O
367
    .slv1_stb( xgate_s_stb ),
368
    .slv1_ack( xgate_s_ack ),
369
    .slv1_din( xgate_s_dout ),
370
    // Slave #2 Bus I/O
371
    .slv2_stb( slv2_stb ),
372 68 rehayes
    .slv2_ack( tb_slave_ack ),
373 62 rehayes
    .slv2_din( tb_slave_dout ),
374 36 rehayes
    // Miscellaneous
375
    .host_clk( mstr_test_clk ),
376
    .risc_clk( mstr_test_clk ),
377
    .rst( rstn ),  // No Connect
378
    .err( 1'b0 ),  // No Connect
379
    .rty( 1'b0 )   // No Connect
380
  );
381 62 rehayes
 
382 5 rehayes
  // hookup XGATE core - Parameters take all default values
383 54 rehayes
  xgate_top  #(.SINGLE_CYCLE(1'b0),
384 68 rehayes
               .WB_RD_DEFAULT(1'b0),
385 89 rehayes
               .MAX_CHANNEL(MAX_CHANNEL))    // Max XGATE Interrupt Channel Number
386
    xgate(
387
    // Wishbone slave interface
388
    .wbs_clk_i( mstr_test_clk ),
389
    .wbs_rst_i( 1'b0 ),       // sync_reset
390
    .arst_i( rstn ),          // async resetn
391
    .wbs_adr_i( sys_adr[6:1] ),
392
    .wbs_dat_i( sys_dout ),
393
    .wbs_dat_o( xgate_s_dout ),
394
    .wbs_we_i( sys_we ),
395
    .wbs_stb_i( xgate_s_stb ),
396
    .wbs_cyc_i( sys_cyc ),
397
    .wbs_sel_i( sys_sel ),
398
    .wbs_ack_o( xgate_s_ack ),
399
    .wbs_err_o( wbs_err_o ),
400 2 rehayes
 
401 89 rehayes
    // Wishbone master Signals
402
    .wbm_dat_o( wbm_dat_o ),
403
    .wbm_we_o( wbm_we_o ),
404
    .wbm_stb_o( wbm_stb_o ),
405
    .wbm_cyc_o( wbm_cyc_o ),
406
    .wbm_sel_o( wbm_sel_o ),
407
    .wbm_adr_o( wbm_adr_o ),
408
    .wbm_dat_i( sys_din ),
409
    .wbm_ack_i( xgate_ack ),
410 5 rehayes
 
411 89 rehayes
    .xgif( xgif ),             // XGATE Interrupt Flag output
412
    .xg_sw_irq( xg_sw_irq ),   // XGATE Software Error Interrupt Flag output
413
    .xgswt( xgswt ),
414
    .risc_clk( mstr_test_clk ),
415
    .chan_req_i( {channel_req[MAX_CHANNEL:40], xgswt, channel_req[31:1]} ),
416
    .debug_mode_i( 1'b0 ),
417
    .secure_mode_i( 1'b0 ),
418
    .scantestmode( scantestmode )
419 2 rehayes
  );
420
 
421 54 rehayes
  tb_slave #(.DWIDTH(16),
422 89 rehayes
             .SINGLE_CYCLE(1'b1),
423
             .MAX_CHANNEL(MAX_CHANNEL))
424
    tb_slave_regs(
425
    // wishbone interface
426
    .wb_clk_i( mstr_test_clk ),
427
    .wb_rst_i( 1'b0 ),
428
    .arst_i( rstn ),
429
    .wb_adr_i( sys_adr[4:1] ),
430
    .wb_dat_i( sys_dout ),
431
    .wb_dat_o( tb_slave_dout),
432
    .wb_we_i( sys_we ),
433
    .wb_stb_i( slv2_stb ),
434
    .wb_cyc_i( sys_cyc ),
435
    .wb_sel_i( sys_sel ),
436
    .wb_ack_o( tb_slave_ack ),
437 2 rehayes
 
438 89 rehayes
    .ack_pulse( ack_pulse ),
439 82 rehayes
          .brkpt_cntl( brkpt_cntl ),
440 89 rehayes
    .error_pulse( error_pulse ),
441
    .brk_pt(  ),
442
    .x_address( wbm_adr_o ),
443
    .xgif( xgif ),
444
    .vector( vector )
445 54 rehayes
  );
446 2 rehayes
 
447 89 rehayes
tb_debug #(.DWIDTH(16),                  // Data bus width
448 82 rehayes
           .BREAK_CAPT_0(BREAK_CAPT_0),
449
           .BREAK_CAPT_1(BREAK_CAPT_1),
450
           .BREAK_CAPT_2(BREAK_CAPT_2),
451
           .BREAK_CAPT_3(BREAK_CAPT_3),
452
           .BREAK_CAPT_4(BREAK_CAPT_4),
453
           .BREAK_CAPT_5(BREAK_CAPT_5),
454
           .BREAK_CAPT_6(BREAK_CAPT_6),
455
           .BREAK_CAPT_7(BREAK_CAPT_7))
456
  debugger(
457 89 rehayes
    .arst_i( rstn ),
458
    .risc_clk( mstr_test_clk ),
459
    .brkpt_cntl( brkpt_cntl )
460 82 rehayes
  );
461 54 rehayes
 
462
 
463 2 rehayes
////////////////////////////////////////////////////////////////////////////////
464
////////////////////////////////////////////////////////////////////////////////
465
////////////////////////////////////////////////////////////////////////////////
466
 
467 54 rehayes
// Main Test Program
468 2 rehayes
initial
469
  begin
470 36 rehayes
    $display("\nstatus at time: %t Testbench started", $time);
471 2 rehayes
 
472 36 rehayes
    // reset system
473 89 rehayes
    rstn = 1'b1;        // negate reset
474
    channel_req = 1;    //
475 36 rehayes
    repeat(1) @(posedge mstr_test_clk);
476 89 rehayes
    sync_reset = 1'b1;  // Make the sync reset 1 clock cycle long
477
    #2;                 // move the async reset away from the clock edge
478
    rstn = 1'b0;        // assert async reset
479
    #5;                 // Keep the async reset pulse with less than a clock cycle
480
    rstn = 1'b1;        // negate async reset
481 36 rehayes
    por_reset_b = 1'b1;
482 89 rehayes
    channel_req = 0;    //
483 36 rehayes
    repeat(1) @(posedge mstr_test_clk);
484
    sync_reset = 1'b0;
485 89 rehayes
    channel_req = 0;    //
486 2 rehayes
 
487 36 rehayes
    $display("\nstatus at time: %t done reset", $time);
488 21 rehayes
 
489 89 rehayes
    test_skipjack;
490
 
491 36 rehayes
    test_inst_set;
492 21 rehayes
 
493 36 rehayes
    test_debug_mode;
494 2 rehayes
 
495 36 rehayes
    test_debug_bit;
496 21 rehayes
 
497 36 rehayes
    test_chid_debug;
498 21 rehayes
 
499 41 rehayes
    reg_test_16;
500 89 rehayes
 
501 68 rehayes
    reg_irq;
502 41 rehayes
 
503 68 rehayes
    // host_ram;
504 54 rehayes
 
505 36 rehayes
    // End testing
506
    wrap_up;
507 2 rehayes
  end
508
 
509 36 rehayes
////////////////////////////////////////////////////////////////////////////////
510 21 rehayes
// Test CHID Debug mode operation
511
task test_chid_debug;
512
  begin
513
    test_num = test_num + 1;
514
    $display("\nTEST #%d Starts at vector=%d, test_chid_debug", test_num, vector);
515 36 rehayes
    $readmemh("../../../bench/verilog/debug_test.v", p_ram.ram_8);
516 21 rehayes
 
517 68 rehayes
    // Enable interrupts to RISC
518
    host.wb_write(0, IRQ_BYPS_0,  16'h0000, WORD);
519
 
520 21 rehayes
    data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
521 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Enable interrupt on BRK instruction
522 65 rehayes
    $display("BRK Software Error Interrupt enabled at vector=%d", vector);
523 21 rehayes
 
524
    activate_thread_sw(3);
525
 
526
    wait_debug_set;   // Debug Status bit is set by BRK instruction
527
 
528 89 rehayes
    host.wb_cmp(0, XGATE_XGPC,     16'h20c6, WORD);  // See Program code (BRK).
529
    host.wb_cmp(0, XGATE_XGR3,     16'h0001, WORD);  // See Program code.R3 = 1
530
    host.wb_cmp(0, XGATE_XGCHID,   16'h0003, WORD);  // Check for Correct CHID
531 65 rehayes
    $display("Debug entry detected at vector=%d", vector);
532 21 rehayes
 
533
    channel_req[5] = 1'b1; //
534
    repeat(7) @(posedge mstr_test_clk);
535 89 rehayes
    host.wb_cmp(0, XGATE_XGCHID,   16'h0003, WORD);    // Check for Correct CHID
536 21 rehayes
 
537 89 rehayes
    host.wb_write(0, XGATE_XGCHID, 16'h000f, H_BYTE);  // Check byte select lines
538 41 rehayes
    repeat(4) @(posedge mstr_test_clk);
539 89 rehayes
    host.wb_cmp(0, XGATE_XGCHID,   16'h0003, WORD);    // Verify CHID is unchanged
540 21 rehayes
 
541 89 rehayes
    host.wb_write(0, XGATE_XGCHID, 16'h000f, L_BYTE);  // Change CHID
542
    host.wb_cmp(0, XGATE_XGCHID,   16'h000f, WORD);    // Check for Correct CHID
543 21 rehayes
 
544 89 rehayes
    host.wb_write(0, XGATE_XGCHID, 16'h0000, WORD);    // Change CHID to 00, RISC should go to IDLE state
545 62 rehayes
 
546 21 rehayes
    repeat(1) @(posedge mstr_test_clk);
547
 
548 89 rehayes
    host.wb_write(0, XGATE_XGCHID, 16'h0004, WORD);    // Change CHID
549 21 rehayes
 
550
    repeat(8) @(posedge mstr_test_clk);
551 65 rehayes
    $display("Channel ID changed at vector=%d", vector);
552 21 rehayes
 
553 89 rehayes
 
554 21 rehayes
    data_xgmctl = XGMCTL_XGDBGM;
555 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Clear Debug Mode Control Bit
556 21 rehayes
 
557 89 rehayes
    wait_debug_set;                                      // Debug Status bit is set by BRK instruction
558
    host.wb_cmp(0, XGATE_XGCHID,   16'h0004, WORD);      // Check for Correct CHID
559
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Clear Debug Mode Control Bit (Excape from Break State and run)
560 21 rehayes
 
561
    wait_debug_set;   // Debug Status bit is set by BRK instruction
562 89 rehayes
    host.wb_cmp(0, XGATE_XGCHID,   16'h0005, WORD);      // Check for Correct CHID
563 21 rehayes
    activate_channel(6);
564 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Clear Debug Mode Control Bit (Excape from Break State and run)
565 21 rehayes
 
566 89 rehayes
    wait_debug_set;                                      // Debug Status bit is set by BRK instruction
567
    host.wb_cmp(0, XGATE_XGCHID,   16'h0006, WORD);      // Check for Correct CHID
568
    host.wb_cmp(0, XGATE_XGPC,     16'h211c, WORD);      // See Program code (BRK)
569 21 rehayes
    data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
570 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step
571 65 rehayes
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
572 89 rehayes
    host.wb_cmp(0, XGATE_XGPC,     16'h211e, WORD);      // See Program code (BRA)
573
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step
574 65 rehayes
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
575 89 rehayes
    host.wb_cmp(0, XGATE_XGPC,     16'h2122, WORD);      // See Program code ()
576 21 rehayes
 
577
    repeat(20) @(posedge mstr_test_clk);
578
 
579
    data_xgmctl = XGMCTL_XGDBGM;
580 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Clear Debug Mode Control Bit
581 21 rehayes
 
582
    repeat(50) @(posedge mstr_test_clk);
583
 
584 36 rehayes
    p_ram.dump_ram(0);
585
 
586 68 rehayes
    read_ram_cmp(16'h0000, 16'h7b55);
587
    read_ram_cmp(16'h0004, 16'h7faa);
588
    read_ram_cmp(16'h0006, 16'h6f55);
589
    read_ram_cmp(16'h0008, 16'h00c3);
590
    read_ram_cmp(16'h000a, 16'h5f66);
591
    read_ram_cmp(16'h000c, 16'h0003);
592
    read_ram_cmp(16'h0022, 16'hccxx);
593
    read_ram_cmp(16'h0026, 16'hxx99);
594
    read_ram_cmp(16'h0032, 16'h1fcc);
595
    read_ram_cmp(16'h0038, 16'h2f99);
596
    read_ram_cmp(16'h0042, 16'h33xx);
597
    read_ram_cmp(16'h0046, 16'hxx55);
598
    read_ram_cmp(16'h0052, 16'hxx66);
599
    read_ram_cmp(16'h0058, 16'h99xx);
600
    read_ram_cmp(16'h0062, 16'h1faa);
601
    read_ram_cmp(16'h0068, 16'h2fcc);
602 41 rehayes
 
603 21 rehayes
  end
604
endtask
605
 
606 36 rehayes
////////////////////////////////////////////////////////////////////////////////
607 11 rehayes
// Test Debug bit operation
608
task test_debug_bit;
609 2 rehayes
  begin
610 11 rehayes
    test_num = test_num + 1;
611 21 rehayes
    $display("\nTEST #%d Starts at vector=%d, test_debug_bit", test_num, vector);
612 36 rehayes
    $readmemh("../../../bench/verilog/debug_test.v", p_ram.ram_8);
613 21 rehayes
 
614 68 rehayes
    // Enable interrupts to RISC
615
    host.wb_write(0, IRQ_BYPS_0,  16'h0000, WORD);
616
 
617 11 rehayes
    data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
618 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Enable interrupt on BRK instruction
619 11 rehayes
 
620
    activate_thread_sw(2);
621 21 rehayes
 
622 65 rehayes
    // Approxmatly 12 instructions need to be done before activating Debug Mode
623
    repeat(12 + RAM_WAIT_STATES*12) @(posedge mstr_test_clk);
624 11 rehayes
 
625
    data_xgmctl = XGMCTL_XGDBGM | XGMCTL_XGDBG;
626 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Set Debug Mode Control Bit
627 21 rehayes
    repeat(5) @(posedge mstr_test_clk);
628 65 rehayes
    $display("DEBUG bit set at vector=%d", vector);
629 21 rehayes
 
630 36 rehayes
    host.wb_read(1, XGATE_XGR3, q, WORD);
631 21 rehayes
    data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
632
    qq = q;
633
 
634 89 rehayes
    // The Xgate test program is in an infinite loop incrementing R3
635 21 rehayes
    while (qq == q)  // Look for change in R3 register
636
      begin
637 89 rehayes
        host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step
638
        repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
639
        host.wb_read(1, XGATE_XGR3, q, WORD);
640 21 rehayes
      end
641
    if (q != (qq+1))
642
      begin
643 89 rehayes
        $display("Error! - Unexpected value of R3 at vector=%d", vector);
644
        error_count = error_count + 1;
645 21 rehayes
      end
646
 
647
 
648 89 rehayes
    host.wb_write(1, XGATE_XGPC, 16'h2094, WORD);    // Write to PC to force exit from infinite loop
649 54 rehayes
    repeat(10) @(posedge mstr_test_clk);
650 89 rehayes
    host.wb_cmp(0, XGATE_XGPC,     16'h2094, WORD);  // Verify Proram Counter was changed
651 65 rehayes
    $display("Program Counter changed at vector=%d", vector);
652 21 rehayes
 
653
    data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
654 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step (Load ADDL instruction)
655 65 rehayes
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
656 89 rehayes
    host.wb_cmp(0, XGATE_XGR4,     16'h0002, WORD);      // See Program code.(R4 <= R4 + 1)
657 21 rehayes
 
658 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step (Load ADDL instruction)
659 65 rehayes
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
660 89 rehayes
    host.wb_cmp(0, XGATE_XGR4,     16'h0003, WORD);      // See Program code.(R4 <= R4 + 1)
661 21 rehayes
 
662
    data_xgmctl = XGMCTL_XGDBGM;
663 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Clear Debug Mode Control Bit
664
             // Should be back in Run Mode
665 21 rehayes
 
666
//    data_xgmctl = XGMCTL_XGSWEIFM | XGMCTL_XGSWEIF | XGMCTL_XGBRKIEM;
667 36 rehayes
//    host.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Clear Software Interrupt and BRK Interrupt Enable Bit
668 11 rehayes
    repeat(15) @(posedge mstr_test_clk);
669 21 rehayes
 
670 2 rehayes
  end
671
endtask
672
 
673 36 rehayes
////////////////////////////////////////////////////////////////////////////////
674 11 rehayes
// Test Debug mode operation
675
task test_debug_mode;
676 2 rehayes
  begin
677 11 rehayes
    test_num = test_num + 1;
678
    $display("\nTEST #%d Starts at vector=%d, test_debug_mode", test_num, vector);
679 36 rehayes
    $readmemh("../../../bench/verilog/debug_test.v", p_ram.ram_8);
680 21 rehayes
 
681 68 rehayes
    // Enable interrupts to RISC
682
    host.wb_write(0, IRQ_BYPS_0,  16'h0000, WORD);
683
 
684 11 rehayes
    data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
685 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Enable interrupt on BRK instruction
686 11 rehayes
 
687
    activate_thread_sw(1);
688 21 rehayes
 
689 11 rehayes
    wait_debug_set;   // Debug Status bit is set by BRK instruction
690
 
691 89 rehayes
    host.wb_cmp(0, XGATE_XGPC,     16'h203a, WORD);  // See Program code (BRK).
692
    host.wb_cmp(0, XGATE_XGR3,     16'h0001, WORD);  // See Program code.R3 = 1
693 11 rehayes
 
694
    data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
695
 
696 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step (Load ADDL instruction)
697 65 rehayes
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
698 89 rehayes
    host.wb_cmp(0, XGATE_XGPC,     16'h203c, WORD);      // PC + 2.
699 11 rehayes
 
700 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step (Load NOP instruction)
701
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);     // Execute ADDL instruction
702
    host.wb_cmp(0, XGATE_XGR3,     16'h0002, WORD);      // See Program code.(R3 <= R3 + 1)
703
    host.wb_cmp(0, XGATE_XGCCR,    16'h0000, WORD);      // See Program code.
704
    host.wb_cmp(0, XGATE_XGPC,     16'h203e, WORD);      // PC + 2.
705 65 rehayes
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
706 89 rehayes
    host.wb_cmp(0, XGATE_XGPC,     16'h203e, WORD);      // Still no change.
707 11 rehayes
 
708 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step (Load BRA instruction)
709
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);     // Execute NOP instruction
710
    host.wb_cmp(0, XGATE_XGPC,     16'h2040, WORD);      // See Program code.
711 11 rehayes
 
712
 
713 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step
714
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);     // Execute BRA instruction
715
    host.wb_cmp(0, XGATE_XGPC,     16'h2064, WORD);      // PC = Branch destination.
716
               // Load ADDL instruction
717 21 rehayes
 
718 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step (Load LDW R7 instruction)
719
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);     // Execute ADDL instruction
720
    host.wb_cmp(0, XGATE_XGPC,     16'h2066, WORD);      // PC + 2.
721
    host.wb_cmp(0, XGATE_XGR3,     16'h0003, WORD);      // See Program code.(R3 <= R3 + 1)
722 11 rehayes
 
723 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step (LDW R7)
724 65 rehayes
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
725 89 rehayes
    host.wb_cmp(0, XGATE_XGPC,     16'h2068, WORD);      // PC + 2.
726
    host.wb_cmp(0, XGATE_XGR7,     16'h00c3, WORD);      // See Program code
727 11 rehayes
 
728
    repeat(1) @(posedge mstr_test_clk);
729 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step (BRA)
730 65 rehayes
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
731 89 rehayes
    host.wb_cmp(0, XGATE_XGPC,     16'h2048, WORD);      // See Program code.
732 11 rehayes
 
733 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step (STW R3)
734 65 rehayes
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
735 89 rehayes
    host.wb_cmp(0, XGATE_XGPC,     16'h204a, WORD);      // PC + 2.
736
    host.wb_cmp(0, XGATE_XGR3,     16'h0003, WORD);      // See Program code.(R3 <= R3 + 1)
737 11 rehayes
 
738 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step (R3 <= R3 + 1)
739 65 rehayes
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
740 89 rehayes
    host.wb_cmp(0, XGATE_XGPC,     16'h204c, WORD);      // PC + 2.
741 11 rehayes
 
742 65 rehayes
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
743 11 rehayes
 
744
    data_xgmctl = XGMCTL_XGDBGM;
745 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Clear Debug Mode Control Bit
746
               // Should be back in Run Mode
747 11 rehayes
    wait_irq_set(1);
748 36 rehayes
    host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);
749 21 rehayes
 
750 11 rehayes
    data_xgmctl = XGMCTL_XGSWEIFM | XGMCTL_XGSWEIF | XGMCTL_XGBRKIEM;
751 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Clear Software Interrupt and BRK Interrupt Enable Bit
752 11 rehayes
    repeat(15) @(posedge mstr_test_clk);
753 21 rehayes
 
754 2 rehayes
  end
755
endtask
756
 
757 36 rehayes
////////////////////////////////////////////////////////////////////////////////
758 11 rehayes
// Test instruction set
759
task test_inst_set;
760
  begin
761 36 rehayes
    $readmemh("../../../bench/verilog/inst_test.v", p_ram.ram_8);
762 11 rehayes
    test_num = test_num + 1;
763 65 rehayes
    $display("\nTEST #%d Starts at vector=%d, test_inst_set", test_num, vector);
764 21 rehayes
    repeat(1) @(posedge mstr_test_clk);
765 89 rehayes
 
766 68 rehayes
    // Enable interrupts to RISC
767
    host.wb_write(0, IRQ_BYPS_0,  16'h0000, WORD);
768 11 rehayes
 
769
    activate_thread_sw(1);
770
    wait_irq_set(1);
771 36 rehayes
    host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);
772 21 rehayes
 
773 11 rehayes
    activate_thread_sw(2);
774
    wait_irq_set(2);
775 36 rehayes
    host.wb_write(1, XGATE_XGIF_0, 16'h0004, WORD);
776 11 rehayes
 
777
    activate_thread_sw(3);
778
    wait_irq_set(3);
779 36 rehayes
    host.wb_write(1, XGATE_XGIF_0, 16'h0008, WORD);
780 21 rehayes
 
781 11 rehayes
    activate_thread_sw(4);
782
    wait_irq_set(4);
783 36 rehayes
    host.wb_write(1, XGATE_XGIF_0, 16'h0010, WORD);
784 21 rehayes
 
785 11 rehayes
    activate_thread_sw(5);
786
    wait_irq_set(5);
787 36 rehayes
    host.wb_write(1, XGATE_XGIF_0, 16'h0020, WORD);
788 21 rehayes
 
789 11 rehayes
    activate_thread_sw(6);
790
    wait_irq_set(6);
791 36 rehayes
    host.wb_write(1, XGATE_XGIF_0, 16'h0040, WORD);
792 21 rehayes
 
793 11 rehayes
    activate_thread_sw(7);
794
    wait_irq_set(7);
795 36 rehayes
    host.wb_write(1, XGATE_XGIF_0, 16'h0080, WORD);
796 21 rehayes
 
797 11 rehayes
    activate_thread_sw(8);
798
    wait_irq_set(8);
799 36 rehayes
    host.wb_write(1, XGATE_XGIF_0, 16'h0100, WORD);
800 21 rehayes
 
801 11 rehayes
    activate_thread_sw(9);
802
    wait_irq_set(9);
803 36 rehayes
    host.wb_write(1, XGATE_XGIF_0, 16'h0200, WORD);
804 21 rehayes
 
805 36 rehayes
    host.wb_write(1, XGATE_XGSEM, 16'h5050, WORD);
806 89 rehayes
    host.wb_cmp(0, XGATE_XGSEM,    16'h0050, WORD);   //
807 11 rehayes
    activate_thread_sw(10);
808
    wait_irq_set(10);
809 36 rehayes
    host.wb_write(1, XGATE_XGIF_0, 16'h0400, WORD);
810 21 rehayes
 
811 36 rehayes
    host.wb_write(1, XGATE_XGSEM, 16'hff00, WORD);    // clear the old settings
812 89 rehayes
    host.wb_cmp(0, XGATE_XGSEM,   16'h0000, WORD);    //
813 36 rehayes
    host.wb_write(1, XGATE_XGSEM, 16'ha0a0, WORD);    // Verify that bits were unlocked by RISC
814 89 rehayes
    host.wb_cmp(0, XGATE_XGSEM,   16'h00a0, WORD);    // Verify bits were set
815 36 rehayes
    host.wb_write(1, XGATE_XGSEM, 16'hff08, WORD);    // Try to set the bit that was left locked by the RISC
816 89 rehayes
    host.wb_cmp(0, XGATE_XGSEM,   16'h0000, WORD);    // Verify no bits were set
817 21 rehayes
 
818 11 rehayes
    repeat(20) @(posedge mstr_test_clk);
819
 
820 36 rehayes
    p_ram.dump_ram(0);
821 62 rehayes
 
822 89 rehayes
    read_ram_cmp(16'h0000, 16'haa55);
823
    read_ram_cmp(16'h0004, 16'h7faa);
824
    read_ram_cmp(16'h0006, 16'h6f55);
825
    read_ram_cmp(16'h000a, 16'h5f66);
826
    read_ram_cmp(16'h0032, 16'h1fcc);
827
    read_ram_cmp(16'h0038, 16'h2f99);
828
    read_ram_cmp(16'h0062, 16'h1faa);
829
    read_ram_cmp(16'h0068, 16'h2fcc);
830
    read_ram_cmp(16'h0022, 16'hccxx);
831
    read_ram_cmp(16'h0026, 16'hxx99);
832
    read_ram_cmp(16'h0052, 16'hxx66);
833
    read_ram_cmp(16'h0058, 16'h99xx);
834
    read_ram_cmp(16'h0080, 16'h9966);
835
    read_ram_cmp(16'h0086, 16'h7533);
836 62 rehayes
 
837 50 rehayes
    data_xgmctl = 16'hff00;
838 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Disable XGATE
839 50 rehayes
 
840 11 rehayes
  end
841
endtask
842
 
843 36 rehayes
////////////////////////////////////////////////////////////////////////////////
844 89 rehayes
// Test instruction set
845 82 rehayes
task test_skipjack;
846
  begin
847
    $readmemh("../../../bench/verilog/skipjack.v", p_ram.ram_8);
848
    test_num = test_num + 1;
849
    $display("\nTEST #%d Starts at vector=%d, test_skipjack", test_num, vector);
850
    repeat(1) @(posedge mstr_test_clk);
851 89 rehayes
 
852 82 rehayes
    host.wb_write(0, DEBUG_CNTRL,  16'hFFFF, WORD);
853
 
854
    // Enable interrupts to RISC
855
    host.wb_write(0, IRQ_BYPS_0,  16'h0000, WORD);
856
 
857
    activate_thread_sw(2);
858
    wait_irq_set(2);
859
    host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);
860
 
861
 
862
    repeat(20) @(posedge mstr_test_clk);
863
 
864
    p_ram.dump_ram(16'h2000);
865
    // repeat(2) @(posedge mstr_test_clk);
866
    // p_ram.dump_ram(16'h9000);
867
 
868
    data_xgmctl = 16'hff00;
869 89 rehayes
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Disable XGATE
870 82 rehayes
 
871
  end
872
endtask
873
 
874
////////////////////////////////////////////////////////////////////////////////
875 2 rehayes
// check register bits - reset, read/write
876
task reg_test_16;
877
  begin
878 65 rehayes
    test_num = test_num + 1;
879
    $display("\nTEST #%d Starts at vector=%d, reg_test_16", test_num, vector);
880 41 rehayes
 
881 65 rehayes
    system_reset;
882 2 rehayes
 
883 89 rehayes
    host.wb_cmp(0, XGATE_XGMCTL,   16'h0000, WORD); // verify reset
884
    host.wb_cmp(0, XGATE_XGCHID,   16'h0000, WORD); // verify reset
885
    host.wb_cmp(0, XGATE_XGISPHI,  16'h0000, WORD); // verify reset
886
    host.wb_cmp(0, XGATE_XGISPLO,  16'h0000, WORD); // verify reset
887
    host.wb_cmp(0, XGATE_XGVBR,    16'hfe00, WORD); // verify reset
888
    host.wb_cmp(0, XGATE_XGIF_7,   16'h0000, WORD); // verify reset
889
    host.wb_cmp(0, XGATE_XGIF_6,   16'h0000, WORD); // verify reset
890
    host.wb_cmp(0, XGATE_XGIF_5,   16'h0000, WORD); // verify reset
891
    host.wb_cmp(0, XGATE_XGIF_4,   16'h0000, WORD); // verify reset
892
    host.wb_cmp(0, XGATE_XGIF_3,   16'h0000, WORD); // verify reset
893
    host.wb_cmp(0, XGATE_XGIF_2,   16'h0000, WORD); // verify reset
894
    host.wb_cmp(0, XGATE_XGIF_1,   16'h0000, WORD); // verify reset
895
    host.wb_cmp(0, XGATE_XGIF_0,   16'h0000, WORD); // verify reset
896
    host.wb_cmp(0, XGATE_XGSWT,    16'h0000, WORD); // verify reset
897
    host.wb_cmp(0, XGATE_XGSEM,    16'h0000, WORD); // verify reset
898
    host.wb_cmp(0, XGATE_XGCCR,    16'h0000, WORD); // verify reset
899
    host.wb_cmp(0, XGATE_XGPC,     16'h0000, WORD); // verify reset
900
    host.wb_cmp(0, XGATE_XGR1,     16'h0000, WORD); // verify reset
901
    host.wb_cmp(0, XGATE_XGR2,     16'h0000, WORD); // verify reset
902
    host.wb_cmp(0, XGATE_XGR3,     16'h0000, WORD); // verify reset
903
    host.wb_cmp(0, XGATE_XGR4,     16'h0000, WORD); // verify reset
904
    host.wb_cmp(0, XGATE_XGR5,     16'h0000, WORD); // verify reset
905
    host.wb_cmp(0, XGATE_XGR6,     16'h0000, WORD); // verify reset
906
    host.wb_cmp(0, XGATE_XGR7,     16'h0000, WORD); // verify reset
907 62 rehayes
 
908 89 rehayes
   // Test bits in the Xgate Control Register (XGMCTL)
909 65 rehayes
    data_xgmctl = XGMCTL_XGEM | XGMCTL_XGFRZM | XGMCTL_XGFACTM | XGMCTL_XGFRZ | XGMCTL_XGFACT | XGMCTL_XGE;
910
    host.wb_write(0, XGATE_XGMCTL,   data_xgmctl, WORD);   //
911
    data_xgmctl = XGMCTL_XGFRZ | XGMCTL_XGFACT | XGMCTL_XGE;
912
    host.wb_cmp(  0, XGATE_XGMCTL, data_xgmctl, WORD);
913 2 rehayes
 
914 65 rehayes
    data_xgmctl = XGMCTL_XGEM;
915
    host.wb_write(0, XGATE_XGMCTL,   data_xgmctl, WORD);   //
916
    data_xgmctl = XGMCTL_XGFRZ | XGMCTL_XGFACT;
917
    host.wb_cmp(  0, XGATE_XGMCTL, data_xgmctl, WORD);
918 2 rehayes
 
919 65 rehayes
    data_xgmctl = XGMCTL_XGFRZM | XGMCTL_XGFACTM;
920
    host.wb_write(0, XGATE_XGMCTL,   data_xgmctl, WORD);   //
921
    data_xgmctl = 16'h0000;
922
    host.wb_cmp(  0, XGATE_XGMCTL, data_xgmctl, WORD);
923 41 rehayes
 
924 65 rehayes
    data_xgmctl = 16'hffff;
925
    host.wb_write(0, XGATE_XGMCTL,   data_xgmctl, H_BYTE);   //
926
    data_xgmctl = 16'h0000;
927
    host.wb_cmp(  0, XGATE_XGMCTL, data_xgmctl, WORD);
928 41 rehayes
 
929 65 rehayes
    data_xgmctl = 16'hffff;
930
    host.wb_write(0, XGATE_XGMCTL,   data_xgmctl, L_BYTE);   //
931
    data_xgmctl = 16'h0000;
932
    host.wb_cmp(  0, XGATE_XGMCTL, data_xgmctl, WORD);
933 41 rehayes
 
934 65 rehayes
    // Test the Xgate Vector Base Address Register (XGVBR)
935
    host.wb_write(0, XGATE_XGVBR,  16'h5555, WORD);
936
    host.wb_cmp(0, XGATE_XGVBR,    16'h5554, WORD);
937 41 rehayes
 
938 65 rehayes
    host.wb_write(0, XGATE_XGVBR,  16'hAAAA, WORD);
939
    host.wb_cmp(0, XGATE_XGVBR,    16'hAAAA, WORD);
940 41 rehayes
 
941 65 rehayes
    host.wb_write(0, XGATE_XGVBR,  16'hFF55, L_BYTE);
942
    host.wb_cmp(0, XGATE_XGVBR,    16'hAA54, WORD);
943 62 rehayes
 
944 65 rehayes
    host.wb_write(0, XGATE_XGVBR,  16'h55AA, H_BYTE);
945
    host.wb_cmp(0, XGATE_XGVBR,    16'h5554, WORD);
946 62 rehayes
 
947 65 rehayes
    data_xgmctl = XGMCTL_XGEM | XGMCTL_XGE;
948
    host.wb_write(0, XGATE_XGMCTL,   data_xgmctl, WORD);   //
949
    data_xgmctl = XGMCTL_XGE;
950
    host.wb_cmp(  0, XGATE_XGMCTL, data_xgmctl, WORD);
951
    host.wb_write(0, XGATE_XGVBR,  16'hFFFF, WORD);
952
    host.wb_cmp(0, XGATE_XGVBR,    16'h5554, WORD);
953 41 rehayes
 
954 65 rehayes
    data_xgmctl = XGMCTL_XGEM;
955
    host.wb_write(0, XGATE_XGMCTL,   data_xgmctl, WORD);   //
956 41 rehayes
 
957 65 rehayes
    // Test the Xgate Software Trigger Register (XGSWT)
958
    host.wb_write(0, XGATE_XGSWT,  16'hFFFF, WORD);
959
    host.wb_cmp(0, XGATE_XGSWT,    16'h00FF, WORD);
960
    host.wb_write(0, XGATE_XGSWT,  16'hFF00, WORD);
961
    host.wb_cmp(0, XGATE_XGSWT,    16'h0000, WORD);
962 41 rehayes
 
963 65 rehayes
    host.wb_write(0, XGATE_XGSWT,  16'hFF55, L_BYTE);
964
    host.wb_cmp(0, XGATE_XGSWT,    16'h0000, WORD);
965
    host.wb_write(0, XGATE_XGSWT,  16'hFF55, H_BYTE);
966
    host.wb_cmp(0, XGATE_XGSWT,    16'h0000, WORD);
967 41 rehayes
 
968 65 rehayes
    // Test the Xgate Semaphore Register (XGSEM)
969
    host.wb_write(0, XGATE_XGSEM,  16'hFFFF, WORD);
970
    host.wb_cmp(0, XGATE_XGSEM,    16'h00FF, WORD);
971
    host.wb_write(0, XGATE_XGSEM,  16'hFF00, WORD);
972
    host.wb_cmp(0, XGATE_XGSEM,    16'h0000, WORD);
973 41 rehayes
 
974 65 rehayes
    host.wb_write(0, XGATE_XGSEM,  16'hFFFF, L_BYTE);
975
    host.wb_cmp(0, XGATE_XGSEM,    16'h0000, WORD);
976
    host.wb_write(0, XGATE_XGSEM,  16'hFFFF, H_BYTE);
977
    host.wb_cmp(0, XGATE_XGSEM,    16'h0000, WORD);
978 41 rehayes
 
979 65 rehayes
    // Test the Xgate Condition Code Register (XGCCR)
980
    host.wb_write(0, XGATE_XGCCR,  16'hFFFF, L_BYTE);
981
    host.wb_cmp(0, XGATE_XGCCR,    16'h000F, WORD);
982
    host.wb_write(0, XGATE_XGCCR,  16'hFFF0, WORD);
983
    host.wb_cmp(0, XGATE_XGCCR,    16'h0000, WORD);
984 41 rehayes
 
985 65 rehayes
    // Test the Xgate Program Counter Register (XGPC)
986
    host.wb_write(0, XGATE_XGPC,  16'hFF55, L_BYTE);
987
    host.wb_cmp(0, XGATE_XGPC,    16'h0055, WORD);
988
    host.wb_write(0, XGATE_XGPC,  16'hAAFF, H_BYTE);
989
    host.wb_cmp(0, XGATE_XGPC,    16'hAA55, WORD);
990
    host.wb_write(0, XGATE_XGPC,  16'h9966, WORD);
991
    host.wb_cmp(0, XGATE_XGPC,    16'h9966, WORD);
992 41 rehayes
 
993 65 rehayes
    // Test the Xgate Register #1 (XGR1)
994
    host.wb_write(0, XGATE_XGR1,  16'hFF33, L_BYTE);
995
    host.wb_cmp(0, XGATE_XGR1,    16'h0033, WORD);
996
    host.wb_write(0, XGATE_XGR1,  16'hccFF, H_BYTE);
997
    host.wb_cmp(0, XGATE_XGR1,    16'hcc33, WORD);
998
    host.wb_write(0, XGATE_XGR1,  16'hf11f, WORD);
999
    host.wb_cmp(0, XGATE_XGR1,    16'hf11f, WORD);
1000 41 rehayes
 
1001 65 rehayes
    // Test the Xgate Register #2 (XGR2)
1002
    host.wb_write(0, XGATE_XGR2,  16'hFF11, L_BYTE);
1003
    host.wb_cmp(0, XGATE_XGR2,    16'h0011, WORD);
1004
    host.wb_write(0, XGATE_XGR2,  16'h22FF, H_BYTE);
1005
    host.wb_cmp(0, XGATE_XGR2,    16'h2211, WORD);
1006
    host.wb_write(0, XGATE_XGR2,  16'hddee, WORD);
1007
    host.wb_cmp(0, XGATE_XGR2,    16'hddee, WORD);
1008 41 rehayes
 
1009 65 rehayes
    // Test the Xgate Register #3 (XGR3)
1010
    host.wb_write(0, XGATE_XGR3,  16'hFF43, L_BYTE);
1011
    host.wb_cmp(0, XGATE_XGR3,    16'h0043, WORD);
1012
    host.wb_write(0, XGATE_XGR3,  16'h54FF, H_BYTE);
1013
    host.wb_cmp(0, XGATE_XGR3,    16'h5443, WORD);
1014
    host.wb_write(0, XGATE_XGR3,  16'habbc, WORD);
1015
    host.wb_cmp(0, XGATE_XGR3,    16'habbc, WORD);
1016 41 rehayes
 
1017 65 rehayes
    // Test the Xgate Register #4 (XGR4)
1018
    host.wb_write(0, XGATE_XGR4,  16'hFF54, L_BYTE);
1019
    host.wb_cmp(0, XGATE_XGR4,    16'h0054, WORD);
1020
    host.wb_write(0, XGATE_XGR4,  16'h65FF, H_BYTE);
1021
    host.wb_cmp(0, XGATE_XGR4,    16'h6554, WORD);
1022
    host.wb_write(0, XGATE_XGR4,  16'h9aab, WORD);
1023
    host.wb_cmp(0, XGATE_XGR4,    16'h9aab, WORD);
1024 41 rehayes
 
1025 65 rehayes
    // Test the Xgate Register #5 (XGR5)
1026
    host.wb_write(0, XGATE_XGR5,  16'hFF65, L_BYTE);
1027
    host.wb_cmp(0, XGATE_XGR5,    16'h0065, WORD);
1028
    host.wb_write(0, XGATE_XGR5,  16'h76FF, H_BYTE);
1029
    host.wb_cmp(0, XGATE_XGR5,    16'h7665, WORD);
1030
    host.wb_write(0, XGATE_XGR5,  16'h899a, WORD);
1031
    host.wb_cmp(0, XGATE_XGR5,    16'h899a, WORD);
1032 41 rehayes
 
1033 65 rehayes
    // Test the Xgate Register #6 (XGR6)
1034
    host.wb_write(0, XGATE_XGR6,  16'hFF76, L_BYTE);
1035
    host.wb_cmp(0, XGATE_XGR6,    16'h0076, WORD);
1036
    host.wb_write(0, XGATE_XGR6,  16'h87FF, H_BYTE);
1037
    host.wb_cmp(0, XGATE_XGR6,    16'h8776, WORD);
1038
    host.wb_write(0, XGATE_XGR6,  16'h7889, WORD);
1039
    host.wb_cmp(0, XGATE_XGR6,    16'h7889, WORD);
1040 41 rehayes
 
1041 65 rehayes
    // Test the Xgate Register #7 (XGR7)
1042
    host.wb_write(0, XGATE_XGR7,  16'hFF87, L_BYTE);
1043
    host.wb_cmp(0, XGATE_XGR7,    16'h0087, WORD);
1044
    host.wb_write(0, XGATE_XGR7,  16'h98FF, H_BYTE);
1045
    host.wb_cmp(0, XGATE_XGR7,    16'h9887, WORD);
1046
    host.wb_write(0, XGATE_XGR7,  16'h6778, WORD);
1047
    host.wb_cmp(0, XGATE_XGR7,    16'h6778, WORD);
1048 41 rehayes
 
1049 65 rehayes
    host.wb_cmp(0, XGATE_XGPC,    16'h9966, WORD);
1050
    host.wb_cmp(0, XGATE_XGR1,    16'hf11f, WORD);
1051
    host.wb_cmp(0, XGATE_XGR2,    16'hddee, WORD);
1052
    host.wb_cmp(0, XGATE_XGR3,    16'habbc, WORD);
1053
    host.wb_cmp(0, XGATE_XGR4,    16'h9aab, WORD);
1054
    host.wb_cmp(0, XGATE_XGR5,    16'h899a, WORD);
1055
    host.wb_cmp(0, XGATE_XGR6,    16'h7889, WORD);
1056
    host.wb_cmp(0, XGATE_XGR7,    16'h6778, WORD);
1057 41 rehayes
 
1058 2 rehayes
  end
1059
endtask
1060
 
1061 68 rehayes
////////////////////////////////////////////////////////////////////////////////
1062 73 rehayes
// check irq register bits - reset, read/write
1063 68 rehayes
task reg_irq;
1064
  begin
1065
    test_num = test_num + 1;
1066
    $display("\nTEST #%d Starts at vector=%d, reg_irq", test_num, vector);
1067
    $readmemh("../../../bench/verilog/irq_test.v", p_ram.ram_8);
1068 2 rehayes
 
1069 68 rehayes
    system_reset;
1070
 
1071 89 rehayes
    host.wb_cmp(0, IRQ_BYPS_0,   16'hFFFE, WORD); // verify reset
1072
    host.wb_cmp(0, IRQ_BYPS_1,   16'hFFFF, WORD); // verify reset
1073
    host.wb_cmp(0, IRQ_BYPS_2,   16'hFFFF, WORD); // verify reset
1074
    host.wb_cmp(0, IRQ_BYPS_3,   16'hFFFF, WORD); // verify reset
1075
    host.wb_cmp(0, IRQ_BYPS_4,   16'hFFFF, WORD); // verify reset
1076
    host.wb_cmp(0, IRQ_BYPS_5,   16'hFFFF, WORD); // verify reset
1077
    host.wb_cmp(0, IRQ_BYPS_6,   16'hFFFF, WORD); // verify reset
1078
    host.wb_cmp(0, IRQ_BYPS_7,   16'hFFFF, WORD); // verify reset
1079 68 rehayes
 
1080
 
1081
    // Test the Xgate IRQ Bypass Registers (IRQ_BYPS)
1082
    host.wb_write(0, IRQ_BYPS_0,  16'hAAAA, WORD);
1083
    host.wb_cmp(0, IRQ_BYPS_0,    16'hAAAA, WORD);
1084
    host.wb_write(0, IRQ_BYPS_0,  16'h5555, WORD);
1085 73 rehayes
    host.wb_cmp(0, IRQ_BYPS_0,    16'h5554, WORD);
1086 68 rehayes
 
1087
    host.wb_write(0, IRQ_BYPS_0,  16'hFF66, L_BYTE);
1088
    host.wb_cmp(0, IRQ_BYPS_0,    16'h5566, WORD);
1089
    host.wb_write(0, IRQ_BYPS_0,  16'h33FF, H_BYTE);
1090
    host.wb_cmp(0, IRQ_BYPS_0,    16'h3366, WORD);
1091
    host.wb_write(0, IRQ_BYPS_0,  16'hFFFF, H_BYTE);
1092
 
1093
    channel_req[17] = 1'b1; //
1094
    repeat(4) @(posedge mstr_test_clk);
1095
    host.wb_cmp(0, CHANNEL_XGIRQ_1,    16'h0002, WORD);
1096
    channel_req[17] = 1'b0; //
1097
    repeat(4) @(posedge mstr_test_clk);
1098
    host.wb_cmp(0, CHANNEL_XGIRQ_1,    16'h0000, WORD);
1099
 
1100
    host.wb_write(0, TB_SEMPHORE,  16'h0000, WORD);
1101
    host.wb_write(0, IRQ_BYPS_0,  16'h0000, WORD);
1102
    host.wb_write(0, IRQ_BYPS_0,  16'h0000, WORD);
1103
    data_xgmctl = XGMCTL_XGEM | XGMCTL_XGE;
1104
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Enable XGATE
1105
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
1106
    channel_req[3:1] = 3'b111; //
1107
 
1108
    q = 0;
1109 89 rehayes
    // The Xgate test program is in an infinite loop for the test bench semaphore register to be changed
1110 68 rehayes
    while (q == 0)  // Look for change in test bench semapore register
1111
      begin
1112 89 rehayes
        host.wb_read(1, TB_SEMPHORE, q, WORD);
1113 68 rehayes
      end
1114 89 rehayes
 
1115 68 rehayes
    if (q != 1)
1116
      begin
1117 89 rehayes
        $display("IRQ test failure, Wrong interrupt being processed! Interrupt=%d, vector=%d", q, vector);
1118 68 rehayes
      end
1119 89 rehayes
 
1120 68 rehayes
    channel_req[1] = 1'b0; //
1121
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
1122
    host.wb_write(0, TB_SEMPHORE,  16'h0000, WORD);
1123
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
1124
 
1125
//    host.wb_cmp(0, CHANNEL_XGIRQ_0, 16'h0002, WORD);  // Verify Xgate output interrupt flag set
1126
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0002, WORD);  // Verify Xgate interrupt status bit set
1127
    host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);  // Clear Interrupt Flag from Xgate
1128
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0000, WORD);  // Verify flag cleared
1129 89 rehayes
 
1130 68 rehayes
    q = 0;
1131 89 rehayes
    // The Xgate test program is in an infinite loop for the test bench semaphore register to be changed
1132 68 rehayes
    while (q == 0)  // Look for change in test bench semapore register
1133
      begin
1134 89 rehayes
        host.wb_read(1, TB_SEMPHORE, q, WORD);
1135 68 rehayes
      end
1136 89 rehayes
 
1137 68 rehayes
    if (q != 2)
1138
      begin
1139 89 rehayes
        $display("IRQ test failure, Wrong interrupt being processed! Interrupt=%d, vector=%d", q, vector);
1140 68 rehayes
      end
1141 89 rehayes
 
1142 68 rehayes
    channel_req[2] = 1'b0; //
1143
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
1144
    host.wb_write(0, TB_SEMPHORE,  16'h0000, WORD);
1145
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
1146 89 rehayes
 
1147 68 rehayes
//    host.wb_cmp(0, CHANNEL_XGIRQ_0, 16'h0002, WORD);  // Verify Xgate output interrupt flag set
1148
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0002, WORD);  // Verify Xgate interrupt status bit set
1149
    host.wb_write(1, XGATE_XGIF_0, 16'h0004, WORD);  // Clear Interrupt Flag from Xgate
1150
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0000, WORD);  // Verify flag cleared
1151 89 rehayes
 
1152 68 rehayes
    q = 0;
1153 89 rehayes
    // The Xgate test program is in an infinite loop for the test bench semaphore register to be changed
1154 68 rehayes
    while (q == 0)  // Look for change in test bench semapore register
1155
      begin
1156 89 rehayes
        host.wb_read(1, TB_SEMPHORE, q, WORD);
1157 68 rehayes
      end
1158 89 rehayes
 
1159 68 rehayes
    if (q != 3)
1160
      begin
1161 89 rehayes
        $display("IRQ test failure, Wrong interrupt being processed! Interrupt=%d, vector=%d", q, vector);
1162 68 rehayes
      end
1163 89 rehayes
 
1164 68 rehayes
    channel_req[3] = 1'b0; //
1165
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
1166
    host.wb_write(0, TB_SEMPHORE,  16'h0000, WORD);
1167
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
1168 89 rehayes
 
1169 68 rehayes
//    host.wb_cmp(0, CHANNEL_XGIRQ_0, 16'h0002, WORD);  // Verify Xgate output interrupt flag set
1170
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0002, WORD);  // Verify Xgate interrupt status bit set
1171
    host.wb_write(1, XGATE_XGIF_0, 16'h0008, WORD);  // Clear Interrupt Flag from Xgate
1172
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0000, WORD);  // Verify flag cleared
1173 89 rehayes
 
1174 68 rehayes
  end
1175
endtask
1176
 
1177
 
1178 36 rehayes
////////////////////////////////////////////////////////////////////////////////
1179
// check RAM Read/Write from host
1180
task host_ram;
1181
  begin
1182
    test_num = test_num + 1;
1183 65 rehayes
    $display("\nTEST #%d Starts at vector=%d, host_ram", test_num, vector);
1184 36 rehayes
 
1185
    host.wb_write(1, SYS_RAM_BASE, 16'h5555, WORD);
1186
    host.wb_cmp(  0, SYS_RAM_BASE, 16'h5555, WORD);
1187
 
1188
    repeat(5) @(posedge mstr_test_clk);
1189
    p_ram.dump_ram(0);
1190
 
1191
  end
1192
endtask
1193
 
1194
////////////////////////////////////////////////////////////////////////////////
1195 11 rehayes
// Poll for XGATE Interrupt set
1196
task wait_irq_set;
1197
  input [ 6:0] chan_val;
1198
  begin
1199
    while(!xgif[chan_val])
1200
      @(posedge mstr_test_clk); // poll it until it is set
1201
    $display("XGATE Interrupt Request #%d set detected at vector =%d", chan_val, vector);
1202
  end
1203
endtask
1204 2 rehayes
 
1205 36 rehayes
////////////////////////////////////////////////////////////////////////////////
1206 11 rehayes
// Poll for debug bit set
1207
task wait_debug_set;
1208
  begin
1209 36 rehayes
    host.wb_read(1, XGATE_XGMCTL, q, WORD);
1210 11 rehayes
    while(~|(q & XGMCTL_XGDBG))
1211 36 rehayes
      host.wb_read(1, XGATE_XGMCTL, q, WORD); // poll it until it is set
1212 11 rehayes
    $display("DEBUG Flag set detected at vector =%d", vector);
1213
  end
1214
endtask
1215 2 rehayes
 
1216 11 rehayes
 
1217 36 rehayes
////////////////////////////////////////////////////////////////////////////////
1218 2 rehayes
task system_reset;  // reset system
1219
  begin
1220 89 rehayes
    repeat(1) @(posedge mstr_test_clk);
1221
    sync_reset = 1'b1;  // Make the sync reset 1 clock cycle long
1222
    #2;     // move the async reset away from the clock edge
1223
    rstn = 1'b0;    // assert async reset
1224
    #5;     // Keep the async reset pulse with less than a clock cycle
1225
    rstn = 1'b1;    // negate async reset
1226
    repeat(1) @(posedge mstr_test_clk);
1227
    sync_reset = 1'b0;
1228 2 rehayes
 
1229 89 rehayes
    $display("\nstatus: %t System Reset Task Done", $time);
1230
    test_num = test_num + 1;
1231 2 rehayes
 
1232 89 rehayes
    repeat(2) @(posedge mstr_test_clk);
1233
  end
1234 2 rehayes
endtask
1235
 
1236
 
1237 36 rehayes
////////////////////////////////////////////////////////////////////////////////
1238 2 rehayes
task activate_channel;
1239
  input [ 6:0] chan_val;
1240
  begin
1241 21 rehayes
    $display("Activating Channel %d", chan_val);
1242 2 rehayes
 
1243 21 rehayes
    channel_req[chan_val] = 1'b1; //
1244
    repeat(1) @(posedge mstr_test_clk);
1245 2 rehayes
  end
1246
endtask
1247
 
1248
 
1249 36 rehayes
////////////////////////////////////////////////////////////////////////////////
1250 2 rehayes
task clear_channel;
1251
  input [ 6:0] chan_val;
1252
  begin
1253 21 rehayes
    $display("Clearing Channel interrupt input #%d", chan_val);
1254 2 rehayes
 
1255 21 rehayes
    channel_req[chan_val] = 1'b0; //
1256
    repeat(1) @(posedge mstr_test_clk);
1257
  end
1258 2 rehayes
endtask
1259
 
1260
 
1261 36 rehayes
////////////////////////////////////////////////////////////////////////////////
1262 2 rehayes
task clear_irq_flag;
1263
  input [ 6:0] chan_val;
1264
  begin
1265
      $display("Clearing Channel interrupt flag #%d", chan_val);
1266
      if (0 < chan_val < 16)
1267 89 rehayes
        host.wb_write(1, XGATE_XGIF_0, 16'hffff, WORD);
1268 2 rehayes
      if (15 < chan_val < 32)
1269 89 rehayes
        host.wb_write(1, XGATE_XGIF_1, 16'hffff, WORD);
1270 2 rehayes
      if (31 < chan_val < 48)
1271 89 rehayes
        host.wb_write(1, XGATE_XGIF_2, 16'hffff, WORD);
1272 2 rehayes
      if (47 < chan_val < 64)
1273 89 rehayes
        host.wb_write(1, XGATE_XGIF_3, 16'hffff, WORD);
1274 2 rehayes
      if (63 < chan_val < 80)
1275 89 rehayes
        host.wb_write(1, XGATE_XGIF_4, 16'hffff, WORD);
1276 2 rehayes
      if (79 < chan_val < 96)
1277 89 rehayes
        host.wb_write(1, XGATE_XGIF_5, 16'hffff, WORD);
1278 2 rehayes
      if (95 < chan_val < 112)
1279 89 rehayes
        host.wb_write(1, XGATE_XGIF_6, 16'hffff, WORD);
1280 2 rehayes
      if (111 < chan_val < 128)
1281 89 rehayes
        host.wb_write(1, XGATE_XGIF_7, 16'hffff, WORD);
1282 2 rehayes
 
1283 21 rehayes
      channel_req[chan_val] = 1'b0; //
1284 2 rehayes
      repeat(1) @(posedge mstr_test_clk);
1285
   end
1286
endtask
1287
 
1288
 
1289 36 rehayes
////////////////////////////////////////////////////////////////////////////////
1290 2 rehayes
task activate_thread_sw;
1291
  input [ 6:0] chan_val;
1292
  begin
1293 50 rehayes
      $display("Activating Software Thread - Channel #%d", chan_val);
1294 2 rehayes
 
1295 11 rehayes
      data_xgmctl = XGMCTL_XGEM | XGMCTL_XGE;
1296 36 rehayes
      host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Enable XGATE
1297 2 rehayes
 
1298 21 rehayes
      channel_req[chan_val] = 1'b1; //
1299 2 rehayes
      repeat(1) @(posedge mstr_test_clk);
1300
   end
1301
endtask
1302
 
1303 36 rehayes
////////////////////////////////////////////////////////////////////////////////
1304 41 rehayes
task read_ram_cmp;
1305
  input [15:0] address;
1306
  input [15:0] value;
1307 89 rehayes
  reg [15:0] q;
1308 41 rehayes
  begin
1309
 
1310
      // BIGENDIAN
1311
      q = {p_ram.ram_8[address], p_ram.ram_8[address+1]};
1312
      // "X" compares don't work, "X" in value or q always match
1313
      if (value != q)
1314 89 rehayes
        begin
1315
          error_count = error_count + 1;
1316
          $display("RAM Data compare error at address %h. Received %h, expected %h at time %t", address, q, value, $time);
1317
        end
1318 41 rehayes
   end
1319
endtask
1320
 
1321
////////////////////////////////////////////////////////////////////////////////
1322 5 rehayes
task wrap_up;
1323
  begin
1324 21 rehayes
    test_num = test_num + 1;
1325
    repeat(10) @(posedge mstr_test_clk);
1326 5 rehayes
    $display("\nSimulation Finished!! - vector =%d", vector);
1327
    if (error_count == 0)
1328
      $display("Simulation Passed");
1329
    else
1330 21 rehayes
      $display("Simulation Failed  --- Errors =%d", error_count);
1331 5 rehayes
 
1332
    $finish;
1333
  end
1334
endtask
1335
 
1336 36 rehayes
////////////////////////////////////////////////////////////////////////////////
1337 2 rehayes
function [15:0] four_2_16;
1338
  input [3:0] vector;
1339
  begin
1340
    case (vector)
1341
      4'h0 : four_2_16 = 16'b0000_0000_0000_0001;
1342
      4'h1 : four_2_16 = 16'b0000_0000_0000_0010;
1343
      4'h2 : four_2_16 = 16'b0000_0000_0000_0100;
1344
      4'h3 : four_2_16 = 16'b0000_0000_0000_1000;
1345
      4'h4 : four_2_16 = 16'b0000_0000_0001_0000;
1346
      4'h5 : four_2_16 = 16'b0000_0000_0010_0000;
1347
      4'h6 : four_2_16 = 16'b0000_0000_0100_0000;
1348
      4'h7 : four_2_16 = 16'b0000_0000_1000_0000;
1349
      4'h8 : four_2_16 = 16'b0000_0001_0000_0000;
1350
      4'h9 : four_2_16 = 16'b0000_0010_0000_0000;
1351
      4'ha : four_2_16 = 16'b0000_0100_0000_0000;
1352
      4'hb : four_2_16 = 16'b0000_1000_0000_0000;
1353
      4'hc : four_2_16 = 16'b0001_0000_0000_0000;
1354
      4'hd : four_2_16 = 16'b0010_0000_0000_0000;
1355
      4'he : four_2_16 = 16'b0100_0000_0000_0000;
1356
      4'hf : four_2_16 = 16'b1000_0000_0000_0000;
1357
    endcase
1358
  end
1359
endfunction
1360
 
1361
endmodule  // tst_bench_top
1362
 
1363 36 rehayes
////////////////////////////////////////////////////////////////////////////////
1364
////////////////////////////////////////////////////////////////////////////////
1365
////////////////////////////////////////////////////////////////////////////////
1366 89 rehayes
module bus_arbitration  #(parameter dwidth = 16,
1367
        parameter awidth    = 24,
1368
        parameter ram_base  = 0,
1369
        parameter ram_size  = 16'hffff,
1370
        parameter slv1_base = 0,
1371
        parameter slv1_size = 1,
1372
        parameter slv2_base = 0,
1373
        parameter slv2_size = 1,
1374 65 rehayes
                          parameter ram_wait_states = 0) // Number between 0 and 15
1375 36 rehayes
  (
1376
  // System bus I/O
1377 89 rehayes
  output reg                 sys_cyc,
1378
  output reg                 sys_stb,
1379
  output reg                 sys_we,
1380 54 rehayes
  output reg [dwidth/8 -1:0] sys_sel,
1381
  output reg [awidth   -1:0] sys_adr,
1382
  output reg [dwidth   -1:0] sys_dout,
1383
  output     [dwidth   -1:0] sys_din,
1384 62 rehayes
 
1385 36 rehayes
  // Host bus I/O
1386 89 rehayes
  output         host_ack,
1387 36 rehayes
  output     [dwidth   -1:0] host_dout,
1388 89 rehayes
  input          host_cyc,
1389
  input          host_stb,
1390
  input          host_we,
1391
  input      [dwidth/8 -1:0] host_sel,
1392
  input      [awidth   -1:0] host_adr,
1393
  input      [dwidth   -1:0] host_din,
1394 62 rehayes
 
1395 36 rehayes
  // Alternate Bus Master #1 Bus I/O
1396 89 rehayes
  output         alt1_ack,
1397 36 rehayes
  output     [dwidth   -1:0] alt1_dout,
1398 89 rehayes
  input          alt1_cyc,
1399
  input          alt1_stb,
1400
  input          alt1_we,
1401
  input      [dwidth/8 -1:0] alt1_sel,
1402
  input      [awidth   -1:0] alt1_adr,
1403
  input      [dwidth   -1:0] alt1_din,
1404 62 rehayes
 
1405 54 rehayes
  // System RAM memory signals
1406 89 rehayes
  output         ram_sel,
1407
  input      [dwidth   -1:0] ram_dout,
1408 54 rehayes
 
1409 36 rehayes
  // Slave #1 Bus I/O
1410 89 rehayes
  output         slv1_stb,
1411
  input          slv1_ack,
1412
  input      [dwidth   -1:0] slv1_din,
1413 62 rehayes
 
1414 36 rehayes
  // Slave #2 Bus I/O
1415 89 rehayes
  output         slv2_stb,
1416
  input          slv2_ack,
1417
  input      [dwidth   -1:0] slv2_din,
1418 62 rehayes
 
1419 36 rehayes
  // Miscellaneous
1420 89 rehayes
  input          host_clk,
1421
  input          risc_clk,
1422
  input          rst,       // No Connect
1423
  input          err,       // No Connect
1424
  input          rty        // No Connect
1425 36 rehayes
  );
1426 62 rehayes
 
1427 60 rehayes
  // States for bus arbitration
1428 89 rehayes
  parameter [1:0] BUS_IDLE  = 2'b00,
1429
                  HOST_OWNS = 2'b10,
1430
                  RISC_OWNS = 2'b11;
1431 62 rehayes
 
1432 89 rehayes
  parameter max_bus_hold = 5;  // Max number of cycles any bus master can hold the system bus
1433 36 rehayes
  //////////////////////////////////////////////////////////////////////////////
1434
  //
1435
  // Local Wires and Registers
1436
  //
1437 89 rehayes
  wire       ram_ack;        //
1438
  wire       any_ack;        //
1439
  reg        host_wait;      // Host bus in wait state, Hold the bus till the transaction complets
1440 36 rehayes
  reg  [3:0] host_cycle_cnt; // Used to count the cycle the host and break the lock if the risc needs access
1441 62 rehayes
 
1442 89 rehayes
  wire       risc_lock;      // RISC has the slave bus
1443
  reg        risc_wait;      // RISC bus in wait state, Hold the bus till the transaction complets
1444 36 rehayes
  reg  [3:0] risc_cycle_cnt; // Used to count the cycle the risc and break the lock if the host needs access
1445 62 rehayes
 
1446 54 rehayes
  reg  [1:0] owner_state;
1447
  reg  [1:0] owner_ns;
1448 36 rehayes
 
1449 89 rehayes
  wire       host_timeout;
1450
  wire       risc_timeout;
1451 62 rehayes
 
1452 89 rehayes
  wire       ram_ack_dly;    // Delayed bus ack to simulate bus wait states
1453 60 rehayes
  reg  [3:0] ack_dly_cnt;    // Counter to delay bus ack to master modules
1454 54 rehayes
 
1455
 
1456
  //
1457 36 rehayes
  always @(posedge host_clk or negedge rst)
1458
    if (!rst)
1459 54 rehayes
      owner_state <= BUS_IDLE;
1460 36 rehayes
    else
1461 54 rehayes
      owner_state <= owner_ns;
1462 62 rehayes
 
1463 54 rehayes
  //
1464
  always @*
1465
    case (owner_state)
1466
      BUS_IDLE :
1467 89 rehayes
        begin
1468
          if (host_cyc)
1469
            owner_ns = HOST_OWNS;
1470
          else if (alt1_cyc)
1471
            owner_ns = RISC_OWNS;
1472
        end
1473 54 rehayes
      HOST_OWNS :
1474 89 rehayes
        begin
1475
          if (!host_cyc && !alt1_cyc)
1476
            owner_ns = BUS_IDLE;
1477
          else if (alt1_cyc && (!host_cyc || host_timeout))
1478
            owner_ns = RISC_OWNS;
1479
        end
1480 54 rehayes
      RISC_OWNS :
1481 89 rehayes
        begin
1482
          if (!host_cyc && !alt1_cyc)
1483
            owner_ns = BUS_IDLE;
1484
          else if (host_cyc && (!alt1_cyc || risc_timeout))
1485
            owner_ns = HOST_OWNS;
1486
        end
1487 54 rehayes
      default : owner_ns = BUS_IDLE;
1488
    endcase
1489 36 rehayes
 
1490 62 rehayes
 
1491 60 rehayes
  assign host_timeout = (owner_state == HOST_OWNS) && (host_cycle_cnt > max_bus_hold) && any_ack;
1492
  assign risc_timeout = (owner_state == RISC_OWNS) && (risc_cycle_cnt > max_bus_hold) && any_ack;
1493 54 rehayes
 
1494
  // Start counting cycles that the host has the bus, if the risc is also requesting the bus
1495 36 rehayes
  always @(posedge host_clk or negedge rst)
1496
    if (!rst)
1497
      host_cycle_cnt <= 0;
1498 54 rehayes
    else if ((owner_state != HOST_OWNS) || !alt1_cyc)
1499
      host_cycle_cnt <= 0;
1500 89 rehayes
    else if (&host_cycle_cnt && !host_timeout)  // Don't allow rollover
1501 54 rehayes
      host_cycle_cnt <= host_cycle_cnt;
1502
    else if ((owner_state == HOST_OWNS) && alt1_cyc)
1503
      host_cycle_cnt <= host_cycle_cnt + 1'b1;
1504 36 rehayes
 
1505 54 rehayes
  // Start counting cycles that the risc has the bus, if the host is also requesting the bus
1506 36 rehayes
  always @(posedge host_clk or negedge rst)
1507
    if (!rst)
1508
      risc_cycle_cnt <= 0;
1509 54 rehayes
    else if ((owner_state != RISC_OWNS) || !host_cyc)
1510
      risc_cycle_cnt <= 0;
1511 89 rehayes
    else if (&risc_cycle_cnt && !risc_timeout)  // Don't allow rollover
1512 54 rehayes
      risc_cycle_cnt <= risc_cycle_cnt;
1513
    else if ((owner_state == RISC_OWNS) && host_cyc)
1514
      risc_cycle_cnt <= risc_cycle_cnt + 1'b1;
1515 36 rehayes
 
1516 62 rehayes
  // Aribartration Logic for System Bus access
1517 54 rehayes
  assign any_ack  = slv1_ack || slv2_ack || ram_ack;
1518
  assign host_ack = (owner_state == HOST_OWNS) && any_ack && host_cyc;
1519
  assign alt1_ack = (owner_state == RISC_OWNS) && any_ack && alt1_cyc;
1520 36 rehayes
 
1521 54 rehayes
 
1522
  // Address decoding for different Slave module instances
1523
  assign slv1_stb = sys_stb && (sys_adr >= slv1_base) && (sys_adr < (slv1_base + slv1_size));
1524
  assign slv2_stb = sys_stb && (sys_adr >= slv2_base) && (sys_adr < (slv2_base + slv2_size));
1525 62 rehayes
 
1526 36 rehayes
  // Address decoding for Testbench access to RAM
1527 54 rehayes
  assign ram_sel = sys_cyc && sys_stb && !(slv1_stb || slv2_stb) &&
1528 89 rehayes
                   (sys_adr >= ram_base) &&
1529
                   (sys_adr < (ram_base + ram_size));
1530 62 rehayes
 
1531 60 rehayes
  // Throw in some wait states from the memory
1532
  always @(posedge host_clk)
1533
    if ((ack_dly_cnt == ram_wait_states) || !ram_sel)
1534
      ack_dly_cnt <= 0;
1535
    else if (ram_sel)
1536
      ack_dly_cnt <= ack_dly_cnt + 1'b1;
1537 36 rehayes
 
1538 60 rehayes
  assign ram_ack_dly = (ack_dly_cnt == ram_wait_states);
1539
  assign ram_ack = ram_sel && ram_ack_dly;
1540 36 rehayes
 
1541 60 rehayes
 
1542 54 rehayes
  // Create the System Read Data Bus from the Slave output data buses
1543 68 rehayes
  assign sys_din = ({dwidth{1'b1}} & slv1_din) |
1544 89 rehayes
       ({dwidth{slv2_stb}} & slv2_din) |
1545
       ({dwidth{ram_sel}}  & ram_dout);
1546 36 rehayes
 
1547 54 rehayes
  // Mux for System Bus access
1548
  always @*
1549
    case (owner_state)
1550
      BUS_IDLE :
1551 89 rehayes
        begin
1552
          sys_cyc   = 0;
1553
          sys_stb   = 0;
1554
          sys_we    = 0;
1555
          sys_sel   = 0;
1556
          sys_adr   = 0;
1557
          sys_dout  = 0;
1558
        end
1559 54 rehayes
      HOST_OWNS :
1560 89 rehayes
        begin
1561
          sys_cyc   = host_cyc;
1562
          sys_stb   = host_stb;
1563
          sys_we    = host_we;
1564
          sys_sel   = host_sel;
1565
          sys_adr   = host_adr;
1566
          sys_dout  = host_din;
1567
        end
1568 54 rehayes
      RISC_OWNS :
1569 89 rehayes
        begin
1570
          sys_cyc   = alt1_cyc;
1571
          sys_stb   = alt1_stb;
1572
          sys_we    = alt1_we;
1573
          sys_sel   = alt1_sel;
1574
          sys_adr   = alt1_adr;
1575
          sys_dout  = alt1_din;
1576
        end
1577 54 rehayes
      default :
1578 89 rehayes
        begin
1579
          sys_cyc   = 0;
1580
          sys_stb   = 0;
1581
          sys_we    = 0;
1582
          sys_sel   = 0;
1583
          sys_adr   = 0;
1584
          sys_dout  = 0;
1585
        end
1586 54 rehayes
    endcase
1587 36 rehayes
 
1588 54 rehayes
endmodule   // bus_arbitration
1589 36 rehayes
 
1590 54 rehayes
////////////////////////////////////////////////////////////////////////////////
1591
////////////////////////////////////////////////////////////////////////////////
1592
////////////////////////////////////////////////////////////////////////////////
1593
module tb_slave #(parameter SINGLE_CYCLE = 1'b0,  // No bus wait state added
1594 89 rehayes
                  parameter MAX_CHANNEL  = 127,   // Max XGATE Interrupt Channel Number
1595
                  parameter DWIDTH       = 16)    // Data bus width
1596 54 rehayes
  (
1597
  // Wishbone Signals
1598 89 rehayes
  output [DWIDTH-1:0] wb_dat_o,     // databus output
1599
  output              wb_ack_o,     // bus cycle acknowledge output
1600
  input               wb_clk_i,     // master clock input
1601
  input               wb_rst_i,     // synchronous active high reset
1602
  input               arst_i,       // asynchronous reset
1603
  input        [ 3:0] wb_adr_i,     // lower address bits
1604
  input  [DWIDTH-1:0] wb_dat_i,     // databus input
1605
  input               wb_we_i,      // write enable input
1606
  input               wb_stb_i,     // stobe/core select signal
1607
  input               wb_cyc_i,     // valid bus cycle input
1608
  input        [ 1:0] wb_sel_i,     // Select byte in word bus transaction
1609 62 rehayes
  // Slave unique IO Signals
1610 89 rehayes
  output reg              error_pulse,  // Error detected output pulse
1611
  output reg              ack_pulse,    // Thread ack output pulse
1612 82 rehayes
  output reg [DWIDTH-1:0] brkpt_cntl,   // Break Point Control reg
1613
 
1614 89 rehayes
  output                brk_pt,       // Break point
1615
  input          [15:0] x_address,    // XGATE WISHBONE Master bus address
1616
  input [MAX_CHANNEL:1] xgif,         // XGATE Interrupt Flag to Host
1617
  input          [19:0] vector
1618 54 rehayes
  );
1619 62 rehayes
 
1620 89 rehayes
  wire      async_rst_b;   // Asyncronous reset
1621
  wire      sync_reset;    // Syncronous reset
1622 62 rehayes
 
1623 54 rehayes
  // Wishbone Bus interface
1624
  // registers
1625 89 rehayes
  reg               bus_wait_state;  // Holdoff wb_ack_o for one clock to add wait state
1626 68 rehayes
  reg  [DWIDTH-1:0] rd_data_mux;     // Pseudo Register, WISHBONE Read Data Mux
1627
  reg  [DWIDTH-1:0] rd_data_reg;     // Latch for WISHBONE Read Data
1628 36 rehayes
 
1629 68 rehayes
  reg  [DWIDTH-1:0] check_point_reg;
1630
  reg  [DWIDTH-1:0] channel_ack_reg;
1631
  reg  [DWIDTH-1:0] channel_err_reg;
1632 36 rehayes
 
1633 68 rehayes
  reg  [DWIDTH-1:0] brkpt_addr_reg;  // Break Point Address reg
1634 65 rehayes
 
1635 68 rehayes
  reg  [DWIDTH-1:0] tb_semaphr_reg;  // Test bench semaphore reg
1636
 
1637 54 rehayes
  event check_point_wrt;
1638
  event channel_ack_wrt;
1639
  event channel_err_wrt;
1640 36 rehayes
 
1641 54 rehayes
  // Wires
1642 89 rehayes
  wire   module_sel;    // This module is selected for bus transaction
1643
  wire   wb_wacc;       // WISHBONE Write Strobe
1644
  wire   wb_racc;       // WISHBONE Read Access (Clock gating signal)
1645 36 rehayes
 
1646 54 rehayes
  //
1647
  // module body
1648
  //
1649 36 rehayes
 
1650 54 rehayes
  // generate internal resets
1651
 
1652
 
1653
  // generate wishbone signals
1654
  assign module_sel = wb_cyc_i && wb_stb_i;
1655
  assign wb_wacc    = module_sel && wb_we_i && (wb_ack_o || SINGLE_CYCLE);
1656
  assign wb_racc    = module_sel && !wb_we_i;
1657
  assign wb_ack_o   = SINGLE_CYCLE ? module_sel : bus_wait_state;
1658
  assign wb_dat_o   = SINGLE_CYCLE ? rd_data_mux : rd_data_reg;
1659
 
1660
  // generate acknowledge output signal, By using register all accesses takes two cycles.
1661
  //  Accesses in back to back clock cycles are not possable.
1662
  always @(posedge wb_clk_i or negedge arst_i)
1663
    if (!arst_i)
1664 89 rehayes
      bus_wait_state <=  1'b0;
1665 54 rehayes
    else if (wb_rst_i)
1666 89 rehayes
      bus_wait_state <=  1'b0;
1667 54 rehayes
    else
1668 89 rehayes
      bus_wait_state <=  module_sel && !bus_wait_state;
1669 54 rehayes
 
1670
  // assign data read bus -- DAT_O
1671
  always @(posedge wb_clk_i)
1672 89 rehayes
    if ( wb_racc )           // Clock gate for power saving
1673 54 rehayes
      rd_data_reg <= rd_data_mux;
1674
 
1675
  // WISHBONE Read Data Mux
1676
  always @*
1677
    case (wb_adr_i) // synopsys parallel_case
1678 68 rehayes
      4'b0000: rd_data_mux = check_point_reg;
1679
      4'b0001: rd_data_mux = channel_ack_reg;
1680
      4'b0010: rd_data_mux = channel_err_reg;
1681 82 rehayes
      4'b0011: rd_data_mux = brkpt_cntl;
1682 68 rehayes
      4'b0100: rd_data_mux = brkpt_addr_reg;
1683
      4'b0101: rd_data_mux = tb_semaphr_reg;
1684 73 rehayes
      4'b1000: rd_data_mux = {xgif[15: 1], 1'b0};
1685 68 rehayes
      4'b1001: rd_data_mux = xgif[31:16];
1686
      4'b1010: rd_data_mux = xgif[47:32];
1687
      4'b1011: rd_data_mux = xgif[63:48];
1688
      4'b1100: rd_data_mux = xgif[79:64];
1689
      4'b1101: rd_data_mux = xgif[95:80];
1690
      4'b1110: rd_data_mux = xgif[111:96];
1691
      4'b1111: rd_data_mux = xgif[127:112];
1692
      default: rd_data_mux = {DWIDTH{1'b0}};
1693 54 rehayes
    endcase
1694
 
1695
  // generate wishbone write register strobes
1696
  always @(posedge wb_clk_i or negedge arst_i)
1697
    begin
1698
      if (!arst_i)
1699 89 rehayes
        begin
1700
          check_point_reg <= 0;
1701
          channel_ack_reg <= 0;
1702
          channel_err_reg <= 0;
1703
          ack_pulse       <= 0;
1704
          error_pulse     <= 0;
1705
          brkpt_cntl      <= 0;
1706
          brkpt_addr_reg  <= 0;
1707
          tb_semaphr_reg  <= 0;
1708
        end
1709 54 rehayes
      else if (wb_wacc)
1710 89 rehayes
  case (wb_adr_i) // synopsys parallel_case
1711
     3'b000 :
1712
       begin
1713
         check_point_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : check_point_reg[ 7:0];
1714
         check_point_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : check_point_reg[15:8];
1715
         -> check_point_wrt;
1716
       end
1717
     3'b001 :
1718
       begin
1719
         channel_ack_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : channel_ack_reg[ 7:0];
1720
         channel_ack_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : channel_ack_reg[15:8];
1721
         ack_pulse <= 1;
1722
         -> channel_ack_wrt;
1723
       end
1724
     3'b010 :
1725
       begin
1726
         channel_err_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : channel_err_reg[ 7:0];
1727
         channel_err_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : channel_err_reg[15:8];
1728
         error_pulse <= 1'b1;
1729
         -> channel_err_wrt;
1730
       end
1731
     3'b011 :
1732
       begin
1733
         brkpt_cntl[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : brkpt_cntl[ 7:0];
1734
         brkpt_cntl[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : brkpt_cntl[15:8];
1735
       end
1736
     3'b100 :
1737
       begin
1738
         brkpt_addr_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : brkpt_addr_reg[ 7:0];
1739
         brkpt_addr_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : brkpt_addr_reg[15:8];
1740
       end
1741
     3'b101 :
1742
       begin
1743
         tb_semaphr_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : tb_semaphr_reg[ 7:0];
1744
         tb_semaphr_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : tb_semaphr_reg[15:8];
1745
       end
1746
     default: ;
1747
  endcase
1748 54 rehayes
      else
1749 89 rehayes
  begin
1750
    ack_pulse   <= 0;
1751
    error_pulse <= 1'b0;
1752
  end
1753 54 rehayes
    end
1754
 
1755
  always @check_point_wrt
1756
    begin
1757
      #1;
1758
      $display("\nSoftware Checkpoint #%h -- at vector=%d\n", check_point_reg, vector);
1759
    end
1760
 
1761
  always @channel_err_wrt
1762
    begin
1763
      #1;
1764 89 rehayes
      $display("\n ------ !!!!! Software Checkpoint Error #%d -- at vector=%d\n  -------", channel_err_reg, vector);
1765 54 rehayes
    end
1766
 
1767
 
1768
endmodule // tb_slave
1769
 
1770 82 rehayes
////////////////////////////////////////////////////////////////////////////////
1771
////////////////////////////////////////////////////////////////////////////////
1772
////////////////////////////////////////////////////////////////////////////////
1773 89 rehayes
module tb_debug #(parameter DWIDTH = 16,    // Data bus width
1774 82 rehayes
                  parameter BREAK_CAPT_0 = 0,
1775
                  parameter BREAK_CAPT_1 = 0,
1776
                  parameter BREAK_CAPT_2 = 0,
1777
                  parameter BREAK_CAPT_3 = 0,
1778
                  parameter BREAK_CAPT_4 = 0,
1779
                  parameter BREAK_CAPT_5 = 0,
1780
                  parameter BREAK_CAPT_6 = 0,
1781
                  parameter BREAK_CAPT_7 = 0
1782 89 rehayes
      )
1783 82 rehayes
  (
1784
  // Wishbone Signals
1785 89 rehayes
  input               arst_i,     // asynchronous reset
1786 82 rehayes
  input               risc_clk,
1787 89 rehayes
  input  [DWIDTH-1:0] brkpt_cntl  // databus input
1788 82 rehayes
  );
1789
 
1790
  wire [15:0] next_pc = xgate.risc.program_counter;
1791
  wire [15:0] x1 = xgate.risc.xgr1;
1792
  wire [15:0] x2 = xgate.risc.xgr2;
1793
  wire [15:0] x3 = xgate.risc.xgr3;
1794
  wire [15:0] x4 = xgate.risc.xgr4;
1795
  wire [15:0] x5 = xgate.risc.xgr5;
1796
  wire [15:0] x6 = xgate.risc.xgr6;
1797
  wire [15:0] x7 = xgate.risc.xgr7;
1798 89 rehayes
 
1799 82 rehayes
  reg [15:0] cap_x1;
1800
  reg [15:0] cap_x2;
1801
  reg [15:0] cap_x3;
1802
  reg [15:0] cap_x4;
1803
  reg [15:0] cap_x5;
1804
  reg [15:0] cap_x6;
1805
  reg [15:0] cap_x7;
1806 89 rehayes
 
1807 82 rehayes
  reg [15:0] break_addr_0;
1808
  reg [15:0] break_addr_1;
1809
  reg [15:0] break_addr_2;
1810
  reg [15:0] break_addr_3;
1811
  reg [15:0] break_addr_4;
1812
  reg [15:0] break_addr_5;
1813
  reg [15:0] break_addr_6;
1814
  reg [15:0] break_addr_7;
1815 89 rehayes
 
1816 82 rehayes
  reg detect_addr;
1817 89 rehayes
 
1818 82 rehayes
  wire trigger, trigger0, trigger1, trigger3, trigger4, trigger5, trigger6, trigger7;
1819 89 rehayes
 
1820 82 rehayes
  initial
1821
    begin
1822
      break_addr_0 = 0;
1823
      break_addr_1 = 0;
1824
      break_addr_2 = 0;
1825
      break_addr_3 = 0;
1826
      break_addr_4 = 0;
1827
      break_addr_5 = 0;
1828
      break_addr_6 = 0;
1829
      break_addr_7 = 0;
1830 89 rehayes
      repeat(4) @(posedge risc_clk);
1831 82 rehayes
      break_addr_0 = {p_ram.ram_8[BREAK_CAPT_0], p_ram.ram_8[BREAK_CAPT_0+1]};
1832
      break_addr_1 = {p_ram.ram_8[BREAK_CAPT_1], p_ram.ram_8[BREAK_CAPT_1+1]};
1833
      break_addr_2 = {p_ram.ram_8[BREAK_CAPT_2], p_ram.ram_8[BREAK_CAPT_2+1]};
1834
      break_addr_3 = {p_ram.ram_8[BREAK_CAPT_3], p_ram.ram_8[BREAK_CAPT_3+1]};
1835
      break_addr_4 = {p_ram.ram_8[BREAK_CAPT_4], p_ram.ram_8[BREAK_CAPT_4+1]};
1836
      break_addr_5 = {p_ram.ram_8[BREAK_CAPT_5], p_ram.ram_8[BREAK_CAPT_5+1]};
1837
      break_addr_6 = {p_ram.ram_8[BREAK_CAPT_6], p_ram.ram_8[BREAK_CAPT_6+1]};
1838
      break_addr_7 = {p_ram.ram_8[BREAK_CAPT_7], p_ram.ram_8[BREAK_CAPT_7+1]};
1839
    end
1840 89 rehayes
 
1841 82 rehayes
  assign trigger0 = (next_pc === break_addr_0) && brkpt_cntl[ 8];
1842
  assign trigger1 = (next_pc === break_addr_1) && brkpt_cntl[ 9];
1843
  assign trigger2 = (next_pc === break_addr_2) && brkpt_cntl[10];
1844
  assign trigger3 = (next_pc === break_addr_3) && brkpt_cntl[11];
1845
  assign trigger4 = (next_pc === break_addr_4) && brkpt_cntl[12];
1846
  assign trigger5 = (next_pc === break_addr_5) && brkpt_cntl[13];
1847
  assign trigger6 = (next_pc === break_addr_6) && brkpt_cntl[14];
1848
  assign trigger7 = (next_pc === break_addr_7) && brkpt_cntl[15];
1849 89 rehayes
 
1850 82 rehayes
  assign trigger = brkpt_cntl[0] &
1851
                   (trigger0 | trigger1 | trigger2 | trigger3 | trigger4 | trigger5 | trigger6 | trigger7);
1852 89 rehayes
 
1853 82 rehayes
  always @(posedge risc_clk or negedge arst_i)
1854
    begin
1855
      if (!arst_i)
1856 89 rehayes
        begin
1857
          cap_x1 <= 0;
1858
          cap_x2 <= 0;
1859
          cap_x3 <= 0;
1860
          cap_x4 <= 0;
1861
          cap_x5 <= 0;
1862
          cap_x6 <= 0;
1863
          cap_x7 <= 0;
1864
        end
1865 82 rehayes
      else if (trigger)
1866 89 rehayes
        begin
1867
          cap_x1 <= x1;
1868
          cap_x2 <= x2;
1869
          cap_x3 <= x3;
1870
          cap_x4 <= x4;
1871
          cap_x5 <= x5;
1872
          cap_x6 <= x6;
1873
          cap_x7 <= x7;
1874
        end
1875 82 rehayes
    end
1876
 
1877
 
1878
endmodule // tb_debug
1879
 

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