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///////////////////////////////////////////////////////////////////////
////                                                               ////
////  WISHBONE rev.B2 Wishbone Master model                        ////
////                                                               ////
////                                                               ////
////  Author: Richard Herveille                                    ////
////          richard@asics.ws                                     ////
////          www.asics.ws                                         ////
////                                                               ////
////  Downloaded from: http://www.opencores.org/projects/mem_ctrl  ////
////                                                               ////
///////////////////////////////////////////////////////////////////////
////                                                               ////
//// Copyright (C) 2001 Richard Herveille                          ////
////                    richard@asics.ws                           ////
////                                                               ////
//// This source file may be used and distributed without          ////
//// restriction provided that this copyright statement is not     ////
//// removed from the file and that any derivative work contains   ////
//// the original copyright notice and the associated disclaimer.  ////
////                                                               ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY       ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED     ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS     ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR        ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,           ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES      ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE     ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR          ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT    ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT    ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE           ////
//// POSSIBILITY OF SUCH DAMAGE.                                   ////
////                                                               ////
///////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_master_model.v,v 1.4 2004/02/28 15:40:42 rherveille Exp $
//
//  $Date: 2004/02/28 15:40:42 $
//  $Revision: 1.4 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//
`include "timescale.v"
 
module wb_master_model  #(parameter dwidth = 32,
                          parameter awidth = 32)
(
output reg                 cyc,
output reg                 stb,
output reg                 we,
output reg [dwidth/8 -1:0] sel,
output reg [awidth   -1:0] adr,
output reg [dwidth   -1:0] dout,
input      [dwidth   -1:0] din,
input                      clk,
input                      ack,
input                      rst,  // No Connect
input                      err,  // No Connect
input                      rty   // No Connect
);
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg [dwidth   -1:0] q;
 
event test_command_start;
event test_command_mid;
event test_command_end;
 
event cmp_error_detect;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
 
initial
        begin
                adr  = {awidth{1'bx}};
                dout = {dwidth{1'bx}};
                cyc  = 1'b0;
                stb  = 1'bx;
                we   = 1'hx;
                sel  = {dwidth/8{1'bx}};
                #1;
                $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)");
        end
 
 
////////////////////////////////////////////////////////////////////
//
// Wishbone write cycle
//
 
task wb_write;
        input   delay;
        integer delay;
 
        input   [awidth -1:0]   a;
        input   [dwidth -1:0]   d;
 
        begin
                -> test_command_start;
                // wait initial delay
                repeat(delay) @(posedge clk);
 
                // assert wishbone signal
                #1;
                adr  = a;
                dout = d;
                cyc  = 1'b1;
                stb  = 1'b1;
                we   = 1'b1;
                sel  = {dwidth/8{1'b1}};
                @(posedge clk);
                -> test_command_mid;
 
                // wait for acknowledge from slave
                while(~ack)     @(posedge clk);
                -> test_command_mid;
 
                // negate wishbone signals
                #1;
                cyc  = 1'b0;
                stb  = 1'bx;
                adr  = {awidth{1'bx}};
                dout = {dwidth{1'bx}};
                we   = 1'hx;
                sel  = {dwidth/8{1'bx}};
                -> test_command_end;
 
        end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Wishbone read cycle
//
 
task wb_read;
        input   delay;
        integer delay;
 
        input   [awidth -1:0]  a;
        output  [dwidth -1:0]  d;
 
        begin
 
                // wait initial delay
                repeat(delay) @(posedge clk);
 
                // assert wishbone signals
                #1;
                adr  = a;
                dout = {dwidth{1'bx}};
                cyc  = 1'b1;
                stb  = 1'b1;
                we   = 1'b0;
                sel  = {dwidth/8{1'b1}};
                @(posedge clk);
 
                // wait for acknowledge from slave
                while(~ack)     @(posedge clk);
 
                // negate wishbone signals
                d    = din; // Grab the data on the posedge of clock
                #1;         // Delay the clearing (hold time of the control signals
                cyc  = 1'b0;
                stb  = 1'bx;
                adr  = {awidth{1'bx}};
                dout = {dwidth{1'bx}};
                we   = 1'hx;
                sel  = {dwidth/8{1'bx}};
 
        end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Wishbone compare cycle (read data from location and compare with expected data)
//
 
task wb_cmp;
        input   delay;
        integer delay;
 
        input [awidth -1:0]     a;
        input [dwidth -1:0]     d_exp;
 
        begin
                wb_read (delay, a, q);
 
                if (d_exp !== q)
                  begin
                        -> cmp_error_detect;
                        $display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);
                  end
        end
endtask
 
endmodule
 
 

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[/] [xgate/] [trunk/] [bench/] [verilog/] [wb_master_model.v] - Blame information for rev 20

Line No.	Rev	Author	Line
1	2	rehayes	`///////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE rev.B2 Wishbone Master model ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/mem_ctrl ////`
11			`//// ////`
12			`///////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer. ////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`///////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40			`// $Id: wb_master_model.v,v 1.4 2004/02/28 15:40:42 rherveille Exp $`
41			`//`
42			`// $Date: 2004/02/28 15:40:42 $`
43			`// $Revision: 1.4 $`
44			`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`//`
50			`include "timescale.v"
51
52			`module wb_master_model #(parameter dwidth = 32,`
53			`parameter awidth = 32)`
54	20	rehayes	`(`
55			`output reg cyc,`
56			`output reg stb,`
57			`output reg we,`
58			`output reg [dwidth/8 -1:0] sel,`
59			`output reg [awidth -1:0] adr,`
60			`output reg [dwidth -1:0] dout,`
61			`input [dwidth -1:0] din,`
62			`input clk,`
63			`input ack,`
64			`input rst, // No Connect`
65			`input err, // No Connect`
66			`input rty // No Connect`
67			`);`
68	2	rehayes
69			`////////////////////////////////////////////////////////////////////`
70			`//`
71			`// Local Wires`
72			`//`
73
74			`reg [dwidth -1:0] q;`
75
76			`event test_command_start;`
77			`event test_command_mid;`
78			`event test_command_end;`
79
80	20	rehayes	`event cmp_error_detect;`
81
82	2	rehayes	`////////////////////////////////////////////////////////////////////`
83			`//`
84			`// Memory Logic`
85			`//`
86
87			`initial`
88			`begin`
89			`adr = {awidth{1'bx}};`
90			`dout = {dwidth{1'bx}};`
91			`cyc = 1'b0;`
92			`stb = 1'bx;`
93			`we = 1'hx;`
94			`sel = {dwidth/8{1'bx}};`
95			`#1;`
96			`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)");`
97			`end`
98
99	20	rehayes
100	2	rehayes	`////////////////////////////////////////////////////////////////////`
101			`//`
102			`// Wishbone write cycle`
103			`//`
104
105			`task wb_write;`
106			`input delay;`
107			`integer delay;`
108
109			`input [awidth -1:0] a;`
110			`input [dwidth -1:0] d;`
111
112			`begin`
113			`-> test_command_start;`
114			`// wait initial delay`
115			`repeat(delay) @(posedge clk);`
116
117			`// assert wishbone signal`
118			`#1;`
119			`adr = a;`
120			`dout = d;`
121			`cyc = 1'b1;`
122			`stb = 1'b1;`
123			`we = 1'b1;`
124			`sel = {dwidth/8{1'b1}};`
125			`@(posedge clk);`
126			`-> test_command_mid;`
127
128			`// wait for acknowledge from slave`
129			`while(~ack) @(posedge clk);`
130			`-> test_command_mid;`
131
132			`// negate wishbone signals`
133			`#1;`
134			`cyc = 1'b0;`
135			`stb = 1'bx;`
136			`adr = {awidth{1'bx}};`
137			`dout = {dwidth{1'bx}};`
138			`we = 1'hx;`
139			`sel = {dwidth/8{1'bx}};`
140			`-> test_command_end;`
141
142			`end`
143			`endtask`
144
145			`////////////////////////////////////////////////////////////////////`
146			`//`
147			`// Wishbone read cycle`
148			`//`
149
150			`task wb_read;`
151			`input delay;`
152			`integer delay;`
153
154			`input [awidth -1:0] a;`
155			`output [dwidth -1:0] d;`
156
157			`begin`
158
159			`// wait initial delay`
160			`repeat(delay) @(posedge clk);`
161
162			`// assert wishbone signals`
163			`#1;`
164			`adr = a;`
165			`dout = {dwidth{1'bx}};`
166			`cyc = 1'b1;`
167			`stb = 1'b1;`
168			`we = 1'b0;`
169			`sel = {dwidth/8{1'b1}};`
170			`@(posedge clk);`
171
172			`// wait for acknowledge from slave`
173			`while(~ack) @(posedge clk);`
174
175			`// negate wishbone signals`
176			`d = din; // Grab the data on the posedge of clock`
177			`#1; // Delay the clearing (hold time of the control signals`
178			`cyc = 1'b0;`
179			`stb = 1'bx;`
180			`adr = {awidth{1'bx}};`
181			`dout = {dwidth{1'bx}};`
182			`we = 1'hx;`
183			`sel = {dwidth/8{1'bx}};`
184
185			`end`
186			`endtask`
187
188			`////////////////////////////////////////////////////////////////////`
189			`//`
190			`// Wishbone compare cycle (read data from location and compare with expected data)`
191			`//`
192
193			`task wb_cmp;`
194			`input delay;`
195			`integer delay;`
196
197			`input [awidth -1:0] a;`
198			`input [dwidth -1:0] d_exp;`
199
200			`begin`
201			`wb_read (delay, a, q);`
202
203			`if (d_exp !== q)`
204	20	rehayes	`begin`
205			`-> cmp_error_detect;`
206	2	rehayes	`$display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);`
207	20	rehayes	`end`
208	2	rehayes	`end`
209			`endtask`
210
211			`endmodule`
212
213