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///////////////////////////////////////////////////////////////////////
////                                                               ////
////  WISHBONE rev.B2 Wishbone Master model                        ////
////                                                               ////
////                                                               ////
////  Author: Richard Herveille                                    ////
////          richard@asics.ws                                     ////
////          www.asics.ws                                         ////
////                                                               ////
////  Downloaded from: http://www.opencores.org/projects/mem_ctrl  ////
////                                                               ////
///////////////////////////////////////////////////////////////////////
////                                                               ////
//// Copyright (C) 2001 Richard Herveille                          ////
////                    richard@asics.ws                           ////
////                                                               ////
//// This source file may be used and distributed without          ////
//// restriction provided that this copyright statement is not     ////
//// removed from the file and that any derivative work contains   ////
//// the original copyright notice and the associated disclaimer.  ////
////                                                               ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY       ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED     ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS     ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR        ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,           ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES      ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE     ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR          ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT    ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT    ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE           ////
//// POSSIBILITY OF SUCH DAMAGE.                                   ////
////                                                               ////
///////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id$
//
//  $Date$
//  $Revision$
//  $Author$
//  $Locker$
//  $State$
//
// Change History:
//
`include "timescale.v"
 
module wb_master_model  #(parameter dwidth = 32,
                          parameter awidth = 32)
(
output reg                 cyc,
output reg                 stb,
output reg                 we,
output reg [dwidth/8 -1:0] sel,
output reg [awidth   -1:0] adr,
output reg [dwidth   -1:0] dout,
input      [dwidth   -1:0] din,
input                      clk,
input                      ack,
input                      rst,  // No Connect
input                      err,  // No Connect
input                      rty   // No Connect
);
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg [dwidth   -1:0] q;
 
event test_command_start;
event test_command_mid;
event test_command_end;
 
event cmp_error_detect;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
 
initial
        begin
                adr  = {awidth{1'bx}};
                dout = {dwidth{1'bx}};
                cyc  = 1'b0;
                stb  = 1'bx;
                we   = 1'hx;
                sel  = {dwidth/8{1'bx}};
                #1;
                $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)");
        end
 
 
////////////////////////////////////////////////////////////////////
//
// Wishbone write cycle
//
 
task wb_write;
        input   delay;
        integer delay;
 
        input   [awidth   -1:0] a;
        input   [dwidth   -1:0] d;
        input   [dwidth/8 -1:0] s;
 
        begin
                -> test_command_start;
                // wait initial delay
                repeat(delay) @(posedge clk);
 
                // assert wishbone signal
                #1;
                adr  = a;
                dout = d;
                cyc  = 1'b1;
                stb  = 1'b1;
                we   = 1'b1;
                sel  = s;
                @(posedge clk);
                -> test_command_mid;
 
                // wait for acknowledge from slave
                while(~ack)     @(posedge clk);
                -> test_command_mid;
 
                // negate wishbone signals
                #1;
                cyc  = 1'b0;
                stb  = 1'bx;
                adr  = {awidth{1'bx}};
                dout = {dwidth{1'bx}};
                we   = 1'hx;
                sel  = {dwidth/8{1'bx}};
                -> test_command_end;
 
        end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Wishbone read cycle
//
 
task wb_read;
        input   delay;
        integer delay;
 
        input   [awidth   -1:0] a;
        output  [dwidth   -1:0] d;
        input   [dwidth/8 -1:0] s;
 
        begin
 
                // wait initial delay
                repeat(delay) @(posedge clk);
 
                // assert wishbone signals
                #1;
                adr  = a;
                dout = {dwidth{1'bx}};
                cyc  = 1'b1;
                stb  = 1'b1;
                we   = 1'b0;
                sel  = s;
                @(posedge clk);
 
                // wait for acknowledge from slave
                while(~ack)     @(posedge clk);
 
                // negate wishbone signals
                d    = din; // Grab the data on the posedge of clock
                #1;         // Delay the clearing (hold time of the control signals
                cyc  = 1'b0;
                stb  = 1'bx;
                adr  = {awidth{1'bx}};
                dout = {dwidth{1'bx}};
                we   = 1'hx;
                sel  = {dwidth/8{1'bx}};
 
        end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Wishbone compare cycle (read data from location and compare with expected data)
//
 
task wb_cmp;
        input   delay;
        integer delay;
 
        input [awidth   -1:0] a;
        input [dwidth   -1:0] d_exp;
        input [dwidth/8 -1:0] s;
 
        begin
                wb_read (delay, a, q, s);
 
                if (d_exp !== q)
                  begin
                        -> cmp_error_detect;
                        $display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);
                  end
        end
endtask
 
endmodule
 
 

Line No.	Rev	Author	Line
1	2	rehayes	`///////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE rev.B2 Wishbone Master model ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/mem_ctrl ////`
11			`//// ////`
12			`///////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer. ////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`///////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40	27	rehayes	`// $Id$`
41	2	rehayes	`//`
42	27	rehayes	`// $Date$`
43			`// $Revision$`
44			`// $Author$`
45			`// $Locker$`
46			`// $State$`
47	2	rehayes	`//`
48			`// Change History:`
49			`//`
50			`include "timescale.v"
51
52			`module wb_master_model #(parameter dwidth = 32,`
53			`parameter awidth = 32)`
54	20	rehayes	`(`
55			`output reg cyc,`
56			`output reg stb,`
57			`output reg we,`
58			`output reg [dwidth/8 -1:0] sel,`
59			`output reg [awidth -1:0] adr,`
60			`output reg [dwidth -1:0] dout,`
61			`input [dwidth -1:0] din,`
62			`input clk,`
63			`input ack,`
64			`input rst, // No Connect`
65			`input err, // No Connect`
66			`input rty // No Connect`
67			`);`
68	2	rehayes
69			`////////////////////////////////////////////////////////////////////`
70			`//`
71			`// Local Wires`
72			`//`
73
74			`reg [dwidth -1:0] q;`
75
76			`event test_command_start;`
77			`event test_command_mid;`
78			`event test_command_end;`
79
80	20	rehayes	`event cmp_error_detect;`
81
82	2	rehayes	`////////////////////////////////////////////////////////////////////`
83			`//`
84			`// Memory Logic`
85			`//`
86
87			`initial`
88			`begin`
89			`adr = {awidth{1'bx}};`
90			`dout = {dwidth{1'bx}};`
91			`cyc = 1'b0;`
92			`stb = 1'bx;`
93			`we = 1'hx;`
94			`sel = {dwidth/8{1'bx}};`
95			`#1;`
96			`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)");`
97			`end`
98
99	20	rehayes
100	2	rehayes	`////////////////////////////////////////////////////////////////////`
101			`//`
102			`// Wishbone write cycle`
103			`//`
104
105			`task wb_write;`
106			`input delay;`
107			`integer delay;`
108
109	35	rehayes	`input [awidth -1:0] a;`
110			`input [dwidth -1:0] d;`
111			`input [dwidth/8 -1:0] s;`
112	2	rehayes
113			`begin`
114			`-> test_command_start;`
115			`// wait initial delay`
116			`repeat(delay) @(posedge clk);`
117
118			`// assert wishbone signal`
119			`#1;`
120			`adr = a;`
121			`dout = d;`
122			`cyc = 1'b1;`
123			`stb = 1'b1;`
124			`we = 1'b1;`
125	35	rehayes	`sel = s;`
126	2	rehayes	`@(posedge clk);`
127			`-> test_command_mid;`
128
129			`// wait for acknowledge from slave`
130			`while(~ack) @(posedge clk);`
131			`-> test_command_mid;`
132
133			`// negate wishbone signals`
134			`#1;`
135			`cyc = 1'b0;`
136			`stb = 1'bx;`
137			`adr = {awidth{1'bx}};`
138			`dout = {dwidth{1'bx}};`
139			`we = 1'hx;`
140			`sel = {dwidth/8{1'bx}};`
141			`-> test_command_end;`
142
143			`end`
144			`endtask`
145
146			`////////////////////////////////////////////////////////////////////`
147			`//`
148			`// Wishbone read cycle`
149			`//`
150
151			`task wb_read;`
152			`input delay;`
153			`integer delay;`
154
155	35	rehayes	`input [awidth -1:0] a;`
156			`output [dwidth -1:0] d;`
157			`input [dwidth/8 -1:0] s;`
158	2	rehayes
159			`begin`
160
161			`// wait initial delay`
162			`repeat(delay) @(posedge clk);`
163
164			`// assert wishbone signals`
165			`#1;`
166			`adr = a;`
167			`dout = {dwidth{1'bx}};`
168			`cyc = 1'b1;`
169			`stb = 1'b1;`
170			`we = 1'b0;`
171	35	rehayes	`sel = s;`
172	2	rehayes	`@(posedge clk);`
173
174			`// wait for acknowledge from slave`
175			`while(~ack) @(posedge clk);`
176
177			`// negate wishbone signals`
178			`d = din; // Grab the data on the posedge of clock`
179			`#1; // Delay the clearing (hold time of the control signals`
180			`cyc = 1'b0;`
181			`stb = 1'bx;`
182			`adr = {awidth{1'bx}};`
183			`dout = {dwidth{1'bx}};`
184			`we = 1'hx;`
185			`sel = {dwidth/8{1'bx}};`
186
187			`end`
188			`endtask`
189
190			`////////////////////////////////////////////////////////////////////`
191			`//`
192			`// Wishbone compare cycle (read data from location and compare with expected data)`
193			`//`
194
195			`task wb_cmp;`
196			`input delay;`
197			`integer delay;`
198
199	35	rehayes	`input [awidth -1:0] a;`
200			`input [dwidth -1:0] d_exp;`
201			`input [dwidth/8 -1:0] s;`
202	2	rehayes
203			`begin`
204	35	rehayes	`wb_read (delay, a, q, s);`
205	2	rehayes
206			`if (d_exp !== q)`
207	20	rehayes	`begin`
208			`-> cmp_error_detect;`
209	2	rehayes	`$display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);`
210	20	rehayes	`end`
211	2	rehayes	`end`
212			`endtask`
213
214			`endmodule`
215
216

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[/] [xgate/] [trunk/] [bench/] [verilog/] [wb_master_model.v] - Blame information for rev 36