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[/] [xgate/] [trunk/] [bench/] [verilog/] [wb_master_model.v] - Blame information for rev 94

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///////////////////////////////////////////////////////////////////////
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////                                                               ////
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////  WISHBONE rev.B2 Wishbone Master model                        ////
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////                                                               ////
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////                                                               ////
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////  Author: Richard Herveille                                    ////
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////          richard@asics.ws                                     ////
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////          www.asics.ws                                         ////
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////                                                               ////
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////  Downloaded from: http://www.opencores.org/projects/mem_ctrl  ////
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////                                                               ////
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///////////////////////////////////////////////////////////////////////
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////                                                               ////
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//// Copyright (C) 2001 Richard Herveille                          ////
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////                    richard@asics.ws                           ////
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////                                                               ////
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//// This source file may be used and distributed without          ////
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//// restriction provided that this copyright statement is not     ////
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//// removed from the file and that any derivative work contains   ////
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//// the original copyright notice and the associated disclaimer.  ////
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////                                                               ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY       ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED     ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS     ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR        ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,           ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES      ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE     ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR          ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT    ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT    ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE           ////
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//// POSSIBILITY OF SUCH DAMAGE.                                   ////
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////                                                               ////
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///////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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module wb_master_model  #(parameter dwidth = 32,
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                          parameter awidth = 32)
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(
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output reg                 cyc,
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output reg                 stb,
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output reg                 we,
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output reg [dwidth/8 -1:0] sel,
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output reg [awidth   -1:0] adr,
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output reg [dwidth   -1:0] dout,
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input      [dwidth   -1:0] din,
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input                      clk,
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input                      ack,
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input                      rst,  // No Connect
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input                      err,  // No Connect
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input                      rty   // No Connect
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);
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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reg [dwidth-1:0] q;
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event test_command_start;
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event test_command_mid;
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event test_command_end;
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event cmp_error_detect;
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////////////////////////////////////////////////////////////////////
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//
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// Memory Logic
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//
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initial
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  begin
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    adr  = {awidth{1'bx}};
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    dout = {dwidth{1'bx}};
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    cyc  = 1'b0;
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    stb  = 1'bx;
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    we   = 1'hx;
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    sel  = {dwidth/8{1'bx}};
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    #1;
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    $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)");
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  end
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////////////////////////////////////////////////////////////////////
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//
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// Wishbone write cycle
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//
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task wb_write;
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  input   delay;
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  integer delay;
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  input   [awidth   -1:0] a;
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  input   [dwidth   -1:0] d;
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  input   [dwidth/8 -1:0] s;
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  begin
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    -> test_command_start;
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    // wait initial delay
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    repeat(delay) @(posedge clk);
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    // assert wishbone signal
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    #1;
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    adr  = a;
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    dout = d;
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    cyc  = 1'b1;
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    stb  = 1'b1;
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    we   = 1'b1;
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    sel  = s;
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    @(posedge clk);
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    -> test_command_mid;
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    // wait for acknowledge from slave
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    while(~ack)     @(posedge clk);
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    -> test_command_mid;
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    // negate wishbone signals
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    #1;
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    cyc  = 1'b0;
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    stb  = 1'bx;
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    adr  = {awidth{1'bx}};
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    dout = {dwidth{1'bx}};
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    we   = 1'hx;
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    sel  = {dwidth/8{1'bx}};
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    -> test_command_end;
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  end
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endtask
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////////////////////////////////////////////////////////////////////
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//
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// Wishbone read cycle
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//
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task wb_read;
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  input   delay;
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  integer delay;
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  input   [awidth   -1:0] a;
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  output  [dwidth   -1:0] d;
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  input   [dwidth/8 -1:0] s;
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  begin
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    // wait initial delay
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    repeat(delay) @(posedge clk);
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    // assert wishbone signals
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    #1;
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    adr  = a;
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    dout = {dwidth{1'bx}};
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    cyc  = 1'b1;
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    stb  = 1'b1;
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    we   = 1'b0;
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    sel  = s;
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    @(posedge clk);
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    // wait for acknowledge from slave
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    while(~ack)     @(posedge clk);
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    // negate wishbone signals
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    d    = din; // Grab the data on the posedge of clock
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    #1;         // Delay the clearing (hold time of the control signals
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    cyc  = 1'b0;
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    stb  = 1'bx;
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    adr  = {awidth{1'bx}};
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    dout = {dwidth{1'bx}};
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    we   = 1'hx;
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    sel  = {dwidth/8{1'bx}};
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  end
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endtask
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////////////////////////////////////////////////////////////////////
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//
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// Wishbone compare cycle (read data from location and compare with expected data)
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//
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task wb_cmp;
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  input   delay;
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  integer delay;
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  input [awidth   -1:0] a;
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  input [dwidth   -1:0] d_exp;
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  input [dwidth/8 -1:0] s;
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  begin
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    wb_read (delay, a, q, s);
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    if (d_exp !== q)
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      begin
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        -> cmp_error_detect;
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        $display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);
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      end
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  end
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endtask
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endmodule
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