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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_regs.v] - Blame information for rev 24

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1 2 rehayes
////////////////////////////////////////////////////////////////////////////////
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//
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//  Computer Operating Properly - Control registers
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//
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//  Author: Bob Hayes
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//          rehayes@opencores.org
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//
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//  Downloaded from: http://www.opencores.org/projects/xgate.....
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//
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2009, Robert Hayes
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// Supplemental terms.
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//     * Redistributions of source code must retain the above copyright
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//       notice, this list of conditions and the following disclaimer.
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//     * Neither the name of the <organization> nor the
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//       names of its contributors may be used to endorse or promote products
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//       derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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module xgate_regs #(parameter ARST_LVL = 1'b0,    // asynchronous reset level
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                    parameter MAX_CHANNEL = 127)  // Max XGATE Interrupt Channel Number
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  (
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  output reg                  xge,          // XGATE Module Enable
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  output reg                  xgfrz,        // Stop XGATE in Freeze Mode
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  output reg                  xgdbg_set,    // Enter XGATE Debug Mode
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  output reg                  xgdbg_clear,  // Leave XGATE Debug Mode
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  output reg                  xgss,         // XGATE Single Step
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  output reg                  xgfact,       // XGATE Flag Activity
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  output reg                  xgsweif_c,    // Clear XGATE Software Error Interrupt FLag
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  output reg                  xgie,         // XGATE Interrupt Enable
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  output reg           [15:1] xgvbr,        // XGATE vector Base Address Register
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  output reg           [ 7:0] xgswt,        // XGATE Software Trigger Register for host
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  output reg           [15:0] xgisp74,      // XGATE Interrupt level 7-4 stack pointer
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  output reg           [15:0] xgisp30,      // XGATE Interrupt level 3-0 stack pointer
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  output reg                  clear_xgif_7,    // Strobe for decode to clear interrupt flag bank 7
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  output reg                  clear_xgif_6,    // Strobe for decode to clear interrupt flag bank 6
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  output reg                  clear_xgif_5,    // Strobe for decode to clear interrupt flag bank 5
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  output reg                  clear_xgif_4,    // Strobe for decode to clear interrupt flag bank 4
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  output reg                  clear_xgif_3,    // Strobe for decode to clear interrupt flag bank 3
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  output reg                  clear_xgif_2,    // Strobe for decode to clear interrupt flag bank 2
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  output reg                  clear_xgif_1,    // Strobe for decode to clear interrupt flag bank 1
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  output reg                  clear_xgif_0,    // Strobe for decode to clear interrupt flag bank 0
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  output reg           [15:0] clear_xgif_data, // Data for decode to clear interrupt flag
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  output                      semaph_stat,     // Return Status of Semaphore bit
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  output reg                  brk_irq_ena,     // Enable BRK instruction to generate interrupt
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  input                       bus_clk,       // Control register bus clock
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  input                       async_rst_b,   // Async reset signal
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  input                       sync_reset,    // Syncronous reset signal
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  input                [15:0] write_bus,     // Write Data Bus
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  input                       write_xgmctl,  // Write Strobe for XGMCTL register
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  input                       write_xgisp74, // Write Strobe for XGISP74 register
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  input                       write_xgisp30, // Write Strobe for XGISP30 register
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  input                       write_xgvbr,   // Write Strobe for XGVBR register
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  input                       write_xgif_7,  // Write Strobe for Interrupt Flag Register 7
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  input                       write_xgif_6,  // Write Strobe for Interrupt Flag Register 6
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  input                       write_xgif_5,  // Write Strobe for Interrupt Flag Register 5
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  input                       write_xgif_4,  // Write Strobe for Interrupt Flag Register 4
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  input                       write_xgif_3,  // Write Strobe for Interrupt Flag Register 3
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  input                       write_xgif_2,  // Write Strobe for Interrupt Flag Register 2
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  input                       write_xgif_1,  // Write Strobe for Interrupt Flag Register 1
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  input                       write_xgif_0,  // Write Strobe for Interrupt Flag Register 0
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  input                       write_xgswt    // Write Strobe for XGSWT register
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  );
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  // registers
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  // Wires
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  wire write_any_xgif;
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  //
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  // module body
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  //
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  // generate wishbone write registers
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  // XGMCTL Register
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  always @(posedge bus_clk or negedge async_rst_b)
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    if (!async_rst_b)
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      begin
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        xge         <= 1'b0;
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        xgfrz       <= 1'b0;
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        xgdbg_set   <= 1'b0;
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        xgdbg_clear <= 1'b0;
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        xgss        <= 1'b0;
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        xgfact      <= 1'b0;
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        brk_irq_ena <= 1'b0;
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        xgsweif_c   <= 1'b0;
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        xgie        <= 1'b0;
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       end
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    else if (sync_reset)
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      begin
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        xge         <= 1'b0;
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        xgfrz       <= 1'b0;
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        xgdbg_set   <= 1'b0;
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        xgdbg_clear <= 1'b0;
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        xgss        <= 1'b0;
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        xgfact      <= 1'b0;
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        brk_irq_ena <= 1'b0;
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        xgsweif_c   <= 1'b0;
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        xgie        <= 1'b0;
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     end
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    else if (write_xgmctl)
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      begin
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        xge         <= write_bus[15] ? write_bus[7] : xge;
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        xgfrz       <= write_bus[14] ? write_bus[6] : xgfrz;
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        xgdbg_set   <= write_bus[13] && write_bus[5];
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        xgdbg_clear <= write_bus[13] && !write_bus[5];
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        xgss        <= write_bus[12] && write_bus[4];
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        xgfact      <= write_bus[11] ? write_bus[3] : xgfact;
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        brk_irq_ena <= write_bus[10] ? write_bus[2] : brk_irq_ena;
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        xgsweif_c   <= write_bus[ 9] && write_bus[1];
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        xgie        <= write_bus[ 8] ? write_bus[0] : xgie;
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      end
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    else
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      begin
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        xgss        <= 1'b0;
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        xgsweif_c   <= 1'b0;
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        xgdbg_set   <= 1'b0;
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        xgdbg_clear <= 1'b0;
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      end
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  // XGVBR Register
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  always @(posedge bus_clk or negedge async_rst_b)
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    if (!async_rst_b)
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      begin
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        xgvbr  <= 15'b1111_1110_0000_000;
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       end
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    else if (sync_reset)
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      begin
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        xgvbr  <= 15'b1111_1110_0000_000;
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      end
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    else if (write_xgvbr)
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      begin
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        xgvbr[15: 1]  <= xge ? 15'b0 : write_bus[15:1];
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      end
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  // XGISP74 Register
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  always @(posedge bus_clk or negedge async_rst_b)
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    if (!async_rst_b)
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      xgisp74  <= 16'b0;
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    else if (sync_reset)
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      xgisp74  <= 16'b0;
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    else if (write_xgisp74)
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      xgisp74  <= xge ? xgisp74 : write_bus;
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  // XGISP30 Register
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  always @(posedge bus_clk or negedge async_rst_b)
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    if (!async_rst_b)
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      xgisp30  <= 16'b0;
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    else if (sync_reset)
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      xgisp30  <= 16'b0;
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    else if (write_xgisp30)
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      xgisp30  <= xge ? xgisp30 : write_bus;
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  // XGIF 7-0 Registers
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  assign write_any_xgif = write_xgif_7 || write_xgif_6 || write_xgif_5 || write_xgif_4 ||
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                          write_xgif_3 || write_xgif_2 || write_xgif_1 || write_xgif_0;
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  // Registers to clear the interrupt flags. Decode a specific interrupt to
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  //  clear by ANDing the clear_xgif_x signal with the clear_xgif_data.
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  always @(posedge bus_clk or negedge async_rst_b)
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    if (!async_rst_b)
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      begin
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        clear_xgif_7    <= 1'b0;
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        clear_xgif_6    <= 1'b0;
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        clear_xgif_5    <= 1'b0;
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        clear_xgif_4    <= 1'b0;
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        clear_xgif_3    <= 1'b0;
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        clear_xgif_2    <= 1'b0;
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        clear_xgif_1    <= 1'b0;
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        clear_xgif_0    <= 1'b0;
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        clear_xgif_data <= 16'b0;
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      end
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    else if (sync_reset)
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      begin
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        clear_xgif_7    <= 1'b0;
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        clear_xgif_6    <= 1'b0;
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        clear_xgif_5    <= 1'b0;
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        clear_xgif_4    <= 1'b0;
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        clear_xgif_3    <= 1'b0;
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        clear_xgif_2    <= 1'b0;
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        clear_xgif_1    <= 1'b0;
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        clear_xgif_0    <= 1'b0;
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        clear_xgif_data <= 16'b0;
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      end
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    else
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      begin
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        clear_xgif_7    <= write_xgif_7 && (MAX_CHANNEL > 111);
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        clear_xgif_6    <= write_xgif_6 && (MAX_CHANNEL > 95);
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        clear_xgif_5    <= write_xgif_5 && (MAX_CHANNEL > 79);
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        clear_xgif_4    <= write_xgif_4 && (MAX_CHANNEL > 63);
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        clear_xgif_3    <= write_xgif_3 && (MAX_CHANNEL > 47);
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        clear_xgif_2    <= write_xgif_2 && (MAX_CHANNEL > 31);
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        clear_xgif_1    <= write_xgif_1 && (MAX_CHANNEL > 15);
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        clear_xgif_0    <= write_xgif_0;
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        clear_xgif_data <= write_any_xgif ? write_bus : clear_xgif_data;
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      end
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  // XGSWT - XGATE Software Trigger Register
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  always @(posedge bus_clk or negedge async_rst_b)
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    if (!async_rst_b)
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      xgswt <= 8'h00;
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    else if (sync_reset)
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      xgswt <= 8'h00;
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    else if (write_xgswt)
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      begin
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        xgswt[7] <= write_bus[15] ? write_bus[7] : xgswt[7];
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        xgswt[6] <= write_bus[14] ? write_bus[6] : xgswt[6];
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        xgswt[5] <= write_bus[13] ? write_bus[5] : xgswt[5];
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        xgswt[4] <= write_bus[11] ? write_bus[4] : xgswt[4];
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        xgswt[3] <= write_bus[12] ? write_bus[3] : xgswt[3];
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        xgswt[2] <= write_bus[10] ? write_bus[2] : xgswt[2];
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        xgswt[1] <= write_bus[ 9] ? write_bus[1] : xgswt[1];
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        xgswt[0] <= write_bus[ 8] ? write_bus[0] : xgswt[0];
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      end
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endmodule  // xgate_regs
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