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1 2 rehayes 
////////////////////////////////////////////////////////////////////////////////
2 
//
3 
//  XGATE Coprocessor - XGATE RISC Processor Core
4 
//
5 
//  Author: Bob Hayes
6 
//          rehayes@opencores.org
7 
//
8 
//  Downloaded from: http://www.opencores.org/projects/xgate.....
9 
//
10 
////////////////////////////////////////////////////////////////////////////////
11 
// Copyright (c) 2009, Robert Hayes
12 
//
13 
// This source file is free software: you can redistribute it and/or modify
14 
// it under the terms of the GNU Lesser General Public License as published
15 
// by the Free Software Foundation, either version 3 of the License, or
16 
// (at your option) any later version.
17 
//
18 
// Supplemental terms.
19 
//     * Redistributions of source code must retain the above copyright
20 
//       notice, this list of conditions and the following disclaimer.
21 
//     * Neither the name of the <organization> nor the
22 
//       names of its contributors may be used to endorse or promote products
23 
//       derived from this software without specific prior written permission.
24 
//
25 
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
26 
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28 
// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
29 
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
31 
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32 
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 
//
36 
// You should have received a copy of the GNU General Public License
37 
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
38 
////////////////////////////////////////////////////////////////////////////////
39 
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
40 
 
41 
module xgate_risc #(parameter MAX_CHANNEL = 127)    // Max XGATE Interrupt Channel Number
42 
 (
43 
  output reg [15:0] xgr1,
44 
  output reg [15:0] xgr2,
45 
  output reg [15:0] xgr3,
46 
  output reg [15:0] xgr4,
47 
  output reg [15:0] xgr5,
48 
  output reg [15:0] xgr6,
49 
  output reg [15:0] xgr7,
50 
  output     [15:0] xgate_address,
51 
  output     [15:0] write_mem_data,   // Data for Memory write
52 34 rehayes 
  output            mem_access,       //
53 2 rehayes 
  output            write_mem_strb_l, // Strobe for writing low data byte
54 
  output            write_mem_strb_h, // Strobe for writing high data bye
55 
  output reg                 zero_flag,
56 
  output reg                 negative_flag,
57 
  output reg                 carry_flag,
58 
  output reg                 overflow_flag,
59 
  output reg          [ 6:0] xgchid,
60 72 rehayes 
  output reg         [127:1] xgif_status,   // XGATE Interrupt Flag
61 12 rehayes 
  output                     xg_sw_irq,     // Xgate Software interrupt
62 2 rehayes 
  output              [ 7:0] host_semap,    // Semaphore status for host
63 12 rehayes 
  output reg                 debug_active,  // Latch to control debug mode in the RISC state machine
64 53 rehayes 
  output                     debug_ack,     // Clear debug register
65 
  output                     single_step,   // Pulse to trigger a single instruction execution in debug mode
66 2 rehayes 
 
67 
 
68 
  input      [15:0] read_mem_data,
69 
  input      [15:0] perif_data,
70 
  input             risc_clk,
71 
  input             async_rst_b,
72 5 rehayes 
  input             mem_req_ack,    // Memory Bus available - data good
73 53 rehayes 
  input             ss_mem_ack,     // WISHBONE Bus has granted single step memory access
74 2 rehayes 
  input             xge,            // XGATE Module Enable
75 31 rehayes 
  input             debug_mode_i,   // Force RISC core into debug mode
76 53 rehayes 
  input             xgdbg_set,      // Enter XGATE Debug Mode, pulse
77 15 rehayes 
  input             xgdbg_clear,    // Leave XGATE Debug Mode
78 2 rehayes 
  input             xgss,           // XGATE Single Step
79 
  input      [15:1] xgvbr,          // XGATE vector Base Address Register
80 
  input      [ 6:0] int_req,        // Encoded interrupt request
81 12 rehayes 
  input             xgie,           // XGATE Interrupt Enable
82 
  input             brk_irq_ena,    // Enable BRK instruction to generate interrupt
83 17 rehayes 
  input             write_xgchid,   // Write Strobe for XGCHID register
84 2 rehayes 
  input             write_xgsem,    // Write Strobe for XGSEM register
85 
  input             write_xgccr,    // Write Strobe for XGATE Condition Code Register
86 41 rehayes 
  input      [ 1:0] write_xgpc,     // Write Strobe for XGATE Program Counter
87 
  input      [ 1:0] write_xgr7,     // Write Strobe for XGATE Data Register R7
88 
  input      [ 1:0] write_xgr6,     // Write Strobe for XGATE Data Register R6
89 
  input      [ 1:0] write_xgr5,     // Write Strobe for XGATE Data Register R5
90 
  input      [ 1:0] write_xgr4,     // Write Strobe for XGATE Data Register R4
91 
  input      [ 1:0] write_xgr3,     // Write Strobe for XGATE Data Register R3
92 
  input      [ 1:0] write_xgr2,     // Write Strobe for XGATE Data Register R2
93 
  input      [ 1:0] write_xgr1,     // Write Strobe for XGATE Data Register R1
94 12 rehayes 
  input             xgsweif_c,      // Clear Software Flag
95 2 rehayes 
  input             clear_xgif_7,   // Strobe for decode to clear interrupt flag bank 7
96 
  input             clear_xgif_6,   // Strobe for decode to clear interrupt flag bank 6
97 
  input             clear_xgif_5,   // Strobe for decode to clear interrupt flag bank 5
98 
  input             clear_xgif_4,   // Strobe for decode to clear interrupt flag bank 4
99 
  input             clear_xgif_3,   // Strobe for decode to clear interrupt flag bank 3
100 
  input             clear_xgif_2,   // Strobe for decode to clear interrupt flag bank 2
101 
  input             clear_xgif_1,   // Strobe for decode to clear interrupt flag bank 1
102 
  input             clear_xgif_0,   // Strobe for decode to clear interrupt flag bank 0
103 
  input      [15:0] clear_xgif_data // Data for decode to clear interrupt flag
104 
);
105 
 
106 26 rehayes 
  integer j;     // Loop counters for decode of XGATE Interrupt Register
107 2 rehayes 
  integer k;     // Loop counter for Bit Field Insert decode
108 26 rehayes 
  integer bfi, bfii;   // Loop counter for Bit Field Insert function
109 2 rehayes 
 
110 
  // State machine sequence
111 5 rehayes 
  parameter [3:0]      //synopsys enum state_info
112 
       IDLE    = 4'b0000,      // waiting for interrupt
113 
       CONT    = 4'b0001,      // Instruction processing state, first state
114 12 rehayes 
       S_STALL = 4'b0010,      // Simple Stall while updating PC after change of flow
115 40 rehayes 
       W_STORE = 4'b1101,      // Stall while doing memory word write access
116 
       W_LOAD  = 4'b0011,      // Stall while doing memory word read access
117 
       B_LOAD  = 4'b0100,      // Stall while doing memory byte read access
118 12 rehayes 
       BREAK   = 4'b0101,      // Stop in this state after BRK instruction
119 
       BREAK_2 = 4'b0110,      // Advance PC after Single Step command
120 
       LD_INST = 4'b0111,      // Load Instruction in Debug mode
121 
       DEBUG   = 4'b1000,      // Stop in this state while waiting for debug commands
122 
       BOOT_1  = 4'b1001,      //
123 
       BOOT_2  = 4'b1010,      //
124 17 rehayes 
       BOOT_3  = 4'b1011,      //
125 
       CHG_CHID = 4'b1100;
126 12 rehayes 
 
127 
 
128 2 rehayes 
  // Semaphore states
129 
  parameter [1:0] NO_LOCK = 2'b00,
130 12 rehayes 
                  RISC_LOCK = 2'b10,
131 
                  HOST_LOCK = 2'b11;
132 
 
133 
 
134 
  reg  [ 3:0] cpu_state;         // State register for instruction processing
135 5 rehayes 
  reg  [ 3:0] next_cpu_state;    // Pseudo Register,
136 64 rehayes 
  wire        stm_auto_advance;  // State Machine increment without wait state holdoff
137 2 rehayes 
  reg         load_next_inst;    // Pseudo Register,
138 12 rehayes 
  reg  [15:0] program_counter;   // Program Counter register
139 40 rehayes 
  wire [15:0] pc_sum;            // Program Counter Adder
140 
  reg  [15:0] pc_incr_mux;       // Pseudo Register, mux to select the Program Counter Increment value
141 
  reg  [15:0] next_pc;           // Pseudo Register
142 
  wire [15:0] jump_offset;       // Address offset to be added to pc on conditional branch instruction
143 
  wire [15:0] bra_offset;        // Address offset to be added to pc on branch always instruction
144 2 rehayes 
  reg  [15:0] alu_result;        // Pseudo Register,
145 12 rehayes 
  reg  [15:0] op_code;           // Register for instruction being executed
146 2 rehayes 
  reg         ena_rd_low_byte;   // Pseudo Register,
147 
  reg         ena_rd_high_byte;  // Pseudo Register,
148 
 
149 12 rehayes 
  reg         data_access;    // Pseudo Register, RAM access in proccess
150 
  reg         data_write;     // Pseudo Register, RAM access is write operation
151 
  reg         data_word_op;   // Pseudo Register, RAM access operation is 16 bits(word)
152 
  reg  [15:0] data_address;   // Pseudo Register, Address for RAM data read or write
153 
  reg  [15:0] load_data;      // Data captured from WISHBONE Master bus for Load instructions
154 
 
155 
  reg  [ 6:0] set_irq_flag;   // Pseudo Register, pulse for setting irq output register
156 
 
157 2 rehayes 
  reg         next_zero;      // Pseudo Register,
158 
  reg         next_negative;  // Pseudo Register,
159 
  reg         next_carry;     // Pseudo Register,
160 
  reg         next_overflow;  // Pseudo Register,
161 17 rehayes 
 
162 12 rehayes 
  reg         op_code_error;  // Pseudo Register,
163 
  reg         software_error; // OP Code error, Address Error, BRK Error
164 
  wire        addr_error;     // Decode Addressing error
165 2 rehayes 
 
166 
  reg         set_semaph;     // Pseudo Register,
167 
  reg         clear_semaph;   // Pseudo Register,
168 
  reg  [ 2:0] semaph_risc;    // Pseudo Register,
169 
  reg  [ 7:0] semap_risc_bit; // Pseudo Register,
170 
  wire [ 7:0] risc_semap;     // Semaphore status bit for RISC
171 
  wire        semaph_stat;    // Return Status of Semaphore bit
172 12 rehayes 
 
173 2 rehayes 
  reg  [15:0] rd_data;        // Pseudo Register,
174 
  reg  [15:0] rs1_data;       // Pseudo Register,
175 
  reg  [15:0] rs2_data;       // Pseudo Register,
176 12 rehayes 
 
177 2 rehayes 
  wire [ 2:0] wrt_reg_sel;
178 12 rehayes 
  reg         sel_rd_field;   // Pseudo Register,
179 
  reg         wrt_sel_xgr1;   // Pseudo Register,
180 
  reg         wrt_sel_xgr2;   // Pseudo Register,
181 
  reg         wrt_sel_xgr3;   // Pseudo Register,
182 
  reg         wrt_sel_xgr4;   // Pseudo Register,
183 
  reg         wrt_sel_xgr5;   // Pseudo Register,
184 
  reg         wrt_sel_xgr6;   // Pseudo Register,
185 
  reg         wrt_sel_xgr7;   // Pseudo Register,
186 
 
187 72 rehayes 
  reg [127:1] xgif_d;
188 12 rehayes 
 
189 2 rehayes 
  reg  [15:0] shift_in;
190 
  wire [15:0] shift_out;
191 
  wire        shift_rollover;
192 
  reg         shift_left;
193 
  reg  [ 4:0] shift_ammount;
194 
  reg  [15:0] shift_filler;
195 53 rehayes 
  reg  [15:0] bf_mux_mask;   // Mask for controlling mux's in Bit Field Insert Instructions
196 12 rehayes 
 
197 59 rehayes 
  wire        start_thread;  // Signal to pop RISC core out of IDLE State
198 2 rehayes 
 
199 12 rehayes 
  wire        cpu_is_idle;   // Processor is in the IDLE state
200 
  wire        perif_wrt_ena; // Enable for Salve writes to CPU registers
201 
 
202 
  reg         xgss_edge;     // Flop for edge detection
203 
  reg         brk_set_dbg;   // Pulse to set debug_active from instruction decoder
204 15 rehayes 
  reg         cmd_change_pc; // Debug write to PC register
205 53 rehayes 
  reg         debug_edge;    // Reg for edge detection
206 12 rehayes 
 
207 64 rehayes 
  reg         cmd_dbg;
208 
 
209 31 rehayes 
  reg  [ 1:0] chid_sm_ns;    // Pseudo Register for State Machine next state logic,
210 17 rehayes 
  reg  [ 1:0] chid_sm;       //
211 
  wire        chid_goto_idle; //
212 12 rehayes 
 
213 17 rehayes 
  // Debug states for change CHID
214 
  parameter [1:0] CHID_IDLE = 2'b00,
215 
                  CHID_TEST = 2'b10,
216 
                  CHID_WAIT = 2'b11;
217 
 
218 64 rehayes 
 
219 40 rehayes 
  assign jump_offset = {{6{op_code[8]}}, op_code[8:0], 1'b0};
220 
  assign bra_offset  = {{5{op_code[9]}}, op_code[9:0], 1'b0};
221 
  assign pc_sum      = program_counter + pc_incr_mux;
222 17 rehayes 
 
223 2 rehayes 
  assign xgate_address = data_access ? data_address : program_counter;
224 34 rehayes 
 
225 59 rehayes 
  //assign mem_access = data_access || load_next_inst || start_thread;
226 53 rehayes 
  assign mem_access = data_access || load_next_inst || (cpu_state == CONT) ||
227 59 rehayes 
                     (cpu_state == BREAK_2)  || start_thread;
228 17 rehayes 
 
229 12 rehayes 
  // Generate an address for an op code fetch from an odd address or a word Load/Store from/to an odd address.
230 
  assign addr_error = xgate_address[0] && (load_next_inst || (data_access && data_word_op));
231 
 
232 2 rehayes 
  assign write_mem_strb_l = data_access && data_write && (data_word_op || !data_address[0]);
233 
  assign write_mem_strb_h = data_access && data_write && (data_word_op ||  data_address[0]);
234 
  assign write_mem_data   = (write_mem_strb_l || write_mem_strb_h) ? rd_data : 16'b0;
235 12 rehayes 
 
236 17 rehayes 
  assign start_thread = xge && (|int_req) && !debug_active;
237 12 rehayes 
 
238 
  assign cpu_is_idle = (cpu_state == IDLE);
239 15 rehayes 
  assign perif_wrt_ena = (cpu_is_idle && ~xge) || debug_active;
240 12 rehayes 
 
241 2 rehayes 
  // Decode register select for RD and RS
242 
  always @*
243 
    begin
244 26 rehayes 
      case (op_code[10:8]) // synopsys parallel_case
245 2 rehayes 
        3'b001 : rd_data = xgr1;
246 
        3'b010 : rd_data = xgr2;
247 
        3'b011 : rd_data = xgr3;
248 
        3'b100 : rd_data = xgr4;
249 
        3'b101 : rd_data = xgr5;
250 
        3'b110 : rd_data = xgr6;
251 
        3'b111 : rd_data = xgr7;
252 
        default : rd_data = 16'h0;  // XGR0 is always Zero
253 
      endcase
254 
    end
255 
 
256 47 rehayes 
  assign wrt_reg_sel = (cpu_state == BOOT_3) ? 3'b001 :
257 
                       (sel_rd_field ? op_code[10:8] : op_code[4:2]);
258 2 rehayes 
 
259 
  // Decode register write select for eather RD or RI/RS2
260 
  always @*
261 
    begin
262 47 rehayes 
      wrt_sel_xgr1 = (wrt_reg_sel == 3'b001) && mem_req_ack;
263 
      wrt_sel_xgr2 = (wrt_reg_sel == 3'b010) && mem_req_ack;
264 
      wrt_sel_xgr3 = (wrt_reg_sel == 3'b011) && mem_req_ack;
265 
      wrt_sel_xgr4 = (wrt_reg_sel == 3'b100) && mem_req_ack;
266 
      wrt_sel_xgr5 = (wrt_reg_sel == 3'b101) && mem_req_ack;
267 
      wrt_sel_xgr6 = (wrt_reg_sel == 3'b110) && mem_req_ack;
268 
      wrt_sel_xgr7 = (wrt_reg_sel == 3'b111) && mem_req_ack;
269 2 rehayes 
    end
270 
 
271 
  // Decode register select for RS1 and RB
272 
  always @*
273 26 rehayes 
    case (op_code[7:5])  // synopsys parallel_case
274 2 rehayes 
      3'b001 : rs1_data = xgr1;
275 
      3'b010 : rs1_data = xgr2;
276 
      3'b011 : rs1_data = xgr3;
277 
      3'b100 : rs1_data = xgr4;
278 
      3'b101 : rs1_data = xgr5;
279 
      3'b110 : rs1_data = xgr6;
280 
      3'b111 : rs1_data = xgr7;
281 
      default : rs1_data = 16'h0;  // XGR0 is always Zero
282 
    endcase
283 
 
284 
  // Decode register select for RS2 and RI
285 
  always @*
286 26 rehayes 
    case (op_code[4:2])  // synopsys parallel_case
287 2 rehayes 
      3'b001 : rs2_data = xgr1;
288 
      3'b010 : rs2_data = xgr2;
289 
      3'b011 : rs2_data = xgr3;
290 
      3'b100 : rs2_data = xgr4;
291 
      3'b101 : rs2_data = xgr5;
292 
      3'b110 : rs2_data = xgr6;
293 
      3'b111 : rs2_data = xgr7;
294 
      default : rs2_data = 16'h0;  // XGR0 is always Zero
295 
    endcase
296 
 
297 
  // Decode mux select mask for Bit Field Insert Instructions
298 
  always @*
299 
    begin
300 
      k = 0;
301 
      while (k < 16)
302 
        begin
303 
          bf_mux_mask[k] = 1'b0;
304 
          if ((k >= rs2_data[3:0]) && (k <= rs2_data[3:0] + rs2_data[7:4]))
305 
            bf_mux_mask[k] = 1'b1;
306 
          k = k + 1;
307 
        end
308 
    end
309 
 
310 12 rehayes 
  //  Software Error Interrupt Latch
311 
  always @(posedge risc_clk or negedge async_rst_b)
312 
    if ( !async_rst_b )
313 
      software_error <= 1'b0;
314 
    else
315 17 rehayes 
      software_error <= addr_error || op_code_error ||
316 12 rehayes 
                        (brk_set_dbg && brk_irq_ena) || (software_error && !xgsweif_c);
317 17 rehayes 
 
318 12 rehayes 
  assign xg_sw_irq = software_error && xgie;
319 
 
320 64 rehayes 
  //  Latch the need to go to debug state set by xgdb
321 
  always @(posedge risc_clk or negedge async_rst_b)
322 
    if ( !async_rst_b )
323 
      begin
324 
        cmd_dbg  <= 1'b0;
325 
      end
326 
    else
327 
      begin
328 
        cmd_dbg  <= !((cpu_state == LD_INST) || (cpu_state == DEBUG)) &&
329 
                     (cmd_dbg || (xgdbg_set && mem_req_ack && (next_cpu_state == CONT)));
330 
      end
331 
 
332 12 rehayes 
  //  Latch the debug state, set by eather xgdb or BRK instructions
333 
  always @(posedge risc_clk or negedge async_rst_b)
334 
    if ( !async_rst_b )
335 53 rehayes 
      begin
336 64 rehayes 
        debug_active  <= 1'b0;
337 
        debug_edge    <= 0;
338 53 rehayes 
      end
339 12 rehayes 
    else
340 53 rehayes 
      begin
341 64 rehayes 
        debug_active  <= !xgdbg_clear && (cmd_dbg ||
342 
                         brk_set_dbg || op_code_error || debug_active);
343 
        debug_edge    <= debug_active;
344 53 rehayes 
      end
345 
 
346 
  assign debug_ack = debug_active && !debug_edge; // Posedge of debug_active
347 12 rehayes 
 
348 
  //  Convert xgss (Single Step Pulse) to a one risc_clk wide pulse
349 
  always @(posedge risc_clk or negedge async_rst_b)
350 
    if ( !async_rst_b )
351 
      xgss_edge  <= 1'b0;
352 
    else
353 
      xgss_edge  <= xgss;
354 
 
355 53 rehayes 
  assign single_step = (xgss && !xgss_edge) || (!debug_active && debug_edge);
356 12 rehayes 
 
357 59 rehayes 
  assign stm_auto_advance = (chid_sm != CHID_IDLE);
358 12 rehayes 
 
359 2 rehayes 
  //  CPU State Register
360 
  always @(posedge risc_clk or negedge async_rst_b)
361 
    if ( !async_rst_b )
362 
      cpu_state  <= IDLE;
363 
    else
364 59 rehayes 
      cpu_state  <= (mem_req_ack || stm_auto_advance) ? next_cpu_state : cpu_state;
365 2 rehayes 
 
366 
  //  CPU Instruction Register
367 
  always @(posedge risc_clk or negedge async_rst_b)
368 
    if ( !async_rst_b )
369 
      op_code  <= 16'h0000;
370 
    else
371 5 rehayes 
      op_code  <= (load_next_inst && mem_req_ack) ? read_mem_data : op_code;
372 12 rehayes 
 
373 2 rehayes 
  //  Active Channel Latch
374 
  always @(posedge risc_clk or negedge async_rst_b)
375 
    if ( !async_rst_b )
376 
      xgchid  <= 7'b0;
377 
    else
378 59 rehayes 
      xgchid  <= (write_xgchid && debug_active) ? perif_data[6:0] : (cpu_is_idle ? int_req : xgchid);
379 2 rehayes 
 
380 17 rehayes 
  //  Channel Change Debug state machine register
381 
  always @(posedge risc_clk or negedge async_rst_b)
382 
    if ( !async_rst_b )
383 
      chid_sm  <= CHID_IDLE;
384 
    else
385 
      chid_sm  <= chid_sm_ns;
386 
 
387 
  //  Channel Change Debug next state
388 
  always @*
389 26 rehayes 
    case (chid_sm)  // synopsys parallel_case
390 17 rehayes 
      CHID_IDLE:
391 
        if ( write_xgchid && debug_active )
392 
          chid_sm_ns  = CHID_TEST;
393 75 rehayes 
        else
394 
          chid_sm_ns  = CHID_IDLE;
395 17 rehayes 
      CHID_TEST:
396 
        if ( !((cpu_state == IDLE) || (cpu_state == CHG_CHID)) && (|xgchid) )
397 
          chid_sm_ns  = CHID_IDLE;
398 
        else
399 
          chid_sm_ns  = CHID_WAIT;
400 
      CHID_WAIT:
401 
        if ( (cpu_state == IDLE) || (cpu_state == CHG_CHID) )
402 
          chid_sm_ns  = CHID_IDLE;
403 
        else
404 
          chid_sm_ns  = CHID_WAIT;
405 
      default : chid_sm_ns  = CHID_IDLE;
406 
    endcase
407 
 
408 
  assign chid_goto_idle = (chid_sm == CHID_WAIT);
409 
 
410 2 rehayes 
  //  CPU Read Data Buffer Register
411 
  always @(posedge risc_clk or negedge async_rst_b)
412 
    if ( !async_rst_b )
413 
      load_data  <= 16'h0000;
414 
    else
415 5 rehayes 
      load_data  <= (data_access && !data_write && mem_req_ack) ? read_mem_data : load_data;
416 2 rehayes 
 
417 
  //  Program Counter Register
418 
  always @(posedge risc_clk or negedge async_rst_b)
419 
    if ( !async_rst_b )
420 
      program_counter  <= 16'h0000;
421 
    else
422 41 rehayes 
      program_counter  <= (|write_xgpc && perif_wrt_ena) ?
423 
      {(write_xgpc[1] ? perif_data[15:8]: program_counter[15:8]),
424 
       (write_xgpc[0] ? perif_data[ 7:0]: program_counter[ 7:0])} :
425 
      (mem_req_ack ? next_pc : program_counter);
426 2 rehayes 
 
427 15 rehayes 
  //  Debug Change Program Counter Register
428 
  always @(posedge risc_clk or negedge async_rst_b)
429 
    if ( !async_rst_b )
430 
      cmd_change_pc  <= 1'b0;
431 
    else
432 53 rehayes 
      cmd_change_pc  <= (|write_xgpc && perif_wrt_ena) || (cmd_change_pc && !mem_req_ack);
433 15 rehayes 
 
434 2 rehayes 
  //  ALU Flag Bits
435 
  always @(posedge risc_clk or negedge async_rst_b)
436 
    if ( !async_rst_b )
437 
      begin
438 
        carry_flag    <= 1'b0;
439 
        overflow_flag <= 1'b0;
440 
        zero_flag     <= 1'b0;
441 
        negative_flag <= 1'b0;
442 
      end
443 
    else
444 
      begin
445 12 rehayes 
        carry_flag    <= (write_xgccr && perif_wrt_ena) ? perif_data[0] : (mem_req_ack ? next_carry : carry_flag);
446 
        overflow_flag <= (write_xgccr && perif_wrt_ena) ? perif_data[1] : (mem_req_ack ? next_overflow : overflow_flag);
447 
        zero_flag     <= (write_xgccr && perif_wrt_ena) ? perif_data[2] : (mem_req_ack ? next_zero : zero_flag);
448 
        negative_flag <= (write_xgccr && perif_wrt_ena) ? perif_data[3] : (mem_req_ack ? next_negative : negative_flag);
449 2 rehayes 
      end
450 
 
451 
  //  Interrupt Flag next value
452 
  always @*
453 12 rehayes 
    begin
454 31 rehayes 
      xgif_d = 0;
455 72 rehayes 
      j = 1;
456 
      while (j <= MAX_CHANNEL)  // while loop sets irq bit and maintains previously set bits
457 12 rehayes 
        begin
458 31 rehayes 
         xgif_d[j]  = xgif_status[j] || (set_irq_flag == j);
459 12 rehayes 
         j = j + 1;
460 
        end
461 67 rehayes 
      if (clear_xgif_0)
462 72 rehayes 
        xgif_d[15: 1]  = ~clear_xgif_data & xgif_status[15: 1];
463 67 rehayes 
      if (clear_xgif_1)
464 
        xgif_d[31:16]  = ~clear_xgif_data & xgif_status[31:16];
465 
      if (clear_xgif_2)
466 
        xgif_d[47:32]  = ~clear_xgif_data & xgif_status[47:32];
467 
      if (clear_xgif_3)
468 
        xgif_d[63:48]  = ~clear_xgif_data & xgif_status[63:48];
469 
      if (clear_xgif_4)
470 
        xgif_d[79:64]  = ~clear_xgif_data & xgif_status[79:64];
471 
      if (clear_xgif_5)
472 
        xgif_d[95:80]  = ~clear_xgif_data & xgif_status[95:80];
473 
      if (clear_xgif_6)
474 
        xgif_d[111:96]  = ~clear_xgif_data & xgif_status[111:96];
475 
      if (clear_xgif_7)
476 
        xgif_d[127:112] = ~clear_xgif_data & xgif_status[127:112];
477 12 rehayes 
    end
478 2 rehayes 
 
479 
  //  Interrupt Flag Registers
480 
  always @(posedge risc_clk or negedge async_rst_b)
481 
    if ( !async_rst_b )
482 31 rehayes 
      xgif_status  <= 0;
483 2 rehayes 
    else
484 31 rehayes 
      xgif_status  <= xgif_d;
485 2 rehayes 
 
486 
 
487 
  //  RISC Data Registers
488 
  always @(posedge risc_clk or negedge async_rst_b)
489 
    if ( !async_rst_b )
490 
      begin
491 
        xgr1 <= 16'b0;
492 
        xgr2 <= 16'b0;
493 
        xgr3 <= 16'b0;
494 
        xgr4 <= 16'b0;
495 
        xgr5 <= 16'b0;
496 
        xgr6 <= 16'b0;
497 
        xgr7 <= 16'b0;
498 
      end
499 
    else
500 
      begin
501 41 rehayes 
        xgr1 <= (|write_xgr1 && perif_wrt_ena) ?
502 
                {(write_xgr1[1] ? perif_data[15:8]: xgr1[15:8]),
503 
                 (write_xgr1[0] ? perif_data[ 7:0]: xgr1[ 7:0])} :
504 2 rehayes 
                {((wrt_sel_xgr1 && ena_rd_high_byte) ? alu_result[15:8] : xgr1[15:8]),
505 
                 ((wrt_sel_xgr1 && ena_rd_low_byte)  ? alu_result[ 7:0] : xgr1[ 7:0])};
506 41 rehayes 
        xgr2 <= (|write_xgr2 && perif_wrt_ena) ?
507 
                {(write_xgr2[1] ? perif_data[15:8]: xgr2[15:8]),
508 
                 (write_xgr2[0] ? perif_data[ 7:0]: xgr2[ 7:0])} :
509 2 rehayes 
                {((wrt_sel_xgr2 && ena_rd_high_byte) ? alu_result[15:8] : xgr2[15:8]),
510 
                 ((wrt_sel_xgr2 && ena_rd_low_byte)  ? alu_result[ 7:0] : xgr2[ 7:0])};
511 41 rehayes 
        xgr3 <= (|write_xgr3 && perif_wrt_ena) ?
512 
                {(write_xgr3[1] ? perif_data[15:8]: xgr3[15:8]),
513 
                 (write_xgr3[0] ? perif_data[ 7:0]: xgr3[ 7:0])} :
514 2 rehayes 
                {((wrt_sel_xgr3 && ena_rd_high_byte) ? alu_result[15:8] : xgr3[15:8]),
515 
                 ((wrt_sel_xgr3 && ena_rd_low_byte)  ? alu_result[ 7:0] : xgr3[ 7:0])};
516 41 rehayes 
        xgr4 <= (|write_xgr4 && perif_wrt_ena) ?
517 
                {(write_xgr4[1] ? perif_data[15:8]: xgr4[15:8]),
518 
                 (write_xgr4[0] ? perif_data[ 7:0]: xgr4[ 7:0])} :
519 2 rehayes 
                {((wrt_sel_xgr4 && ena_rd_high_byte) ? alu_result[15:8] : xgr4[15:8]),
520 
                 ((wrt_sel_xgr4 && ena_rd_low_byte)  ? alu_result[ 7:0] : xgr4[ 7:0])};
521 41 rehayes 
        xgr5 <= (|write_xgr5 && perif_wrt_ena) ?
522 
                {(write_xgr5[1] ? perif_data[15:8]: xgr5[15:8]),
523 
                 (write_xgr5[0] ? perif_data[ 7:0]: xgr5[ 7:0])} :
524 2 rehayes 
                {((wrt_sel_xgr5 && ena_rd_high_byte) ? alu_result[15:8] : xgr5[15:8]),
525 
                 ((wrt_sel_xgr5 && ena_rd_low_byte)  ? alu_result[ 7:0] : xgr5[ 7:0])};
526 41 rehayes 
        xgr6 <= (|write_xgr6 && perif_wrt_ena) ?
527 
                {(write_xgr6[1] ? perif_data[15:8]: xgr6[15:8]),
528 
                 (write_xgr6[0] ? perif_data[ 7:0]: xgr6[ 7:0])} :
529 2 rehayes 
                {((wrt_sel_xgr6 && ena_rd_high_byte) ? alu_result[15:8] : xgr6[15:8]),
530 
                 ((wrt_sel_xgr6 && ena_rd_low_byte)  ? alu_result[ 7:0] : xgr6[ 7:0])};
531 41 rehayes 
        xgr7 <= (|write_xgr7 && perif_wrt_ena) ?
532 
                {(write_xgr7[1] ? perif_data[15:8]: xgr7[15:8]),
533 
                 (write_xgr7[0] ? perif_data[ 7:0]: xgr7[ 7:0])} :
534 2 rehayes 
                {((wrt_sel_xgr7 && ena_rd_high_byte) ? alu_result[15:8] : xgr7[15:8]),
535 
                 ((wrt_sel_xgr7 && ena_rd_low_byte)  ? alu_result[ 7:0] : xgr7[ 7:0])};
536 
      end
537 
 
538 
  // V Ñ Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
539 
  // P Ñ Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
540 
  // r Ñ 8-bit data read: lasts for at least one RISC core cycle
541 
  // R Ñ 16-bit data read: lasts for at least one RISC core cycle
542 
  // w Ñ 8-bit data write: lasts for at least one RISC core cycle
543 
  // W Ñ 16-bit data write: lasts for at least one RISC core cycle
544 
  // A Ñ Alignment cycle: no read or write, lasts for zero or one RISC core cycles
545 
  // f Ñ Free cycle: no read or write, lasts for one RISC core cycles
546 
  // Special Cases
547 
  // PP/P Ñ Branch: PP if branch taken, P if not taken
548 
 
549 
  always @*
550 
    begin
551 
      ena_rd_low_byte  = 1'b0;
552 
      ena_rd_high_byte = 1'b0;
553 
 
554 64 rehayes 
      next_cpu_state = (debug_active || cmd_dbg) ? LD_INST : CONT;
555 2 rehayes 
      load_next_inst = 1'b1;
556 64 rehayes 
      pc_incr_mux    = cmd_dbg ? 16'h0000: 16'h0002;  // Verilog Instruction order dependent
557 40 rehayes 
      next_pc        = pc_sum;    // ""
558 2 rehayes 
 
559 
      next_zero      = zero_flag;
560 
      next_negative  = negative_flag;
561 
      next_carry     = carry_flag;
562 
      next_overflow  = overflow_flag;
563 
 
564 12 rehayes 
      brk_set_dbg    = 1'b0;
565 
      op_code_error  = 1'b0;
566 
 
567 2 rehayes 
      alu_result     = 16'h0000;
568 
      sel_rd_field   = 1'b1;
569 12 rehayes 
 
570 2 rehayes 
      data_access    = 1'b0;
571 
      data_word_op   = 1'b0;
572 12 rehayes 
      data_write     = 1'b0;
573 2 rehayes 
      data_address   = 16'h0000;
574 
 
575 
      shift_left     = 1'b0;
576 
      shift_ammount  = 5'b0_0000;
577 
      shift_filler   = 16'h0000;
578 
      shift_in       = rd_data;
579 12 rehayes 
 
580 2 rehayes 
      set_irq_flag   = 7'b0;
581 12 rehayes 
 
582 2 rehayes 
      set_semaph    = 1'b0;
583 
      clear_semaph  = 1'b0;
584 
      semaph_risc   = 3'b0;
585 
 
586 
  casez ({cpu_state, op_code})
587 
 
588 
      {IDLE, 16'b????????????????} :
589 
         begin
590 
           next_cpu_state   = start_thread ? BOOT_1 : IDLE;
591 40 rehayes 
           pc_incr_mux      = 16'h0000;
592 
           next_pc          = pc_sum;
593 2 rehayes 
           load_next_inst   = 1'b0;
594 
         end
595 
 
596 17 rehayes 
      {CHG_CHID, 16'b????????????????} :
597 
         begin
598 
           if (!xge)
599 
             next_cpu_state = IDLE;
600 53 rehayes 
           else if (ss_mem_ack || !debug_active)
601 17 rehayes 
             next_cpu_state = BOOT_1;
602 
           else
603 
             next_cpu_state = CHG_CHID;
604 
 
605 40 rehayes 
           pc_incr_mux      = 16'h0000;
606 
           next_pc          = pc_sum;
607 17 rehayes 
           load_next_inst   = 1'b0;
608 
         end
609 
 
610 2 rehayes 
      // Output RAM address for Program Counter
611 
      {BOOT_1, 16'b????????????????} :
612 
         begin
613 
           next_cpu_state   = BOOT_2;
614 40 rehayes 
           pc_incr_mux      = 16'h0000;
615 
           next_pc          = pc_sum;
616 2 rehayes 
           load_next_inst   = 1'b0;
617 
           data_access      = 1'b1;
618 
           data_word_op     = 1'b1;
619 
           data_address     = {xgvbr, 1'b0} + {7'b0, xgchid, 2'b0};
620 
         end
621 
 
622 
      // Load PC value from data buffer register
623 
      // Output RAM address for initial variable pointer
624 
      {BOOT_2, 16'b????????????????} :
625 
         begin
626 
           next_cpu_state   = BOOT_3;
627 
           next_pc          = load_data;
628 
           load_next_inst   = 1'b0;
629 
           data_access      = 1'b1;
630 
           data_word_op     = 1'b1;
631 
           data_address     = {xgvbr, 1'b0} + {7'b0, xgchid, 2'b0} + 2;
632 
         end
633 
 
634 
      // Load R1 with initial variable pointer from data buffer register
635 
      // Load first instruction to op_code register
636 
      // Increment Program Counter
637 
      {BOOT_3, 16'b????????????????} :
638 
         begin
639 
           next_cpu_state   = CONT;
640 
           ena_rd_low_byte  = 1'b1;
641 
           ena_rd_high_byte = 1'b1;
642 
           alu_result       = load_data;
643 
         end
644 
 
645 12 rehayes 
      {BREAK, 16'b????????????????} :
646 
         begin
647 17 rehayes 
           if (!xge)
648 
             next_cpu_state = IDLE;
649 53 rehayes 
           else if (ss_mem_ack || !debug_active)
650 17 rehayes 
             next_cpu_state = BREAK_2;
651 
           else if (chid_goto_idle)
652 
             next_cpu_state = CHG_CHID;
653 
           else
654 
             next_cpu_state = BREAK;
655 12 rehayes 
           load_next_inst = 1'b0;
656 40 rehayes 
           pc_incr_mux    = 16'h0000;
657 
           next_pc        = pc_sum;
658 12 rehayes 
         end
659 
 
660 
      {BREAK_2, 16'b????????????????} :
661 
         begin
662 
           next_cpu_state = LD_INST;
663 
           load_next_inst = 1'b0;
664 
         end
665 
 
666 
      {LD_INST, 16'b????????????????} :
667 
         begin
668 
           next_cpu_state = DEBUG;
669 40 rehayes 
           pc_incr_mux    = 16'h0000;
670 
           next_pc        = pc_sum;
671 12 rehayes 
         end
672 
 
673 2 rehayes 
      {DEBUG, 16'b????????????????} :
674 
         begin
675 17 rehayes 
           if (!xge)
676 
             next_cpu_state = IDLE;
677 53 rehayes 
           else if (ss_mem_ack || !debug_active)
678 17 rehayes 
             next_cpu_state = CONT;
679 
           else if (cmd_change_pc)
680 
             next_cpu_state = LD_INST;
681 
           else if (chid_goto_idle)
682 
             next_cpu_state = CHG_CHID;
683 
           else
684 
             next_cpu_state = DEBUG;
685 
 
686 15 rehayes 
           load_next_inst = cmd_change_pc;
687 40 rehayes 
           pc_incr_mux    = 16'h0000;
688 
           next_pc        = pc_sum;
689 2 rehayes 
         end
690 
 
691 12 rehayes 
      // Pause here for program counter change of flow or memory write access
692 5 rehayes 
      //  Load next instruction and increment PC
693 12 rehayes 
      // Default next_cpu_state is CONT
694 5 rehayes 
      {S_STALL, 16'b????????????????} :
695 
         begin
696 
         end
697 
 
698 
      // Pause here for memory read word access
699 
      //  Load next instruction and increment PC
700 40 rehayes 
      {W_LOAD, 16'b????????????????} :
701 5 rehayes 
         begin
702 
           alu_result       = load_data;
703 
           ena_rd_low_byte  = 1'b1;
704 
           ena_rd_high_byte = 1'b1;
705 
         end
706 
 
707 
      // Pause here for memory read byte access
708 
      //  Load next instruction and increment PC
709 40 rehayes 
      {B_LOAD, 16'b????????????????} :
710 5 rehayes 
         begin
711 
           alu_result       = {8'h00, load_data[15:8]};
712 
           ena_rd_low_byte  = 1'b1;
713 
           ena_rd_high_byte = 1'b1;
714 
         end
715 
 
716 2 rehayes 
      // -----------------------------------------------------------------------
717 
      // Instruction Group -- Return to Scheduler and Others
718 
      // -----------------------------------------------------------------------
719 
 
720 
      // Instruction = BRK, Op Code =  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
721 
      // Cycles - PAff
722 
      {CONT, 16'b0000000000000000} :
723 
         begin
724 12 rehayes 
           next_cpu_state   = BREAK;
725 40 rehayes 
           pc_incr_mux      = 16'hfffe;  // equals -2
726 
           next_pc          = pc_sum;
727 2 rehayes 
           load_next_inst   = 1'b0;
728 12 rehayes 
           brk_set_dbg      = 1'b1;
729 2 rehayes 
         end
730 
 
731 
      // Instruction = NOP, Op Code =  0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
732 
      {CONT, 16'b0000000100000000} :
733 
         begin
734 
         end
735 
 
736 
      // Instruction = RTS, Op Code =  0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
737 
      // Cycles - PA
738 
      {CONT, 16'b0000001000000000} :
739 
         begin
740 
           next_cpu_state   = IDLE;
741 40 rehayes 
           pc_incr_mux      = 16'h0000;
742 
           next_pc          = pc_sum;
743 2 rehayes 
           load_next_inst   = 1'b0;
744 
         end
745 
 
746 
      // Instruction = SIF, Op Code =  0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
747 
      // Sets the Interrupt Flag of the current channel (XGCHID) will be set.
748 
      // Cycles - PA
749 
      {CONT, 16'b0000001100000000} :
750 
         begin
751 
           set_irq_flag = xgchid;
752 
         end
753 
 
754 
      // -----------------------------------------------------------------------
755 
      // Instruction Group -- Semaphore Instructions
756 
      // -----------------------------------------------------------------------
757 
 
758 
      // Instruction = CSEM IMM3, Op Code =  0 0 0 0 0 IMM3 1 1 1 1 0 0 0 0
759 
      // Unlocks a semaphore that was locked by the RISC core.
760 
      // Cycles - PA
761 
      {CONT, 16'b00000???11110000} :
762 
         begin
763 
           clear_semaph = 1'b1;
764 
           semaph_risc  = op_code[10:8];
765 
         end
766 
 
767 
      // Instruction = CSEM RS, Op Code =  0 0 0 0 0 RS 1 1 1 1 0 0 0 1
768 
      // Unlocks a semaphore that was locked by the RISC core.
769 
      // In monadic address mode, bits RS[2:0] select the semaphore to be cleared.
770 
      // Cycles - PA
771 
      {CONT, 16'b00000???11110001} :
772 
         begin
773 
           clear_semaph = 1'b1;
774 
           semaph_risc  = rd_data[2:0];
775 
         end
776 
 
777 
      // Instruction = SSEM IMM3, Op Code =  0 0 0 0 0 IMM3 1 1 1 1 0 0 1 0
778 
      // Attempts to set a semaphore. The state of the semaphore will be stored in the Carry-Flag:
779 
      // 1 = Semaphore is locked by the RISC core
780 
      // 0 = Semaphore is locked by the S12X_CPU
781 
      // Cycles - PA
782 
      {CONT, 16'b00000???11110010} :
783 
         begin
784 
           set_semaph  = 1'b1;
785 
           semaph_risc = op_code[10:8];
786 
 
787 
           next_carry    = semaph_stat;
788 
         end
789 
 
790 
      // Instruction = SSEM RS, Op Code =  0 0 0 0 0 RS 1 1 1 1 0 0 1 1
791 
      // Attempts to set a semaphore. The state of the semaphore will be stored in the Carry-Flag:
792 
      // 1 = Semaphore is locked by the RISC core
793 
      // 0 = Semaphore is locked by the S12X_CPU
794 
      // In monadic address mode, bits RS[2:0] select the semaphore to be set.
795 
      // Cycles - PA
796 
      {CONT, 16'b00000???11110011} :
797 
         begin
798 
           set_semaph  = 1'b1;
799 
           semaph_risc = rd_data[2:0];
800 
 
801 
           next_carry    = semaph_stat;
802 
         end
803 
 
804 
      // -----------------------------------------------------------------------
805 
      // Instruction Group -- Single Register Instructions
806 
      // -----------------------------------------------------------------------
807 
 
808 
      // Instruction = SEX RD, Op Code =  0 0 0 0 0 RD 1 1 1 1 0 1 0 0
809 
      // SEX - Sign Extend Byte to Word
810 
      // Cycles - P
811 
      {CONT, 16'b00000???11110100} :
812 
         begin
813 
           ena_rd_high_byte = 1'b1;
814 
 
815 
           alu_result    = {{8{rd_data[7]}}, rd_data[7:0]};
816 
           next_zero     = !(|alu_result);
817 
           next_negative = alu_result[15];
818 
           next_overflow = 1'b0;
819 
         end
820 
 
821 
      // Instruction = PAR RD, Op Code =  0 0 0 0 0 RD 1 1 1 1 0 1 0 1
822 
      // PAR - Calculate Parity
823 
      // Set Carry Flag on odd number of bits
824 
      // Cycles - P
825 
      {CONT, 16'b00000???11110101} :
826 
         begin
827 
           next_zero     = !(|rd_data);
828 
           next_negative = 1'b0;
829 
           next_carry    = ^rd_data;
830 
           next_overflow = 1'b0;
831 
         end
832 
 
833 
      // Instruction = JAL RD, Op Code =  0 0 0 0 0 RD 1 1 1 1 0 1 1 0
834 
      // Jump And Link
835 
      // PC + $0002 => RD; RD => PC
836 
      // Jumps to the address stored in RD and saves the return address in RD.
837 
      // Cycles - PP
838 
      {CONT, 16'b00000???11110110} :
839 
         begin
840 5 rehayes 
           next_cpu_state   = S_STALL;
841 2 rehayes 
           load_next_inst   = 1'b0;
842 
           ena_rd_low_byte  = 1'b1;
843 
           ena_rd_high_byte = 1'b1;
844 
           alu_result       = program_counter;
845 
           next_pc          = rd_data;
846 
         end
847 
 
848 
      // Instruction = SIF RS, Op Code =  0 0 0 0 0 RS 1 1 1 1 0 1 1 1
849 
      // Sets the Interrupt Flag associated with the channel id number
850 
      // contained in RS[6:0] is set. The content of RS[15:7] is ignored
851 
      // Cycles - P
852 
      {CONT, 16'b00000???11110111} :
853 
         begin
854 
           set_irq_flag = rd_data[6:0];
855 
         end
856 
 
857 
      // -----------------------------------------------------------------------
858 
      // Instruction Group -- Special Move instructions
859 
      // -----------------------------------------------------------------------
860 
 
861 
      // Instruction = TFR RD,CCR, Op Code =  0 0 0 0 0 RD 1 1 1 1 1 0 0 0
862 
      // Transfer from and to Special Registers
863 
      // TFR RD,CCR: CCR => RD[3:0], 0 => RD[15:4]
864 
      // Cycles - P
865 
      {CONT, 16'b00000???11111000} :
866 
         begin
867 
           ena_rd_low_byte  = 1'b1;
868 
           ena_rd_high_byte = 1'b1;
869 
           alu_result       = {12'b0, negative_flag, zero_flag, overflow_flag, carry_flag};
870 
         end
871 
 
872 
      // Instruction = TFR CCR,RS, Op Code =  0 0 0 0 0 RS 1 1 1 1 1 0 0 1
873 
      // Transfer from and to Special Registers
874 
      // TFR CCR,RD: RD[3:0] => CCR
875 
      // Cycles - P
876 
      {CONT, 16'b00000???11111001} :
877 
         begin
878 
           next_negative = rd_data[3];
879 
           next_zero     = rd_data[2];
880 
           next_overflow = rd_data[1];
881 
           next_carry    = rd_data[0];
882 
         end
883 
 
884 
      // Instruction = TFR RD,PC, Op Code =  0 0 0 0 0 RD 1 1 1 1 1 0 1 0
885 
      // Transfer from and to Special Registers
886 
      // TFR RD,PC: PC+4 => RD
887 
      // Cycles - P
888 
      {CONT, 16'b00000???11111010} :
889 
         begin
890 
           ena_rd_low_byte  = 1'b1;
891 
           ena_rd_high_byte = 1'b1;
892 
           alu_result       = next_pc;
893 
         end
894 
 
895 
      // -----------------------------------------------------------------------
896 
      // Instruction Group -- Shift instructions Dyadic
897 
      // -----------------------------------------------------------------------
898 
 
899 
      // Instruction = BFFO RD, RS, Op Code =  0 0 0 0 1 RD RS 1 0 0 0 0
900 
      // BFFO - Bit Field Find First One
901 
      // FirstOne (RS) => RD
902 
      // Cycles - P
903 
      {CONT, 16'b00001??????10000} :
904 
         begin
905 
           ena_rd_low_byte  = 1'b1;
906 
           ena_rd_high_byte = 1'b1;
907 
 
908 26 rehayes 
           casez (rs1_data)  // synopsys parallel_case
909 2 rehayes 
             16'b1???_????_????_???? : alu_result = 16'h000f;
910 
             16'b01??_????_????_???? : alu_result = 16'h000e;
911 
             16'b001?_????_????_???? : alu_result = 16'h000d;
912 
             16'b0001_????_????_???? : alu_result = 16'h000c;
913 
             16'b0000_1???_????_???? : alu_result = 16'h000b;
914 
             16'b0000_01??_????_???? : alu_result = 16'h000a;
915 
             16'b0000_001?_????_???? : alu_result = 16'h0009;
916 
             16'b0000_0001_????_???? : alu_result = 16'h0008;
917 
             16'b0000_0000_1???_???? : alu_result = 16'h0007;
918 
             16'b0000_0000_01??_???? : alu_result = 16'h0006;
919 
             16'b0000_0000_001?_???? : alu_result = 16'h0005;
920 
             16'b0000_0000_0001_???? : alu_result = 16'h0004;
921 
             16'b0000_0000_0000_1??? : alu_result = 16'h0003;
922 
             16'b0000_0000_0000_01?? : alu_result = 16'h0002;
923 
             16'b0000_0000_0000_001? : alu_result = 16'h0001;
924 
             16'b0000_0000_0000_0001 : alu_result = 16'h0000;
925 
           endcase
926 
           next_zero     = !(|alu_result);
927 
           next_negative = 1'b0;
928 
           next_carry    = !(|rs1_data);
929 
           next_overflow = 1'b0;
930 
         end
931 
 
932 
      // Instruction = ASR RD, RS, Op Code =  0 0 0 0 1 RD RS 1 0 0 0 1
933 
      // ASR - Arithmetic Shift Right
934 
      // n = RS
935 
      // Cycles - P
936 
      {CONT, 16'b00001??????10001} :
937 
         begin
938 
           shift_ammount  = {|rs1_data[15:4], rs1_data[3:0]};
939 
           shift_filler   = {16{rd_data[15]}};
940 12 rehayes 
 
941 2 rehayes 
           ena_rd_low_byte  = 1'b1;
942 
           ena_rd_high_byte = 1'b1;
943 
           alu_result       = shift_out;
944 
           next_zero        = !(|alu_result);
945 
           next_negative    = alu_result[15];
946 
           next_carry       = |rs1_data ? shift_rollover : carry_flag;
947 
           next_overflow    = rd_data[15] ^ alu_result[15];  // Table and text disagree
948 
         end
949 
 
950 
      // Instruction = CSL RD, RS, Op Code =  0 0 0 0 1 RD RS 1 0 0 1 0
951 
      // CSL - Logical Shift Left with Carry
952 
      // n = RS
953 
      // Cycles - P
954 
      {CONT, 16'b00001??????10010} :
955 
         begin
956 
           shift_left     = 1'b1;
957 
           shift_ammount  = {|rs1_data[15:4], rs1_data[3:0]};
958 
           shift_filler   = {16{carry_flag}};
959 
 
960 
           ena_rd_low_byte  = 1'b1;
961 
           ena_rd_high_byte = 1'b1;
962 
           alu_result       = shift_out;
963 
           next_zero        = !(|alu_result);
964 
           next_negative    = alu_result[15];
965 
           next_carry       = |rs1_data ? shift_rollover : carry_flag;
966 
           next_overflow    = rd_data[15] ^ alu_result[15];
967 
         end
968 
 
969 
      // Instruction = CSR RD, RS, Op Code =  0 0 0 0 1 RD RS 1 0 0 1 1
970 
      // Logical Shift Right with Carry
971 
      // n = RS
972 
      // Cycles - P
973 
      {CONT, 16'b00001??????10011} :
974 
         begin
975 
           shift_ammount  = {|rs1_data[15:4], rs1_data[3:0]};
976 
           shift_filler   = {16{carry_flag}};
977 
 
978 
           ena_rd_low_byte  = 1'b1;
979 
           ena_rd_high_byte = 1'b1;
980 
           alu_result       = shift_out;
981 
           next_zero        = !(|alu_result);
982 
           next_negative    = alu_result[15];
983 
           next_carry       = |rs1_data ? shift_rollover : carry_flag;
984 
           next_overflow    = rd_data[15] ^ alu_result[15];
985 
         end
986 
 
987 
      // Instruction = LSL RD, RS, Op Code =  0 0 0 0 1 RD RS 1 0 1 0 0
988 
      // Logical Shift Left
989 
      // n = RS
990 
      // Cycles - P
991 
      {CONT, 16'b00001??????10100} :
992 
         begin
993 
           shift_left     = 1'b1;
994 
           shift_ammount  = {|rs1_data[15:4], rs1_data[3:0]};
995 
           shift_filler   = 16'h0000;
996 
 
997 
           ena_rd_low_byte  = 1'b1;
998 
           ena_rd_high_byte = 1'b1;
999 
           alu_result       = shift_out;
1000 
           next_zero        = !(|alu_result);
1001 
           next_negative    = alu_result[15];
1002 
           next_carry       = |rs1_data ? shift_rollover : carry_flag;
1003 
           next_overflow    = rd_data[15] ^ alu_result[15];
1004 
         end
1005 
 
1006 
      // Instruction = LSR RD, RS, Op Code =  0 0 0 0 1 RD RS 1 0 1 0 1
1007 
      // Logical Shift Right
1008 
      // n = RS
1009 
      // Cycles - P
1010 
      {CONT, 16'b00001??????10101} :
1011 
         begin
1012 
           shift_ammount  = {|rs1_data[15:4], rs1_data[3:0]};
1013 
           shift_filler   = 16'h0000;
1014 
 
1015 
           ena_rd_low_byte  = 1'b1;
1016 
           ena_rd_high_byte = 1'b1;
1017 
           alu_result       = shift_out;
1018 
           next_zero        = !(|alu_result);
1019 
           next_negative    = alu_result[15];
1020 
           next_carry       = |rs1_data ? shift_rollover : carry_flag;
1021 
           next_overflow    = rd_data[15] ^ alu_result[15];
1022 
         end
1023 
 
1024 
      // Instruction = ROL RD, RS, Op Code =  0 0 0 0 1 RD RS 1 0 1 1 0
1025 
      // Rotate Left
1026 
      // n = RS
1027 
      // Cycles - P
1028 
      {CONT, 16'b00001??????10110} :
1029 
         begin
1030 
           shift_left     = 1'b1;
1031 
           shift_ammount  = {1'b0, rs1_data[3:0]};
1032 
           shift_filler   = rd_data;
1033 
 
1034 
           ena_rd_low_byte  = 1'b1;
1035 
           ena_rd_high_byte = 1'b1;
1036 
           alu_result       = shift_out;
1037 
           next_zero        = !(|alu_result);
1038 
           next_negative    = alu_result[15];
1039 
           next_overflow    = 1'b0;
1040 
         end
1041 
 
1042 
      // Instruction = ROR RD, RS, Op Code =  0 0 0 0 1 RD RS 1 0 1 1 1
1043 
      // Rotate Right
1044 
      // n = RS
1045 
      // Cycles - P
1046 
      {CONT, 16'b00001??????10111} :
1047 
         begin
1048 
           shift_ammount  = {1'b0, rs1_data[3:0]};
1049 
           shift_filler   = rd_data;
1050 
 
1051 
           ena_rd_low_byte  = 1'b1;
1052 
           ena_rd_high_byte = 1'b1;
1053 
           alu_result       = shift_out;
1054 
           next_zero        = !(|alu_result);
1055 
           next_negative    = alu_result[15];
1056 
           next_overflow    = 1'b0;
1057 
         end
1058 
 
1059 
      // -----------------------------------------------------------------------
1060 
      // Instruction Group -- Shift instructions immediate
1061 
      // -----------------------------------------------------------------------
1062 
 
1063 
      // Instruction = ASR RD, #IMM4, Op Code =  0 0 0 0 1 RD IMM4 1 0 0 1
1064 
      // ASR - Arithmetic Shift Right
1065 
      // n = IMM4
1066 
      // Cycles - P
1067 
      {CONT, 16'b00001???????1001} :
1068 
         begin
1069 
           shift_ammount  = {!(|op_code[7:4]), op_code[7:4]};
1070 
           shift_filler   = {16{rd_data[15]}};
1071 12 rehayes 
 
1072 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1073 
           ena_rd_high_byte = 1'b1;
1074 
           alu_result       = shift_out;
1075 
           next_zero        = !(|alu_result);
1076 
           next_negative    = alu_result[15];
1077 
           next_carry       = shift_rollover;
1078 
           next_overflow    = rd_data[15] ^ alu_result[15];  // Table and text disagree
1079 
         end
1080 
 
1081 
      // Instruction = CSL RD, #IMM4, Op Code =  0 0 0 0 1 RD IMM4 1 0 1 0
1082 
      // CSL - Logical Shift Left with Carry
1083 
      // n = IMM4
1084 
      // Cycles - P
1085 
      {CONT, 16'b00001???????1010} :
1086 
         begin
1087 
           shift_left     = 1'b1;
1088 
           shift_ammount  = {!(|op_code[7:4]), op_code[7:4]};
1089 
           shift_filler   = {16{carry_flag}};
1090 12 rehayes 
 
1091 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1092 
           ena_rd_high_byte = 1'b1;
1093 
           alu_result       = shift_out;
1094 
           next_zero        = !(|alu_result);
1095 
           next_negative    = alu_result[15];
1096 
           next_carry       = shift_rollover;
1097 
           next_overflow    = rd_data[15] ^ alu_result[15];
1098 
         end
1099 
 
1100 
      // Instruction = CSR RD, #IMM4, Op Code =  0 0 0 0 1 RD IMM4 1 0 1 1
1101 
      // CSR - Logical Shift Right with Carry
1102 
      // n = IMM4
1103 
      // Cycles - P
1104 
      {CONT, 16'b00001???????1011} :
1105 
         begin
1106 
           shift_ammount  = {!(|op_code[7:4]), op_code[7:4]};
1107 
           shift_filler   = {16{carry_flag}};
1108 
 
1109 
           ena_rd_low_byte  = 1'b1;
1110 
           ena_rd_high_byte = 1'b1;
1111 
           alu_result       = shift_out;
1112 
           next_zero        = !(|alu_result);
1113 
           next_negative    = alu_result[15];
1114 
           next_carry       = shift_rollover;
1115 
           next_overflow    = rd_data[15] ^ alu_result[15];
1116 
         end
1117 
 
1118 
      // Instruction = LSL RD, #IMM4, Op Code =  0 0 0 0 1 RD IMM4 1 1 0 0
1119 
      // LSL - Logical Shift Left
1120 
      // n = IMM4
1121 
      // Cycles - P
1122 
      {CONT, 16'b00001???????1100} :
1123 
         begin
1124 
           shift_left     = 1'b1;
1125 
           shift_ammount  = {!(|op_code[7:4]), op_code[7:4]};
1126 
           shift_filler   = 16'h0000;
1127 12 rehayes 
 
1128 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1129 
           ena_rd_high_byte = 1'b1;
1130 
           alu_result       = shift_out;
1131 
           next_zero        = !(|alu_result);
1132 
           next_negative    = alu_result[15];
1133 
           next_carry       = shift_rollover;
1134 
           next_overflow    = rd_data[15] ^ alu_result[15];
1135 
         end
1136 
 
1137 
      // Instruction = LSR RD, #IMM4, Op Code =  0 0 0 0 1 RD IMM4 1 1 0 1
1138 
      // LSR - Logical Shift Right
1139 
      // n = IMM4
1140 
      // Cycles - P
1141 
      {CONT, 16'b00001???????1101} :
1142 
         begin
1143 
           shift_ammount  = {!(|op_code[7:4]), op_code[7:4]};
1144 
           shift_filler   = 16'h0000;
1145 12 rehayes 
 
1146 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1147 
           ena_rd_high_byte = 1'b1;
1148 
           alu_result       = shift_out;
1149 
           next_zero        = !(|alu_result);
1150 
           next_negative    = alu_result[15];
1151 
           next_carry       = shift_rollover;
1152 
           next_overflow    = rd_data[15] ^ alu_result[15];
1153 
         end
1154 
 
1155 
      // Instruction = ROL RD, #IMM4, Op Code =  0 0 0 0 1 RD IMM4 1 1 1 0
1156 
      // ROL - Rotate Left
1157 
      // n = IMM4
1158 
      // Cycles - P
1159 
      {CONT, 16'b00001???????1110} :
1160 
         begin
1161 
           shift_left     = 1'b1;
1162 
           shift_ammount  = {1'b0, op_code[7:4]};
1163 
           shift_filler   = rd_data;
1164 12 rehayes 
 
1165 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1166 
           ena_rd_high_byte = 1'b1;
1167 
           alu_result       = shift_out;
1168 
           next_zero        = !(|alu_result);
1169 
           next_negative    = alu_result[15];
1170 
           next_overflow    = 1'b0;
1171 
         end
1172 
 
1173 
      // Instruction = ROR RD, #IMM4, Op Code =  0 0 0 0 1 RD IMM4 1 1 1 1
1174 
      // ROR - Rotate Right
1175 
      // n = IMM4
1176 
      // Cycles - P
1177 
      {CONT, 16'b00001???????1111} :
1178 
         begin
1179 
           shift_ammount  = {1'b0, op_code[7:4]};
1180 
           shift_filler   = rd_data;
1181 12 rehayes 
 
1182 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1183 
           ena_rd_high_byte = 1'b1;
1184 
           alu_result       = shift_out;
1185 
           next_zero        = !(|alu_result);
1186 
           next_negative    = alu_result[15];
1187 
           next_overflow    = 1'b0;
1188 
         end
1189 
 
1190 
      // -----------------------------------------------------------------------
1191 
      // Instruction Group -- Logical Triadic
1192 
      // -----------------------------------------------------------------------
1193 
 
1194 
      // Instruction = AND RD, RS1, RS2, Op Code =  0 0 0 1 0 RD RS1 RS2 0 0
1195 
      // AND - Logical AND
1196 
      // RS1 & RS2 => RD
1197 
      // Cycles - P
1198 
      {CONT, 16'b00010?????????00} :
1199 
         begin
1200 
           ena_rd_low_byte  = 1'b1;
1201 
           ena_rd_high_byte = 1'b1;
1202 
 
1203 
           alu_result    = rs1_data & rs2_data;
1204 
           next_zero     = !(|alu_result);
1205 
           next_negative = alu_result[15];
1206 
           next_overflow = 1'b0;
1207 
         end
1208 
 
1209 
      // Instruction = OR RD, RS1, RS2, Op Code =  0 0 0 1 0 RD RS1 RS2 1 0
1210 
      // OR - Logical OR
1211 
      // RS1 | RS2 => RD
1212 
      // Cycles - P
1213 
      {CONT, 16'b00010?????????10} :
1214 
         begin
1215 
           ena_rd_low_byte  = 1'b1;
1216 
           ena_rd_high_byte = 1'b1;
1217 
 
1218 
           alu_result    = rs1_data | rs2_data;
1219 
           next_zero     = !(|alu_result);
1220 
           next_negative = alu_result[15];
1221 
           next_overflow = 1'b0;
1222 
          end
1223 
 
1224 
      // Instruction = XNOR RD, RS1, RS2, Op Code =  0 0 0 1 0 RD RS1 RS2 1 1
1225 
      // XNOR - Logical Exclusive NOR
1226 
      // ~(RS1 ^ RS2) => RD
1227 
      // Cycles - P
1228 
      {CONT, 16'b00010?????????11} :
1229 
         begin
1230 
           ena_rd_low_byte  = 1'b1;
1231 
           ena_rd_high_byte = 1'b1;
1232 
 
1233 
           alu_result    = ~(rs1_data ^ rs2_data);
1234 
           next_zero     = !(|alu_result);
1235 
           next_negative = alu_result[15];
1236 
           next_overflow = 1'b0;
1237 
         end
1238 
 
1239 
      // -----------------------------------------------------------------------
1240 
      // Instruction Group -- Arithmetic Triadic
1241 
      // -----------------------------------------------------------------------
1242 
 
1243 
      // Instruction = SUB RD, RS1, RS2, Op Code =  0 0 0 1 1 RD RS1 RS2 0 0
1244 
      // SUB - Subtract without Carry
1245 
      // RS1 - RS2 => RD
1246 
      // Cycles - P
1247 
      {CONT, 16'b00011?????????00} :
1248 
         begin
1249 
           ena_rd_low_byte  = 1'b1;
1250 
           ena_rd_high_byte = 1'b1;
1251 
 
1252 
           {next_carry, alu_result}    = rs1_data - rs2_data;
1253 
           next_zero     = !(|alu_result);
1254 
           next_negative = alu_result[15];
1255 
           next_overflow = (rs1_data[15] && !rs2_data[15] && !alu_result[15]) || (!rs1_data[15] && rs2_data[15] && alu_result[15]);
1256 
         end
1257 
 
1258 
      // Instruction = SBC RD, RS1, RS2, Op Code =  0 0 0 1 1 RD RS1 RS2 0 1
1259 
      // SBC - Subtract with Carry
1260 
      // RS1 - RS2 - C => RD
1261 
      // Cycles - P
1262 
      {CONT, 16'b00011?????????01} :
1263 
         begin
1264 
           ena_rd_low_byte  = 1'b1;
1265 
           ena_rd_high_byte = 1'b1;
1266 
 
1267 
           {next_carry, alu_result}    = rs1_data - rs2_data - {15'b0, carry_flag};
1268 47 rehayes 
           next_zero     = !(|alu_result) && zero_flag;
1269 2 rehayes 
           next_negative = alu_result[15];
1270 
           next_overflow = (rs1_data[15] && !rs2_data[15] && !alu_result[15]) || (!rs1_data[15] && rs2_data[15] && alu_result[15]);
1271 
         end
1272 
 
1273 
      // Instruction = ADD RD, RS1, RS2, Op Code =  0 0 0 1 1 RD RS1 RS2 1 0
1274 
      // ADD - ADD without carry
1275 
      // RS1 + RS2 => RD
1276 
      // Cycles - P
1277 
      {CONT, 16'b00011?????????10} :
1278 
         begin
1279 
           ena_rd_low_byte  = 1'b1;
1280 
           ena_rd_high_byte = 1'b1;
1281 
 
1282 
           {next_carry, alu_result}    = rs1_data + rs2_data;
1283 
           next_zero     = !(|alu_result);
1284 
           next_negative = alu_result[15];
1285 
           next_overflow = (rs1_data[15] && rs2_data[15] && !alu_result[15]) || (!rs1_data[15] && !rs2_data[15] && alu_result[15]);
1286 
         end
1287 
 
1288 
      // Instruction = ADC RD, RS1, RS2, Op Code =  0 0 0 1 1 RD RS1 RS2 1 1
1289 
      // ADC - add with carry
1290 
      // RS1 + RS2 + C => RD
1291 
      // Cycles - P
1292 
      {CONT, 16'b00011?????????11} :
1293 
         begin
1294 
           ena_rd_low_byte  = 1'b1;
1295 
           ena_rd_high_byte = 1'b1;
1296 
 
1297 
           {next_carry, alu_result}    = rs1_data + rs2_data + {15'b0, carry_flag};
1298 47 rehayes 
           next_zero     = !(|alu_result) && zero_flag;
1299 2 rehayes 
           next_negative = alu_result[15];
1300 
           next_overflow = (rs1_data[15] && rs2_data[15] && !alu_result[15]) || (!rs1_data[15] && !rs2_data[15] && alu_result[15]);
1301 
         end
1302 
 
1303 
      // -----------------------------------------------------------------------
1304 
      // Instruction Group -- Branches
1305 
      // -----------------------------------------------------------------------
1306 
 
1307 
      // Instruction = BCC REL9, Op Code =  0 0 1 0 0 0 0 REL9
1308 
      // Branch if Carry Cleared
1309 
      // If C = 0, then PC + $0002 + (REL9 << 1) => PC
1310 
      // Cycles - PP/P
1311 
      {CONT, 16'b0010000?????????} :
1312 
         begin
1313 
           if (!carry_flag)
1314 
             begin
1315 5 rehayes 
               next_cpu_state = S_STALL;
1316 2 rehayes 
               load_next_inst = 1'b0;
1317 40 rehayes 
               pc_incr_mux    = jump_offset;
1318 
               next_pc        = pc_sum;  // There is a race condition when the default declaration is used
1319 2 rehayes 
             end
1320 
         end
1321 
 
1322 
      // Instruction = BCS REL9, Op Code =  0 0 1 0 0 0 1 REL9
1323 
      // Branch if Carry Set
1324 
      // If C = 1, then PC + $0002 + (REL9 << 1) => PC
1325 
      // Cycles - PP/P
1326 
      {CONT, 16'b0010001?????????} :
1327 
         begin
1328 
           if (carry_flag)
1329 
             begin
1330 5 rehayes 
               next_cpu_state = S_STALL;
1331 2 rehayes 
               load_next_inst = 1'b0;
1332 40 rehayes 
               pc_incr_mux    = jump_offset;
1333 
               next_pc        = pc_sum;
1334 2 rehayes 
             end
1335 
         end
1336 
 
1337 
      // Instruction = BNE REL9, Op Code =  0 0 1 0 0 1 0 REL9
1338 
      // Branch if Not Equal
1339 
      // If Z = 0, then PC + $0002 + (REL9 << 1) => PC
1340 
      // Cycles - PP/P
1341 
      {CONT, 16'b0010010?????????} :
1342 
         begin
1343 
           if (!zero_flag)
1344 
             begin
1345 5 rehayes 
               next_cpu_state = S_STALL;
1346 2 rehayes 
               load_next_inst = 1'b0;
1347 40 rehayes 
               pc_incr_mux    = jump_offset;
1348 
               next_pc        = pc_sum;
1349 2 rehayes 
             end
1350 
         end
1351 
 
1352 
      // Instruction = BEQ REL9, Op Code =  0 0 1 0 0 1 1 REL9
1353 
      // Branch if Equal
1354 
      // If Z = 1, then PC + $0002 + (REL9 << 1) => PC
1355 
      // Cycles - PP/P
1356 
      {CONT, 16'b0010011?????????} :
1357 
         begin
1358 
           if (zero_flag)
1359 
             begin
1360 5 rehayes 
               next_cpu_state = S_STALL;
1361 2 rehayes 
               load_next_inst = 1'b0;
1362 40 rehayes 
               pc_incr_mux    = jump_offset;
1363 
               next_pc        = pc_sum;
1364 2 rehayes 
             end
1365 
         end
1366 
 
1367 
      // Instruction = BPL REL9, Op Code =  0 0 1 0 1 0 0 REL9
1368 
      // Branch if Plus
1369 
      // If N = 0, then PC + $0002 + (REL9 << 1) => PC
1370 
      // Cycles - PP/P
1371 
      {CONT, 16'b0010100?????????} :
1372 
         begin
1373 
           if (!negative_flag)
1374 
             begin
1375 5 rehayes 
               next_cpu_state = S_STALL;
1376 2 rehayes 
               load_next_inst = 1'b0;
1377 40 rehayes 
               pc_incr_mux    = jump_offset;
1378 
               next_pc        = pc_sum;
1379 2 rehayes 
             end
1380 
         end
1381 
 
1382 
      // Instruction = BMI REL9, Op Code =  0 0 1 0 1 0 1 REL9
1383 
      // Branch if Minus
1384 
      // If N = 1, then PC + $0002 + (REL9 << 1) => PC
1385 
      // Cycles - PP/P
1386 
      {CONT, 16'b0010101?????????} :
1387 
         begin
1388 
           if (negative_flag)
1389 
             begin
1390 5 rehayes 
               next_cpu_state = S_STALL;
1391 2 rehayes 
               load_next_inst = 1'b0;
1392 40 rehayes 
               pc_incr_mux    = jump_offset;
1393 
               next_pc        = pc_sum;
1394 2 rehayes 
             end
1395 
         end
1396 
 
1397 
      // Instruction = BVC REL9, Op Code =  0 0 1 0 1 1 0 REL9
1398 
      // Branch if Overflow Cleared
1399 
      // If V = 0, then PC + $0002 + (REL9 << 1) => PC
1400 
      // Cycles - PP/P
1401 
      {CONT, 16'b0010110?????????} :
1402 
         begin
1403 
           if (!overflow_flag)
1404 
             begin
1405 5 rehayes 
               next_cpu_state = S_STALL;
1406 2 rehayes 
               load_next_inst = 1'b0;
1407 40 rehayes 
               pc_incr_mux    = jump_offset;
1408 
               next_pc        = pc_sum;
1409 2 rehayes 
             end
1410 
         end
1411 
 
1412 
      // Instruction = BVS REL9, Op Code =  0 0 1 0 1 1 1 REL9
1413 
      // Branch if Overflow Set
1414 
      // If V = 1, then PC + $0002 + (REL9 << 1) => PC
1415 
      // Cycles - PP/P
1416 
      {CONT, 16'b0010111?????????} :
1417 
         begin
1418 
           if (overflow_flag)
1419 
             begin
1420 5 rehayes 
               next_cpu_state = S_STALL;
1421 2 rehayes 
               load_next_inst = 1'b0;
1422 40 rehayes 
               pc_incr_mux    = jump_offset;
1423 
               next_pc        = pc_sum;
1424 2 rehayes 
             end
1425 
         end
1426 
 
1427 
      // Instruction = BHI REL9, Op Code =  0 0 1 1 0 0 0 REL9
1428 
      // Branch if Higher
1429 
      // If C | Z = 0, then PC + $0002 + (REL9 << 1) => PC
1430 
      // Cycles - PP/P
1431 
      {CONT, 16'b0011000?????????} :
1432 
         begin
1433 
           if (!(carry_flag || zero_flag))
1434 
             begin
1435 5 rehayes 
               next_cpu_state = S_STALL;
1436 2 rehayes 
               load_next_inst = 1'b0;
1437 40 rehayes 
               pc_incr_mux    = jump_offset;
1438 
               next_pc        = pc_sum;
1439 2 rehayes 
             end
1440 
         end
1441 
 
1442 
      // Instruction = BLS REL9, Op Code =  0 0 1 1 0 0 1 REL9
1443 
      // Branch if Lower or Same
1444 
      // If C | Z = 1, then PC + $0002 + (REL9 << 1) => PC
1445 
      // Cycles - PP/P
1446 
      {CONT, 16'b0011001?????????} :
1447 
         begin
1448 
           if (carry_flag || zero_flag)
1449 
             begin
1450 5 rehayes 
               next_cpu_state = S_STALL;
1451 2 rehayes 
               load_next_inst = 1'b0;
1452 40 rehayes 
               pc_incr_mux    = jump_offset;
1453 
               next_pc        = pc_sum;
1454 2 rehayes 
             end
1455 
         end
1456 
 
1457 
      // Instruction = BGE REL9, Op Code =  0 0 1 1 0 1 0 REL9
1458 
      // Branch if Greater than or Equal to Zero
1459 
      // If N ^ V = 0, then PC + $0002 + (REL9 << 1) => PC
1460 
      // Cycles - PP/P
1461 
      {CONT, 16'b0011010?????????} :
1462 
         begin
1463 
           if (!(negative_flag ^ overflow_flag))
1464 
             begin
1465 5 rehayes 
               next_cpu_state = S_STALL;
1466 2 rehayes 
               load_next_inst = 1'b0;
1467 40 rehayes 
               pc_incr_mux    = jump_offset;
1468 
               next_pc        = pc_sum;
1469 2 rehayes 
             end
1470 
         end
1471 
 
1472 
      // Instruction = BLT REL9, Op Code =  0 0 1 1 0 1 1 REL9
1473 
      // Branch if Lower than Zero
1474 
      // If N ^ V = 1, then PC + $0002 + (REL9 << 1) => PC
1475 
      // Cycles - PP/P
1476 
      {CONT, 16'b0011011?????????} :
1477 
         begin
1478 
           if (negative_flag ^ overflow_flag)
1479 
             begin
1480 5 rehayes 
               next_cpu_state = S_STALL;
1481 2 rehayes 
               load_next_inst = 1'b0;
1482 40 rehayes 
               pc_incr_mux    = jump_offset;
1483 
               next_pc        = pc_sum;
1484 2 rehayes 
             end
1485 
         end
1486 
 
1487 
      // Instruction = BGT REL9, Op Code =  0 0 1 1 1 0 0 REL9
1488 
      // Branch if Greater than Zero
1489 
      // If Z | (N ^ V) = 0, then PC + $0002 + (REL9 << 1) => PC
1490 
      // Cycles - PP/P
1491 
      {CONT, 16'b0011100?????????} :
1492 
         begin
1493 
           if (!(zero_flag || (negative_flag ^ overflow_flag)))
1494 
             begin
1495 5 rehayes 
               next_cpu_state = S_STALL;
1496 2 rehayes 
               load_next_inst = 1'b0;
1497 40 rehayes 
               pc_incr_mux    = jump_offset;
1498 
               next_pc        = pc_sum;
1499 2 rehayes 
             end
1500 
         end
1501 
 
1502 
      // Instruction = BLE REL9, Op Code =  0 0 1 1 1 0 1 REL9
1503 
      // Branch if Less or Equal to Zero
1504 
      // If Z | (N ^ V) = 1, then PC + $0002 + (REL9 << 1) => PC
1505 
      // Cycles - PP/P
1506 
      {CONT, 16'b0011101?????????} :
1507 
         begin
1508 
           if (zero_flag || (negative_flag ^ overflow_flag))
1509 
             begin
1510 5 rehayes 
               next_cpu_state = S_STALL;
1511 2 rehayes 
               load_next_inst = 1'b0;
1512 40 rehayes 
               pc_incr_mux    = jump_offset;
1513 
               next_pc        = pc_sum;
1514 2 rehayes 
             end
1515 
         end
1516 
 
1517 
      // Instruction = BRA REL10, Op Code =  0 0 1 1 1 1 REL10
1518 
      // Branch Always, signed offset
1519 
      // PC + $0002 + (REL10 << 1) => PC
1520 
      // Cycles - PP
1521 
      {CONT, 16'b001111??????????} :
1522 
         begin
1523 5 rehayes 
           next_cpu_state = S_STALL;
1524 2 rehayes 
           load_next_inst = 1'b0;
1525 40 rehayes 
           pc_incr_mux    = bra_offset;
1526 
           next_pc        = pc_sum;
1527 2 rehayes 
         end
1528 
 
1529 
 
1530 
      // -----------------------------------------------------------------------
1531 
      // Instruction Group -- Load and Store Instructions
1532 
      // -----------------------------------------------------------------------
1533 
 
1534 
      // Instruction = LDB RD, (RB, #OFFS5), Op Code =  0 1 0 0 0 RD RB OFFS5
1535 
      // Load Byte from Memory, unsigned offset
1536 
      // M[RB, #OFFS5] => RD.L; $00 => RD.H
1537 
      // RB field == RS1 field
1538 
      // Cycles - Pr
1539 
      {CONT, 16'b01000???????????} :
1540 
         begin
1541 40 rehayes 
           next_cpu_state = B_LOAD;
1542 2 rehayes 
           load_next_inst = 1'b0;
1543 40 rehayes 
           pc_incr_mux    = 16'h0000;
1544 
           next_pc        = pc_sum;
1545 2 rehayes 
           data_access    = 1'b1;
1546 
           data_address   = rs1_data + {11'b0, op_code[4:0]};
1547 
         end
1548 
 
1549 
      // Instruction = LDW RD, (RB, #OFFS5), Op Code =  0 1 0 0 1 RD RB OFFS5
1550 
      // Load Word from Memory, unsigned offset
1551 
      // M[RB, #OFFS5] => RD
1552 
      // RB field == RS1 field
1553 
      // Cycles - PR
1554 
      {CONT, 16'b01001???????????} :
1555 
         begin
1556 40 rehayes 
           next_cpu_state = W_LOAD;
1557 2 rehayes 
           load_next_inst = 1'b0;
1558 40 rehayes 
           pc_incr_mux    = 16'h0000;
1559 
           next_pc        = pc_sum;
1560 2 rehayes 
           data_access    = 1'b1;
1561 
           data_address   = rs1_data + {11'b0, op_code[4:0]};
1562 
           data_word_op   = 1'b1;
1563 
         end
1564 
 
1565 
      // Instruction = STB RS, (RB, #OFFS5), Op Code =  0 1 0 1 0 RS RB OFFS5
1566 
      // Store Byte to Memory, unsigned offset
1567 
      // RS.L => M[RB, #OFFS5]
1568 
      // RS field == RD fieild, RB field == RS1 field
1569 
      // Cycles - Pw
1570 
      {CONT, 16'b01010???????????} :
1571 
         begin
1572 5 rehayes 
           next_cpu_state = S_STALL;
1573 2 rehayes 
           load_next_inst = 1'b0;
1574 40 rehayes 
           pc_incr_mux    = 16'h0000;
1575 
           next_pc        = pc_sum;
1576 2 rehayes 
           data_access    = 1'b1;
1577 
           data_write     = 1'b1;
1578 
           data_address   = rs1_data + {11'b0, op_code[4:0]};
1579 
         end
1580 
 
1581 
      // Instruction = STW RS, (RB, #OFFS5), Op Code =  0 1 0 1 1 RS RB OFFS5
1582 
      // Store Word to Memory, unsigned offset
1583 
      // RS => M[RB, #OFFS5]
1584 
      // RS field == RD fieild, RB field == RS1 field
1585 
      // Cycles - PW
1586 
      {CONT, 16'b01011???????????} :
1587 
         begin
1588 5 rehayes 
           next_cpu_state = S_STALL;
1589 2 rehayes 
           load_next_inst = 1'b0;
1590 40 rehayes 
           pc_incr_mux    = 16'h0000;
1591 
           next_pc        = pc_sum;
1592 2 rehayes 
           data_access    = 1'b1;
1593 
           data_write     = 1'b1;
1594 
           data_address   = rs1_data + {11'b0, op_code[4:0]};
1595 
           data_word_op   = 1'b1;
1596 
         end
1597 
 
1598 
      // Instruction = LDB RD, (RB, RI), Op Code =  0 1 1 0 0 RD RB RI 0 0
1599 
      // Load Byte from Memory
1600 
      // M[RB, RI] => RD.L; $00 => RD.H
1601 
      // RB field == RS1 field, RI field == RS2 field
1602 
      // Cycles - Pr
1603 
      {CONT, 16'b01100?????????00} :
1604 
         begin
1605 40 rehayes 
           next_cpu_state = B_LOAD;
1606 2 rehayes 
           load_next_inst = 1'b0;
1607 40 rehayes 
           pc_incr_mux    = 16'h0000;
1608 
           next_pc        = pc_sum;
1609 2 rehayes 
           data_access    = 1'b1;
1610 
           data_address   = rs1_data + rs2_data;
1611 
         end
1612 
 
1613 
      // Instruction = LDW RD, (RB, RI), Op Code =  0 1 1 0 1 RD RB RI 0 0
1614 
      // Load Word from Memory
1615 
      // M[RB, RI] => RD
1616 
      // RB field == RS1 field, RI field == RS2 field
1617 
      // Cycles - PR
1618 
      {CONT, 16'b01101?????????00} :
1619 
         begin
1620 40 rehayes 
           next_cpu_state = W_LOAD;
1621 2 rehayes 
           load_next_inst = 1'b0;
1622 40 rehayes 
           pc_incr_mux    = 16'h0000;
1623 
           next_pc        = pc_sum;
1624 2 rehayes 
           data_access    = 1'b1;
1625 
           data_address   = rs1_data + rs2_data;
1626 
           data_word_op   = 1'b1;
1627 
         end
1628 
 
1629 
      // Instruction = STB RS, (RB, RI), Op Code =  0 1 1 1 0 RS RB RI 0 0
1630 
      // RS.L => M[RB, RI]
1631 
      // Store Byte to Memory
1632 
      // RS field == RD fieild, RB field == RS1 field, RI field == RS2 field
1633 
      // Cycles - Pw
1634 
      {CONT, 16'b01110?????????00} :
1635 
         begin
1636 5 rehayes 
           next_cpu_state = S_STALL;
1637 2 rehayes 
           load_next_inst = 1'b0;
1638 40 rehayes 
           pc_incr_mux    = 16'h0000;
1639 
           next_pc        = pc_sum;
1640 2 rehayes 
           data_access    = 1'b1;
1641 
           data_write     = 1'b1;
1642 
           data_address   = rs1_data + rs2_data;
1643 
         end
1644 
 
1645 
      // Instruction = STW RS, (RB, RI), Op Code =  0 1 1 1 1 RS RB RI 0 0
1646 
      // Store Word to Memory
1647 
      // RS => M[RB, RI]
1648 
      // RS field == RD fieild, RB field == RS1 field, RI field == RS2 field
1649 
      // Cycles - PW
1650 
      {CONT, 16'b01111?????????00} :
1651 
         begin
1652 5 rehayes 
           next_cpu_state = S_STALL;
1653 2 rehayes 
           load_next_inst = 1'b0;
1654 40 rehayes 
           pc_incr_mux    = 16'h0000;
1655 
           next_pc        = pc_sum;
1656 2 rehayes 
           data_access    = 1'b1;
1657 
           data_write     = 1'b1;
1658 
           data_address   = rs1_data + rs2_data;
1659 
           data_word_op   = 1'b1;
1660 
         end
1661 
 
1662 
      // Instruction = LDB RD, (RB, RI+), Op Code =  0 1 1 0 0 RD RB RI 0 1
1663 
      // Load Byte from Memory
1664 
      // M[RB, RI] => RD.L; $00 => RD.H; RI+1 => RI
1665 
      //  If the same general purpose register is used as index (RI) and destination register (RD),
1666 
      //  the content of the register will not be incremented after the data move: M[RB, RI] => RD.L; $00 => RD.H
1667 
      // RB field == RS1 field, RI field == RS2 field
1668 
      // Cycles - Pr
1669 
      {CONT, 16'b01100?????????01} :
1670 
         begin
1671 40 rehayes 
           next_cpu_state   = B_LOAD;
1672 2 rehayes 
           load_next_inst   = 1'b0;
1673 40 rehayes 
           pc_incr_mux      = 16'h0000;
1674 
           next_pc          = pc_sum;
1675 2 rehayes 
           data_access      = 1'b1;
1676 
           data_address     = rs1_data + rs2_data;
1677 
           alu_result       = rs2_data + 16'h0001;
1678 12 rehayes 
           sel_rd_field     = 1'b0;
1679 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1680 
           ena_rd_high_byte = 1'b1;
1681 
         end
1682 
 
1683 
      // Instruction = LDW RD, (RB, RI+), Op Code =  0 1 1 0 1 RD RB RI 0 1
1684 
      // Load Word from Memory
1685 
      // M[RB, RI] => RD; RI+2 => RI
1686 
      //  If the same general purpose register is used as index (RI) and destination register (RD),
1687 
      //  the content of the register will not be incremented after the data move: M[RB, RI] => RD
1688 
      // RB field == RS1 field, RI field == RS2 field
1689 
      // Cycles - PR
1690 
      {CONT, 16'b01101?????????01} :
1691 
         begin
1692 40 rehayes 
           next_cpu_state   = W_LOAD;
1693 2 rehayes 
           load_next_inst   = 1'b0;
1694 40 rehayes 
           pc_incr_mux      = 16'h0000;
1695 
           next_pc          = pc_sum;
1696 2 rehayes 
           data_access      = 1'b1;
1697 
           data_address     = rs1_data + rs2_data;
1698 
           data_word_op     = 1'b1;
1699 
           alu_result       = rs2_data + 16'h0002;
1700 12 rehayes 
           sel_rd_field     = 1'b0;
1701 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1702 
           ena_rd_high_byte = 1'b1;
1703 
         end
1704 
 
1705 
      // Instruction = STB RS, (RB, RI+), Op Code =  0 1 1 1 0 RS RB RI 0 1
1706 
      // Store Byte to Memory
1707 
      // RS.L => M[RB, RI]; RI+1 => RI
1708 
      // RS field == RD fieild, RB field == RS1 field, RI field == RS2 field
1709 
      // Cycles - Pw
1710 
      {CONT, 16'b01110?????????01} :
1711 
         begin
1712 5 rehayes 
           next_cpu_state   = S_STALL;
1713 2 rehayes 
           load_next_inst   = 1'b0;
1714 40 rehayes 
           pc_incr_mux      = 16'h0000;
1715 
           next_pc          = pc_sum;
1716 2 rehayes 
           data_access      = 1'b1;
1717 
           data_write       = 1'b1;
1718 
           data_address     = rs1_data + rs2_data;
1719 
           alu_result       = rs2_data + 16'h0001;
1720 12 rehayes 
           sel_rd_field     = 1'b0;
1721 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1722 
           ena_rd_high_byte = 1'b1;
1723 
         end
1724 
 
1725 
      // Instruction = STW RS, (RB, RI+), Op Code =  0 1 1 1 1 RS RB RI 0 1
1726 
      // Store Word to Memory
1727 
      // RS => M[RB, RI]; RI+2 => RI
1728 
      // RS field == RD fieild, RB field == RS1 field, RI field == RS2 field
1729 
      // Cycles - PW
1730 
      {CONT, 16'b01111?????????01} :
1731 
         begin
1732 5 rehayes 
           next_cpu_state   = S_STALL;
1733 2 rehayes 
           load_next_inst   = 1'b0;
1734 40 rehayes 
           pc_incr_mux      = 16'h0000;
1735 
           next_pc          = pc_sum;
1736 2 rehayes 
           data_access      = 1'b1;
1737 
           data_write       = 1'b1;
1738 
           data_word_op     = 1'b1;
1739 
           data_address     = rs1_data + rs2_data;
1740 
           alu_result       = rs2_data + 16'h0002;
1741 12 rehayes 
           sel_rd_field     = 1'b0;
1742 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1743 
           ena_rd_high_byte = 1'b1;
1744 
         end
1745 
 
1746 
      // Instruction = LDB RD, (RB, -RI), Op Code =  0 1 1 0 0 RD RB RI 1 0
1747 
      // Load Byte from Memory
1748 
      // RI-1 => RI; M[RS, RI]  => RD.L; $00 => RD.H
1749 
      // RB field == RS1 field, RI field == RS2 field
1750 
      // Cycles - Pr
1751 
      {CONT, 16'b01100?????????10} :
1752 
         begin
1753 40 rehayes 
           next_cpu_state   = B_LOAD;
1754 2 rehayes 
           load_next_inst   = 1'b0;
1755 40 rehayes 
           pc_incr_mux      = 16'h0000;
1756 
           next_pc          = pc_sum;
1757 2 rehayes 
           data_access      = 1'b1;
1758 
           alu_result       = rs2_data + 16'hffff;
1759 
           data_address     = rs1_data + alu_result;
1760 12 rehayes 
           sel_rd_field     = 1'b0;
1761 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1762 
           ena_rd_high_byte = 1'b1;
1763 
         end
1764 
 
1765 
      // Instruction = LDW RD, (RB, -RI), Op Code =  0 1 1 0 1 RD RB RI 1 0
1766 
      // Load Word from Memory
1767 
      // RI-2 => RI; M[RS, RI] => RD
1768 
      // RB field == RS1 field, RI field == RS2 field
1769 
      // Cycles - PR
1770 
      {CONT, 16'b01101?????????10} :
1771 
         begin
1772 40 rehayes 
           next_cpu_state   = W_LOAD;
1773 2 rehayes 
           load_next_inst   = 1'b0;
1774 40 rehayes 
           pc_incr_mux      = 16'h0000;
1775 
           next_pc          = pc_sum;
1776 2 rehayes 
           data_access      = 1'b1;
1777 
           alu_result       = rs2_data + 16'hfffe;
1778 
           data_address     = rs1_data + alu_result;
1779 
           data_word_op     = 1'b1;
1780 12 rehayes 
           sel_rd_field     = 1'b0;
1781 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1782 
           ena_rd_high_byte = 1'b1;
1783 
         end
1784 
 
1785 
      // Instruction = STB RS, (RB, -RI), Op Code =  0 1 1 1 0 RS RB RI 1 0
1786 
      // Store Byte to Memory
1787 
      // RI-1 => RI; RS.L => M[RB, RI]
1788 
      //  If the same general purpose register is used as index (RI) and source register (RS),
1789 
      //  the unmodified content of the source register is written to the memory: RS.L => M[RB, RS-1]; RS-1 => RS
1790 
      // RS field == RD fieild, RB field == RS1 field, RI field == RS2 field
1791 
      // Cycles - Pw
1792 
      {CONT, 16'b01110?????????10} :
1793 
         begin
1794 5 rehayes 
           next_cpu_state   = S_STALL;
1795 2 rehayes 
           load_next_inst   = 1'b0;
1796 40 rehayes 
           pc_incr_mux      = 16'h0000;
1797 
           next_pc          = pc_sum;
1798 2 rehayes 
           data_access      = 1'b1;
1799 
           data_write       = 1'b1;
1800 
           alu_result       = rs2_data + 16'hffff;
1801 
           data_address     = rs1_data + alu_result;
1802 12 rehayes 
           sel_rd_field     = 1'b0;
1803 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1804 
           ena_rd_high_byte = 1'b1;
1805 
         end
1806 
 
1807 
      // Instruction = STW RS, (RB, -RI), Op Code =  0 1 1 1 1 RS RB RI 1 0
1808 
      // Store Word to Memory
1809 
      // RI-2 => RI; RS => M[RB, RI]
1810 
      //  If the same general purpose register is used as index (RI) and source register (RS),
1811 
      //  the unmodified content of the source register is written to the memory: RS => M[RB, RS-2]; RS-2 => RS
1812 
      // RS field == RD fieild, RB field == RS1 field, RI field == RS2 field
1813 
      // Cycles - PW
1814 
      {CONT, 16'b01111?????????10} :
1815 
         begin
1816 5 rehayes 
           next_cpu_state   = S_STALL;
1817 2 rehayes 
           load_next_inst   = 1'b0;
1818 40 rehayes 
           pc_incr_mux      = 16'h0000;
1819 
           next_pc          = pc_sum;
1820 2 rehayes 
           data_access      = 1'b1;
1821 
           data_write       = 1'b1;
1822 
           data_word_op     = 1'b1;
1823 
           alu_result       = rs2_data + 16'hfffe;
1824 
           data_address     = rs1_data + alu_result;
1825 12 rehayes 
           sel_rd_field     = 1'b0;
1826 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1827 
           ena_rd_high_byte = 1'b1;
1828 
         end
1829 
 
1830 
      // -----------------------------------------------------------------------
1831 
      // Instruction Group -- Bit Field Instructions
1832 
      // -----------------------------------------------------------------------
1833 
 
1834 
      // Instruction = BFEXT RD, RS1, RS2, Op Code =  0 1 1 0 0 RD RS1 RS2 1 1
1835 
      // BFEXT - Bit Field Extract
1836 
      // RS1[(o+w):o] => RD[w:0]; 0 => RD[15:(w+1)]
1837 
      // Cycles - P
1838 
      {CONT, 16'b01100?????????11} :
1839 
         begin
1840 5 rehayes 
           ena_rd_low_byte  = 1'b1;
1841 2 rehayes 
           ena_rd_high_byte = 1'b1;
1842 
           shift_ammount  = {1'b0, rs2_data[3:0]};
1843 
           for (bfi = 0; bfi <= 15; bfi = bfi + 1)
1844 
             shift_in[bfi] = bf_mux_mask[bfi] ? rs1_data[bfi] : 1'b0;
1845 
 
1846 
           alu_result    = shift_out;
1847 
           next_zero     = !(|alu_result);
1848 
           next_negative = alu_result[15];
1849 
           next_overflow = 1'b0;
1850 
         end
1851 
 
1852 
      // Instruction = BFINS RD, RS1, RS2, Op Code =  0 1 1 0 1 RD RS1 RS2 1 1
1853 
      // BFINS - Bit Field Insert
1854 
      // RS1[w:0] => RD[(w+o):o
1855 
      // Cycles - P
1856 
      {CONT, 16'b01101?????????11} :
1857 
         begin
1858 
           ena_rd_low_byte  = 1'b1;
1859 
           ena_rd_high_byte = 1'b1;
1860 
           shift_left     = 1'b1;
1861 
           shift_ammount  = {1'b0, rs2_data[3:0]};
1862 
           shift_in       = rs1_data;
1863 
 
1864 
           for (bfi = 0; bfi <= 15; bfi = bfi + 1)
1865 
             alu_result[bfi] = bf_mux_mask[bfi] ? shift_out[bfi] : rd_data[bfi];
1866 
           next_zero     = !(|alu_result);
1867 
           next_negative = alu_result[15];
1868 
           next_overflow = 1'b0;
1869 
         end
1870 
 
1871 
      // Instruction = BFINSI RD, RS1, RS2, Op Code =  0 1 1 1 0 RD RS1 RS2 1 1
1872 
      // BFINSI - Bit Field Insert and Invert
1873 
      // !RS1[w:0] => RD[w+o:o]
1874 
      // Cycles - P
1875 
      {CONT, 16'b01110?????????11} :
1876 
         begin
1877 
           ena_rd_low_byte  = 1'b1;
1878 
           ena_rd_high_byte = 1'b1;
1879 
           shift_left     = 1'b1;
1880 
           shift_ammount  = {1'b0, rs2_data[3:0]};
1881 
           shift_in       = rs1_data;
1882 
 
1883 
           for (bfi = 0; bfi <= 15; bfi = bfi + 1)
1884 
             alu_result[bfi] = bf_mux_mask[bfi] ? !shift_out[bfi] : rd_data[bfi];
1885 
           next_zero     = !(|alu_result);
1886 
           next_negative = alu_result[15];
1887 
           next_overflow = 1'b0;
1888 
         end
1889 
 
1890 
      // Instruction = BFINSX RD, RS1, RS2, Op Code =  0 1 1 1 1 RD RS1 RS2 1 1
1891 
      // BFINSX - Bit Field Insert and XNOR
1892 
      // !(RS1[w:0] ^ RD[w+o:o]) => RD[w+o:o]
1893 
      // Cycles - P
1894 
      {CONT, 16'b01111?????????11} :
1895 
         begin
1896 
           ena_rd_low_byte  = 1'b1;
1897 
           ena_rd_high_byte = 1'b1;
1898 
           shift_left     = 1'b1;
1899 
           shift_ammount  = {1'b0, rs2_data[3:0]};
1900 
           shift_in       = rs1_data;
1901 
 
1902 26 rehayes 
           for (bfii = 0; bfii <= 15; bfii = bfii + 1)
1903 
             alu_result[bfii] = bf_mux_mask[bfii] ? !(shift_out[bfii] ^ rd_data[bfii]) : rd_data[bfii];
1904 2 rehayes 
           next_zero     = !(|alu_result);
1905 
           next_negative = alu_result[15];
1906 
           next_overflow = 1'b0;
1907 
        end
1908 
 
1909 
      // -----------------------------------------------------------------------
1910 
      // Instruction Group -- Logic Immediate Instructions
1911 
      // -----------------------------------------------------------------------
1912 
 
1913 
      // Instruction = ANDL RD, #IMM8, Op Code =  1 0 0 0 0 RD IMM8
1914 
      // AND - Logical AND
1915 
      // RD.L & IMM8 => RD.L
1916 
      // Cycles - P
1917 
      {CONT, 16'b10000???????????} :
1918 
         begin
1919 
           ena_rd_low_byte = 1'b1;
1920 
 
1921 
           alu_result    = rd_data & {8'b0, op_code[7:0]};
1922 
           next_zero     = !(|alu_result[7:0]);
1923 
           next_negative = alu_result[7];
1924 
           next_overflow = 1'b0;
1925 
         end
1926 
 
1927 
      // Instruction = ANDH RD, #IMM8, Op Code =  1 0 0 0 1 RD IMM8
1928 
      // AND - Logical AND
1929 
      // RD.H & IMM8 => RD.H
1930 
      // Cycles - P
1931 
      {CONT, 16'b10001???????????} :
1932 
         begin
1933 
           ena_rd_high_byte = 1'b1;
1934 
 
1935 
           alu_result    = rd_data & {op_code[7:0], 8'b0};
1936 
           next_zero     = !(|alu_result[15:8]);
1937 
           next_negative = alu_result[15];
1938 
           next_overflow = 1'b0;
1939 
         end
1940 
 
1941 
      // Instruction = BITL RD, #IMM8, Op Code =  1 0 0 1 0 RD IMM8
1942 
      // RD.L & IMM8 => NONE
1943 
      {CONT, 16'b10010???????????} :
1944 
         begin
1945 
 
1946 
           next_zero     = !(|(rd_data[7:0] & op_code[7:0]));
1947 
           next_negative = rd_data[7] && op_code[7];
1948 
           next_overflow = 1'b0;
1949 
         end
1950 
 
1951 
      // Instruction = BITH RD, #IMM8, Op Code =  1 0 0 1 1 RD IMM8
1952 
      // RD.H & IMM8 => NONE
1953 
      {CONT, 16'b10011???????????} :
1954 
         begin
1955 
 
1956 
           next_zero     = !(|(rd_data[15:8] & op_code[7:0]));
1957 
           next_negative = rd_data[15] && op_code[7];
1958 
           next_overflow = 1'b0;
1959 
         end
1960 
 
1961 
      // Instruction = ORL RD, #IMM8, Op Code =  1 0 1 0 0 RD IMM8
1962 
      // OR - Logical OR
1963 
      // RD.L | IMM8 => RD.L
1964 
      {CONT, 16'b10100???????????} :
1965 
         begin
1966 
           ena_rd_low_byte = 1'b1;
1967 
 
1968 
           alu_result    = rd_data | {8'b0, op_code[7:0]};
1969 
           next_zero     = !(|alu_result[7:0]);
1970 
           next_negative = alu_result[7];
1971 
           next_overflow = 1'b0;
1972 
         end
1973 
 
1974 
      // Instruction = ORH RD, #IMM8, Op Code =  1 0 1 0 1 RD IMM8
1975 
      // OR - Logical OR
1976 
      // RD.H | IMM8 => RD.H
1977 
      {CONT, 16'b10101???????????} :
1978 
         begin
1979 
           ena_rd_high_byte = 1'b1;
1980 
 
1981 
           alu_result    = rd_data | {op_code[7:0], 8'b0};
1982 
           next_zero     = !(|alu_result[15:8]);
1983 
           next_negative = alu_result[15];
1984 
           next_overflow = 1'b0;
1985 
         end
1986 
 
1987 
      // Instruction = XNORL RD, #IMM8, Op Code =  1 0 1 1 0 RD IMM8
1988 
      // XNOR - Logical Exclusive NOR
1989 
      // ~(RD.L ^ IMM8) => RD.L
1990 
      {CONT, 16'b10110???????????} :
1991 
         begin
1992 
           ena_rd_low_byte = 1'b1;
1993 
 
1994 
           alu_result    = ~(rd_data ^ {8'b0, op_code[7:0]});
1995 
           next_zero     = !(|alu_result[7:0]);
1996 
           next_negative = alu_result[7];
1997 
           next_overflow = 1'b0;
1998 
         end
1999 
 
2000 
      // Instruction = XNORH RD, #IMM8, Op Code =  1 0 1 1 1 RD IMM8
2001 
      // XNOR - Logical Exclusive NOR
2002 
      // ~(RD.H ^ IMM8) => RD.H
2003 
      {CONT, 16'b10111???????????} :
2004 
         begin
2005 
           ena_rd_high_byte = 1'b1;
2006 
 
2007 
           alu_result    = ~(rd_data ^ {op_code[7:0], 8'b0});
2008 
           next_zero     = !(|alu_result[15:8]);
2009 
           next_negative = alu_result[15];
2010 
           next_overflow = 1'b0;
2011 
         end
2012 
 
2013 
      // -----------------------------------------------------------------------
2014 
      // Instruction Group -- Arithmetic Immediate Instructions
2015 
      // -----------------------------------------------------------------------
2016 
 
2017 
      // Instruction = SUBL RD, #IMM8, Op Code =  1 1 0 0 0 RD IMM8
2018 
      // SUB - Subtract without Carry
2019 
      // RD - $00:IMM8 => RD
2020 
      // Cycles - P
2021 
      {CONT, 16'b11000???????????} :
2022 
         begin
2023 
           ena_rd_low_byte  = 1'b1;
2024 
           ena_rd_high_byte = 1'b1;
2025 
 
2026 
           alu_result    = rd_data - {8'b0, op_code[7:0]};
2027 
           next_zero     = !(|alu_result);
2028 
           next_negative = alu_result[15];
2029 
           next_carry    = (!rd_data[7] && op_code[7]) || (!rd_data[7] && alu_result[7]) || (op_code[7] && alu_result[7]);
2030 
           next_overflow = (rd_data[7] && !op_code[7] && !alu_result[7]) || (!rd_data[7] && op_code[7] && alu_result[7]);
2031 
         end
2032 
 
2033 
      // Instruction = SUBH RD, #IMM8, Op Code =  1 1 0 0 1 RD IMM8
2034 
      // SUB - Subtract without Carry
2035 
      // RD - IMM8:$00 => RD
2036 
      // Cycles - P
2037 
      {CONT, 16'b11001???????????} :
2038 
         begin
2039 
           ena_rd_low_byte  = 1'b1;
2040 
           ena_rd_high_byte = 1'b1;
2041 
 
2042 
           {next_carry, alu_result} = rd_data - {op_code[7:0], 8'b0};
2043 
           next_zero     = !(|alu_result);
2044 
           next_negative = alu_result[15];
2045 
           next_overflow = (rd_data[15] && !op_code[7] && !alu_result[15]) || (!rd_data[15] && op_code[7] && alu_result[15]);
2046 
         end
2047 
 
2048 
      // Instruction = CMPL RS, #IMM8, Op Code =  1 1 0 1 0 RS IMM8
2049 
      // RS.L - IMM8 => NONE, only condition code flags get updated
2050 
      // RS field == RD field
2051 
      // Cycles - P
2052 
      {CONT, 16'b11010???????????} :
2053 
         begin
2054 
 
2055 
           alu_result    = {8'b0, rd_data[7:0] - op_code[7:0]};
2056 
           next_zero     = !(|alu_result[7:0]);
2057 
           next_negative = alu_result[7];
2058 
           next_carry    = (!rd_data[7] && op_code[7]) || (!rd_data[7] && alu_result[7]) || (op_code[7] && alu_result[7]);
2059 
           next_overflow = (rd_data[7] && !op_code[7] && !alu_result[7]) || (!rd_data[7] && op_code[7] && alu_result[7]);
2060 
         end
2061 
 
2062 
      // Instruction = CPCH RS, #IMM8, Op Code =  1 1 0 1 1 RS IMM8
2063 
      // RS.H - IMM8 - C => NONE, only condition code flags get updated
2064 
      // RS field == RD field
2065 
      // Cycles - P
2066 
      {CONT, 16'b11011???????????} :
2067 
         begin
2068 
 
2069 
           alu_result    = {rd_data[15:8], 8'b0} - {op_code[7:0], 8'b0} - {7'b0, carry_flag, 8'b0};
2070 
           next_zero     = !(|alu_result[15:8]) && zero_flag;
2071 
           next_negative = alu_result[15];
2072 
           next_carry    = (!rd_data[15] && op_code[7]) || (!rd_data[15] && alu_result[15]) || (op_code[7] && alu_result[15]);
2073 
           next_overflow = (rd_data[15] && !op_code[7] && !alu_result[15]) || (!rd_data[15] && op_code[7] && alu_result[15]);
2074 
         end
2075 
 
2076 
      // Instruction = ADDL RD, #IMM8, Op Code =  1 1 1 0 0 RD IMM8
2077 
      // ADD - ADD without carry
2078 
      // RD + $00:IMM8 => RD
2079 
      // Cycles - P
2080 
      {CONT, 16'b11100???????????} :
2081 
         begin
2082 
           ena_rd_low_byte  = 1'b1;
2083 
           ena_rd_high_byte = 1'b1;
2084 
 
2085 
           alu_result    = rd_data + {8'b0, op_code[7:0]};
2086 
           next_zero     = !(|alu_result);
2087 
           next_negative = alu_result[15];
2088 
           next_carry    = (rd_data[7] && op_code[7]) || (rd_data[7] && !alu_result[7]) || (op_code[7] && !alu_result[7]);
2089 
           next_overflow = (!rd_data[7] && !op_code[7] && alu_result[7]) || (rd_data[7] && op_code[7] && !alu_result[7]);
2090 
         end
2091 
 
2092 
      // Instruction = ADDH RD, #IMM8, Op Code =  1 1 1 0 1 RD IMM8
2093 
      // ADD - ADD without carry
2094 
      // RD + IMM8:$00 => RD
2095 
      // Cycles - P
2096 
      {CONT, 16'b11101???????????} :
2097 
         begin
2098 
           ena_rd_low_byte  = 1'b1;
2099 
           ena_rd_high_byte = 1'b1;
2100 
 
2101 
           {next_carry, alu_result} = rd_data + {op_code[7:0], 8'b0};
2102 
           next_zero     = !(|alu_result);
2103 
           next_negative = alu_result[15];
2104 
           next_overflow = (rd_data[15] && op_code[7] && !alu_result[15]) || (!rd_data[15] && !op_code[7] && alu_result[15]);
2105 
         end
2106 
 
2107 
      // Instruction = LDL RD, #IMM8, Op Code =  1 1 1 1 0 RD IMM8
2108 
      // IMM8 => RD.L; $00 => RD.H, High Byte is cleared
2109 
      // Cycles - P
2110 
      {CONT, 16'b11110???????????} :
2111 
         begin
2112 
           ena_rd_low_byte  = 1'b1;
2113 
           ena_rd_high_byte = 1'b1;
2114 
 
2115 
           alu_result    = {8'b0, op_code[7:0]};
2116 
         end
2117 
 
2118 
      // Instruction = LDH RD, #IMM8, Op Code =  1 1 1 1 1 RD IMM8
2119 
      // IMM8 => RD.H, Low Byte is unchanged
2120 
      // Cycles - P
2121 
      {CONT, 16'b11111???????????} :
2122 
         begin
2123 
           ena_rd_high_byte = 1'b1;
2124 
 
2125 
           alu_result    = {op_code[7:0], 8'b0};
2126 
         end
2127 
      default :
2128 
        begin
2129 26 rehayes 
          // synopsys translate_off
2130 2 rehayes 
          $display("\nOP Code Error\n");
2131 26 rehayes 
          // synopsys translate_on
2132 12 rehayes 
          next_cpu_state   = DEBUG;
2133 40 rehayes 
          pc_incr_mux      = 16'h0000;
2134 
          next_pc          = pc_sum;
2135 12 rehayes 
          load_next_inst   = 1'b0;
2136 17 rehayes 
          op_code_error    = 1'b1;
2137 2 rehayes 
        end
2138 
    endcase
2139 40 rehayes 
 
2140 2 rehayes 
    end  // always
2141 
 
2142 
  xgate_barrel_shift barrel_shift(
2143 
    // outputs
2144 
    .shift_out( shift_out ),
2145 
    .shift_rollover( shift_rollover ),
2146 
    // inputs
2147 
    .shift_left( shift_left ),
2148 
    .shift_ammount( shift_ammount ),
2149 
    .shift_in( shift_in ),
2150 
    .shift_filler( shift_filler )
2151 
  );
2152 
 
2153 
  // Three to Eight line decoder
2154 
  always @*
2155 26 rehayes 
    case (semaph_risc)  // synopsys parallel_case
2156 2 rehayes 
      4'h0 : semap_risc_bit = 8'b0000_0001;
2157 
      4'h1 : semap_risc_bit = 8'b0000_0010;
2158 
      4'h2 : semap_risc_bit = 8'b0000_0100;
2159 
      4'h3 : semap_risc_bit = 8'b0000_1000;
2160 
      4'h4 : semap_risc_bit = 8'b0001_0000;
2161 
      4'h5 : semap_risc_bit = 8'b0010_0000;
2162 
      4'h6 : semap_risc_bit = 8'b0100_0000;
2163 
      4'h7 : semap_risc_bit = 8'b1000_0000;
2164 
    endcase
2165 12 rehayes 
 
2166 2 rehayes 
  assign semaph_stat = |risc_semap;
2167 
 
2168 59 rehayes 
  // Semaphore Bits
2169 
  genvar sem_gen_count;
2170 
  generate
2171 
    for (sem_gen_count = 0; sem_gen_count < 8; sem_gen_count = sem_gen_count + 1)
2172 
      begin:semaphore_
2173 
        semaphore_bit bit(
2174 
          // outputs
2175 
          .host_status( host_semap[sem_gen_count] ),
2176 
          .risc_status( risc_semap[sem_gen_count] ),
2177 
          // inputs
2178 
          .risc_clk( risc_clk ),
2179 
          .async_rst_b( async_rst_b ),
2180 
          .risc_bit_sel( semap_risc_bit[sem_gen_count] ),
2181 
          .csem( clear_semaph ),
2182 
          .ssem( set_semaph ),
2183 
          .host_wrt( write_xgsem ),
2184 
          .host_bit_mask( perif_data[sem_gen_count+8] ),
2185 
          .host_bit( perif_data[sem_gen_count] )
2186 
        );
2187 
      end
2188 
  endgenerate
2189 2 rehayes 
 
2190 
  endmodule  // xgate_inst_decode
2191 
 
2192 
// -----------------------------------------------------------------------------
2193 
// -----------------------------------------------------------------------------
2194 
// -----------------------------------------------------------------------------
2195 
 
2196 
module xgate_barrel_shift (
2197 
  output reg [15:0] shift_out,
2198 
  output reg        shift_rollover,
2199 
 
2200 
  input             shift_left,
2201 
  input      [ 4:0] shift_ammount,
2202 
  input      [15:0] shift_in,
2203 
  input      [15:0] shift_filler
2204 
  );
2205 
 
2206 
  always @*
2207 26 rehayes 
    casez ({shift_left, shift_ammount})  // synopsys parallel_case
2208 2 rehayes 
     // Start Right Shifts
2209 
      6'b0_0_0000 :
2210 
        begin
2211 
          shift_out      = shift_in;
2212 
          shift_rollover = 1'b0;
2213 
        end
2214 
      6'b0_0_0001 :
2215 
        begin
2216 
          shift_out      = {shift_filler[ 0], shift_in[15: 1]};
2217 
          shift_rollover =  shift_in[ 0];
2218 
        end
2219 
      6'b0_0_0010 :
2220 
        begin
2221 
          shift_out      = {shift_filler[ 1:0], shift_in[15: 2]};
2222 
          shift_rollover =  shift_in[ 1];
2223 
        end
2224 
      6'b0_0_0011 :
2225 
        begin
2226 
          shift_out      = {shift_filler[ 2:0], shift_in[15: 3]};
2227 
          shift_rollover =  shift_in[ 2];
2228 
        end
2229 
      6'b0_0_0100 :
2230 
        begin
2231 
          shift_out      = {shift_filler[ 3:0], shift_in[15: 4]};
2232 
          shift_rollover =  shift_in[ 3];
2233 
        end
2234 
      6'b0_0_0101 :
2235 
        begin
2236 
          shift_out      = {shift_filler[ 4:0], shift_in[15: 5]};
2237 
          shift_rollover =  shift_in[ 4];
2238 
        end
2239 
      6'b0_0_0110 :
2240 
        begin
2241 
          shift_out      = {shift_filler[ 5:0], shift_in[15: 6]};
2242 
          shift_rollover =  shift_in[ 5];
2243 
        end
2244 
      6'b0_0_0111 :
2245 
        begin
2246 
          shift_out      = {shift_filler[ 6:0], shift_in[15: 7]};
2247 
          shift_rollover =  shift_in[ 6];
2248 
        end
2249 
      6'b0_0_1000 :
2250 
        begin
2251 
          shift_out      = {shift_filler[ 7:0], shift_in[15: 8]};
2252 
          shift_rollover =  shift_in[ 7];
2253 
        end
2254 
      6'b0_0_1001 :
2255 
        begin
2256 
          shift_out      = {shift_filler[ 8:0], shift_in[15: 9]};
2257 
          shift_rollover =  shift_in[ 8];
2258 
        end
2259 
      6'b0_0_1010 :
2260 
        begin
2261 
          shift_out      = {shift_filler[ 9:0], shift_in[15:10]};
2262 
          shift_rollover =  shift_in[ 9];
2263 
        end
2264 
      6'b0_0_1011 :
2265 
        begin
2266 
          shift_out      = {shift_filler[10:0], shift_in[15:11]};
2267 
          shift_rollover =  shift_in[10];
2268 
        end
2269 
      6'b0_0_1100 :
2270 
        begin
2271 
          shift_out      = {shift_filler[11:0], shift_in[15:12]};
2272 
          shift_rollover =  shift_in[11];
2273 
        end
2274 
      6'b0_0_1101 :
2275 
        begin
2276 
          shift_out      = {shift_filler[12:0], shift_in[15:13]};
2277 
          shift_rollover =  shift_in[12];
2278 
        end
2279 
      6'b0_0_1110 :
2280 
        begin
2281 
          shift_out      = {shift_filler[13:0], shift_in[15:14]};
2282 
          shift_rollover =  shift_in[13];
2283 
        end
2284 
      6'b0_0_1111 :
2285 
        begin
2286 
          shift_out      = {shift_filler[14:0], shift_in[15]};
2287 
          shift_rollover =  shift_in[14];
2288 
        end
2289 
      6'b0_1_???? :
2290 
        begin
2291 
          shift_out      = shift_filler[15:0];
2292 
          shift_rollover = shift_in[15];
2293 
        end
2294 12 rehayes 
 
2295 2 rehayes 
     // Start Left Shifts
2296 12 rehayes 
 
2297 2 rehayes 
      6'b1_0_0000 :
2298 
        begin
2299 
          shift_out      =  shift_in;
2300 
          shift_rollover  = 1'b0;
2301 
        end
2302 
      6'b1_0_0001 :
2303 
        begin
2304 
          shift_out      = {shift_in[14:0], shift_filler[15]};
2305 
          shift_rollover =  shift_in[15];
2306 
        end
2307 
      6'b1_0_0010 :
2308 
        begin
2309 
          shift_out      = {shift_in[13:0], shift_filler[15:14]};
2310 
          shift_rollover =  shift_in[14];
2311 
        end
2312 
      6'b1_0_0011 :
2313 
        begin
2314 
          shift_out      = {shift_in[12:0], shift_filler[15:13]};
2315 
          shift_rollover =  shift_in[13];
2316 
        end
2317 
      6'b1_0_0100 :
2318 
        begin
2319 
          shift_out      = {shift_in[11:0], shift_filler[15:12]};
2320 
          shift_rollover =  shift_in[12];
2321 
        end
2322 
      6'b1_0_0101 :
2323 
        begin
2324 
          shift_out      = {shift_in[10:0], shift_filler[15:11]};
2325 
          shift_rollover =  shift_in[11];
2326 
        end
2327 
      6'b1_0_0110 :
2328 
        begin
2329 
          shift_out      = {shift_in[ 9:0], shift_filler[15:10]};
2330 
          shift_rollover =  shift_in[10];
2331 
        end
2332 
      6'b1_0_0111 :
2333 
        begin
2334 
          shift_out      = {shift_in[ 8:0], shift_filler[15: 9]};
2335 
          shift_rollover =  shift_in[ 9];
2336 
        end
2337 
      6'b1_0_1000 :
2338 
        begin
2339 
          shift_out      = {shift_in[ 7:0], shift_filler[15: 8]};
2340 
          shift_rollover =  shift_in[ 8];
2341 
        end
2342 
      6'b1_0_1001 :
2343 
        begin
2344 
          shift_out      = {shift_in[ 6:0], shift_filler[15: 7]};
2345 
          shift_rollover =  shift_in[ 7];
2346 
        end
2347 
      6'b1_0_1010 :
2348 
        begin
2349 
          shift_out      = {shift_in[ 5:0], shift_filler[15: 6]};
2350 
          shift_rollover =  shift_in[ 6];
2351 
        end
2352 
      6'b1_0_1011 :
2353 
        begin
2354 
          shift_out      = {shift_in[ 4:0], shift_filler[15: 5]};
2355 
          shift_rollover =  shift_in[ 5];
2356 
        end
2357 
      6'b1_0_1100 :
2358 
        begin
2359 
          shift_out      = {shift_in[ 3:0], shift_filler[15 :4]};
2360 
          shift_rollover =  shift_in[ 4];
2361 
        end
2362 
      6'b1_0_1101 :
2363 
        begin
2364 
          shift_out      = {shift_in[ 2:0], shift_filler[15: 3]};
2365 
          shift_rollover =  shift_in[ 3];
2366 
        end
2367 
      6'b1_0_1110 :
2368 
        begin
2369 
          shift_out      = {shift_in[ 1:0], shift_filler[15: 2]};
2370 
          shift_rollover =  shift_in[ 2];
2371 
        end
2372 
      6'b1_0_1111 :
2373 
        begin
2374 
          shift_out      = {shift_in[ 0], shift_filler[15: 1]};
2375 
          shift_rollover =  shift_in[ 1];
2376 
        end
2377 
      6'b1_1_???? :
2378 
        begin
2379 
          shift_out      = shift_filler[15: 0];
2380 
          shift_rollover = shift_in[ 0];
2381 
        end
2382 75 rehayes 
      default :
2383 
        begin
2384 
          shift_out      =  shift_in;
2385 
          shift_rollover  = 1'b0;
2386 
        end
2387 2 rehayes 
    endcase
2388 12 rehayes 
 
2389 
 
2390 2 rehayes 
endmodule  // xgate_barrel_shift
2391 
 
2392 
// -----------------------------------------------------------------------------
2393 
// -----------------------------------------------------------------------------
2394 
// -----------------------------------------------------------------------------
2395 
 
2396 
module semaphore_bit #(parameter NO_LOCK   = 2'b00,
2397 
                       parameter RISC_LOCK = 2'b10,
2398 12 rehayes 
                       parameter HOST_LOCK = 2'b11)
2399 2 rehayes 
  (
2400 
  output      host_status,   // Return status for Host processor
2401 
  output      risc_status,   // Return Status for RISC processor
2402 
 
2403 
  input       risc_clk,      // Semaphore register clock
2404 
  input       async_rst_b,   // Async reset signal
2405 
  input       risc_bit_sel,  // Bit selected by RISC
2406 
  input       csem,          // RISC Clear Semaphore Bit
2407 
  input       ssem,          // RISC Set Semaphore Bit
2408 
  input       host_wrt,      // Host write to the Semaphore Register
2409 
  input       host_bit_mask, // Host mask bit written to the Semaphore bit
2410 
  input       host_bit       // Host bit written to the Semaphore bit
2411 
  );
2412 
 
2413 
  reg [1:0] next_semap_state;
2414 
  reg [1:0] semap_state;
2415 12 rehayes 
 
2416 2 rehayes 
  assign host_status = semap_state == HOST_LOCK;
2417 
  assign risc_status = ssem && risc_bit_sel && ((semap_state == RISC_LOCK) || (next_semap_state == RISC_LOCK));
2418 
 
2419 
  always @(posedge risc_clk or negedge async_rst_b)
2420 
    if (!async_rst_b)
2421 
      semap_state <= NO_LOCK;
2422 
    else
2423 
      semap_state <= next_semap_state;
2424 
 
2425 
  always @*
2426 
    begin
2427 
      case(semap_state)
2428 12 rehayes 
        NO_LOCK:
2429 
          begin
2430 
            if (host_wrt && host_bit_mask && host_bit)
2431 
              next_semap_state = HOST_LOCK;
2432 
            else if (ssem && risc_bit_sel)
2433 
              next_semap_state = RISC_LOCK;
2434 
            else
2435 
              next_semap_state = NO_LOCK;
2436 
          end
2437 
        RISC_LOCK:
2438 
          begin
2439 
            if (csem && risc_bit_sel)
2440 
              next_semap_state = NO_LOCK;
2441 26 rehayes 
            else
2442 
              next_semap_state = RISC_LOCK;
2443 
           end
2444 12 rehayes 
        HOST_LOCK:
2445 
          begin
2446 
            if (host_wrt && host_bit_mask && !host_bit)
2447 
              next_semap_state = NO_LOCK;
2448 26 rehayes 
            else
2449 
              next_semap_state = HOST_LOCK;
2450 
           end
2451 12 rehayes 
        default:
2452 
          next_semap_state = NO_LOCK;
2453 2 rehayes 
      endcase
2454 
    end
2455 12 rehayes 
 
2456 2 rehayes 
endmodule  // semaphore_bit
2457 
 
2458 
 

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