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1 2 rehayes 
////////////////////////////////////////////////////////////////////////////////
2 
//
3 
//  XGATE Coprocessor - XGATE RISC Processor Core
4 
//
5 
//  Author: Bob Hayes
6 
//          rehayes@opencores.org
7 
//
8 
//  Downloaded from: http://www.opencores.org/projects/xgate.....
9 
//
10 
////////////////////////////////////////////////////////////////////////////////
11 
// Copyright (c) 2009, Robert Hayes
12 
//
13 
// This source file is free software: you can redistribute it and/or modify
14 
// it under the terms of the GNU Lesser General Public License as published
15 
// by the Free Software Foundation, either version 3 of the License, or
16 
// (at your option) any later version.
17 
//
18 
// Supplemental terms.
19 
//     * Redistributions of source code must retain the above copyright
20 
//       notice, this list of conditions and the following disclaimer.
21 
//     * Neither the name of the <organization> nor the
22 
//       names of its contributors may be used to endorse or promote products
23 
//       derived from this software without specific prior written permission.
24 
//
25 
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
26 
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28 
// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
29 
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
31 
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32 
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 
//
36 
// You should have received a copy of the GNU General Public License
37 
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
38 
////////////////////////////////////////////////////////////////////////////////
39 
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
40 
 
41 
module xgate_risc #(parameter MAX_CHANNEL = 127)    // Max XGATE Interrupt Channel Number
42 
 (
43 
  output reg [15:0] xgr1,
44 
  output reg [15:0] xgr2,
45 
  output reg [15:0] xgr3,
46 
  output reg [15:0] xgr4,
47 
  output reg [15:0] xgr5,
48 
  output reg [15:0] xgr6,
49 
  output reg [15:0] xgr7,
50 
  output     [15:0] xgate_address,
51 
  output     [15:0] write_mem_data,   // Data for Memory write
52 89 rehayes 
  output            mem_access,       //
53 2 rehayes 
  output            write_mem_strb_l, // Strobe for writing low data byte
54 
  output            write_mem_strb_h, // Strobe for writing high data bye
55 
  output reg                 zero_flag,
56 
  output reg                 negative_flag,
57 
  output reg                 carry_flag,
58 
  output reg                 overflow_flag,
59 
  output reg          [ 6:0] xgchid,
60 72 rehayes 
  output reg         [127:1] xgif_status,   // XGATE Interrupt Flag
61 12 rehayes 
  output                     xg_sw_irq,     // Xgate Software interrupt
62 2 rehayes 
  output              [ 7:0] host_semap,    // Semaphore status for host
63 12 rehayes 
  output reg                 debug_active,  // Latch to control debug mode in the RISC state machine
64 53 rehayes 
  output                     debug_ack,     // Clear debug register
65 
  output                     single_step,   // Pulse to trigger a single instruction execution in debug mode
66 2 rehayes 
 
67 
 
68 
  input      [15:0] read_mem_data,
69 
  input      [15:0] perif_data,
70 
  input             risc_clk,
71 
  input             async_rst_b,
72 5 rehayes 
  input             mem_req_ack,    // Memory Bus available - data good
73 53 rehayes 
  input             ss_mem_ack,     // WISHBONE Bus has granted single step memory access
74 2 rehayes 
  input             xge,            // XGATE Module Enable
75 31 rehayes 
  input             debug_mode_i,   // Force RISC core into debug mode
76 53 rehayes 
  input             xgdbg_set,      // Enter XGATE Debug Mode, pulse
77 15 rehayes 
  input             xgdbg_clear,    // Leave XGATE Debug Mode
78 2 rehayes 
  input             xgss,           // XGATE Single Step
79 
  input      [15:1] xgvbr,          // XGATE vector Base Address Register
80 
  input      [ 6:0] int_req,        // Encoded interrupt request
81 12 rehayes 
  input             xgie,           // XGATE Interrupt Enable
82 
  input             brk_irq_ena,    // Enable BRK instruction to generate interrupt
83 17 rehayes 
  input             write_xgchid,   // Write Strobe for XGCHID register
84 2 rehayes 
  input             write_xgsem,    // Write Strobe for XGSEM register
85 
  input             write_xgccr,    // Write Strobe for XGATE Condition Code Register
86 41 rehayes 
  input      [ 1:0] write_xgpc,     // Write Strobe for XGATE Program Counter
87 
  input      [ 1:0] write_xgr7,     // Write Strobe for XGATE Data Register R7
88 
  input      [ 1:0] write_xgr6,     // Write Strobe for XGATE Data Register R6
89 
  input      [ 1:0] write_xgr5,     // Write Strobe for XGATE Data Register R5
90 
  input      [ 1:0] write_xgr4,     // Write Strobe for XGATE Data Register R4
91 
  input      [ 1:0] write_xgr3,     // Write Strobe for XGATE Data Register R3
92 
  input      [ 1:0] write_xgr2,     // Write Strobe for XGATE Data Register R2
93 
  input      [ 1:0] write_xgr1,     // Write Strobe for XGATE Data Register R1
94 12 rehayes 
  input             xgsweif_c,      // Clear Software Flag
95 2 rehayes 
  input             clear_xgif_7,   // Strobe for decode to clear interrupt flag bank 7
96 
  input             clear_xgif_6,   // Strobe for decode to clear interrupt flag bank 6
97 
  input             clear_xgif_5,   // Strobe for decode to clear interrupt flag bank 5
98 
  input             clear_xgif_4,   // Strobe for decode to clear interrupt flag bank 4
99 
  input             clear_xgif_3,   // Strobe for decode to clear interrupt flag bank 3
100 
  input             clear_xgif_2,   // Strobe for decode to clear interrupt flag bank 2
101 
  input             clear_xgif_1,   // Strobe for decode to clear interrupt flag bank 1
102 
  input             clear_xgif_0,   // Strobe for decode to clear interrupt flag bank 0
103 
  input      [15:0] clear_xgif_data // Data for decode to clear interrupt flag
104 
);
105 
 
106 26 rehayes 
  integer j;     // Loop counters for decode of XGATE Interrupt Register
107 2 rehayes 
  integer k;     // Loop counter for Bit Field Insert decode
108 26 rehayes 
  integer bfi, bfii;   // Loop counter for Bit Field Insert function
109 2 rehayes 
 
110 
  // State machine sequence
111 5 rehayes 
  parameter [3:0]      //synopsys enum state_info
112 
       IDLE    = 4'b0000,      // waiting for interrupt
113 
       CONT    = 4'b0001,      // Instruction processing state, first state
114 12 rehayes 
       S_STALL = 4'b0010,      // Simple Stall while updating PC after change of flow
115 40 rehayes 
       W_STORE = 4'b1101,      // Stall while doing memory word write access
116 
       W_LOAD  = 4'b0011,      // Stall while doing memory word read access
117 
       B_LOAD  = 4'b0100,      // Stall while doing memory byte read access
118 12 rehayes 
       BREAK   = 4'b0101,      // Stop in this state after BRK instruction
119 
       BREAK_2 = 4'b0110,      // Advance PC after Single Step command
120 
       LD_INST = 4'b0111,      // Load Instruction in Debug mode
121 
       DEBUG   = 4'b1000,      // Stop in this state while waiting for debug commands
122 
       BOOT_1  = 4'b1001,      //
123 
       BOOT_2  = 4'b1010,      //
124 17 rehayes 
       BOOT_3  = 4'b1011,      //
125 
       CHG_CHID = 4'b1100;
126 12 rehayes 
 
127 
 
128 2 rehayes 
  // Semaphore states
129 
  parameter [1:0] NO_LOCK = 2'b00,
130 12 rehayes 
                  RISC_LOCK = 2'b10,
131 
                  HOST_LOCK = 2'b11;
132 
 
133 
 
134 
  reg  [ 3:0] cpu_state;         // State register for instruction processing
135 5 rehayes 
  reg  [ 3:0] next_cpu_state;    // Pseudo Register,
136 64 rehayes 
  wire        stm_auto_advance;  // State Machine increment without wait state holdoff
137 2 rehayes 
  reg         load_next_inst;    // Pseudo Register,
138 12 rehayes 
  reg  [15:0] program_counter;   // Program Counter register
139 40 rehayes 
  wire [15:0] pc_sum;            // Program Counter Adder
140 
  reg  [15:0] pc_incr_mux;       // Pseudo Register, mux to select the Program Counter Increment value
141 
  reg  [15:0] next_pc;           // Pseudo Register
142 
  wire [15:0] jump_offset;       // Address offset to be added to pc on conditional branch instruction
143 
  wire [15:0] bra_offset;        // Address offset to be added to pc on branch always instruction
144 2 rehayes 
  reg  [15:0] alu_result;        // Pseudo Register,
145 12 rehayes 
  reg  [15:0] op_code;           // Register for instruction being executed
146 2 rehayes 
  reg         ena_rd_low_byte;   // Pseudo Register,
147 
  reg         ena_rd_high_byte;  // Pseudo Register,
148 
 
149 12 rehayes 
  reg         data_access;    // Pseudo Register, RAM access in proccess
150 
  reg         data_write;     // Pseudo Register, RAM access is write operation
151 
  reg         data_word_op;   // Pseudo Register, RAM access operation is 16 bits(word)
152 
  reg  [15:0] data_address;   // Pseudo Register, Address for RAM data read or write
153 
  reg  [15:0] load_data;      // Data captured from WISHBONE Master bus for Load instructions
154 
 
155 
  reg  [ 6:0] set_irq_flag;   // Pseudo Register, pulse for setting irq output register
156 
 
157 2 rehayes 
  reg         next_zero;      // Pseudo Register,
158 
  reg         next_negative;  // Pseudo Register,
159 
  reg         next_carry;     // Pseudo Register,
160 
  reg         next_overflow;  // Pseudo Register,
161 17 rehayes 
 
162 12 rehayes 
  reg         op_code_error;  // Pseudo Register,
163 
  reg         software_error; // OP Code error, Address Error, BRK Error
164 
  wire        addr_error;     // Decode Addressing error
165 2 rehayes 
 
166 
  reg         set_semaph;     // Pseudo Register,
167 
  reg         clear_semaph;   // Pseudo Register,
168 
  reg  [ 2:0] semaph_risc;    // Pseudo Register,
169 
  reg  [ 7:0] semap_risc_bit; // Pseudo Register,
170 
  wire [ 7:0] risc_semap;     // Semaphore status bit for RISC
171 
  wire        semaph_stat;    // Return Status of Semaphore bit
172 12 rehayes 
 
173 2 rehayes 
  reg  [15:0] rd_data;        // Pseudo Register,
174 
  reg  [15:0] rs1_data;       // Pseudo Register,
175 
  reg  [15:0] rs2_data;       // Pseudo Register,
176 12 rehayes 
 
177 2 rehayes 
  wire [ 2:0] wrt_reg_sel;
178 12 rehayes 
  reg         sel_rd_field;   // Pseudo Register,
179 
  reg         wrt_sel_xgr1;   // Pseudo Register,
180 
  reg         wrt_sel_xgr2;   // Pseudo Register,
181 
  reg         wrt_sel_xgr3;   // Pseudo Register,
182 
  reg         wrt_sel_xgr4;   // Pseudo Register,
183 
  reg         wrt_sel_xgr5;   // Pseudo Register,
184 
  reg         wrt_sel_xgr6;   // Pseudo Register,
185 
  reg         wrt_sel_xgr7;   // Pseudo Register,
186 
 
187 72 rehayes 
  reg [127:1] xgif_d;
188 12 rehayes 
 
189 2 rehayes 
  reg  [15:0] shift_in;
190 
  wire [15:0] shift_out;
191 
  wire        shift_rollover;
192 
  reg         shift_left;
193 
  reg  [ 4:0] shift_ammount;
194 
  reg  [15:0] shift_filler;
195 53 rehayes 
  reg  [15:0] bf_mux_mask;   // Mask for controlling mux's in Bit Field Insert Instructions
196 12 rehayes 
 
197 59 rehayes 
  wire        start_thread;  // Signal to pop RISC core out of IDLE State
198 2 rehayes 
 
199 12 rehayes 
  wire        cpu_is_idle;   // Processor is in the IDLE state
200 
  wire        perif_wrt_ena; // Enable for Salve writes to CPU registers
201 
 
202 
  reg         xgss_edge;     // Flop for edge detection
203 
  reg         brk_set_dbg;   // Pulse to set debug_active from instruction decoder
204 15 rehayes 
  reg         cmd_change_pc; // Debug write to PC register
205 53 rehayes 
  reg         debug_edge;    // Reg for edge detection
206 12 rehayes 
 
207 64 rehayes 
  reg         cmd_dbg;
208 89 rehayes 
 
209 31 rehayes 
  reg  [ 1:0] chid_sm_ns;    // Pseudo Register for State Machine next state logic,
210 17 rehayes 
  reg  [ 1:0] chid_sm;       //
211 
  wire        chid_goto_idle; //
212 12 rehayes 
 
213 17 rehayes 
  // Debug states for change CHID
214 
  parameter [1:0] CHID_IDLE = 2'b00,
215 
                  CHID_TEST = 2'b10,
216 
                  CHID_WAIT = 2'b11;
217 
 
218 89 rehayes 
 
219 40 rehayes 
  assign jump_offset = {{6{op_code[8]}}, op_code[8:0], 1'b0};
220 
  assign bra_offset  = {{5{op_code[9]}}, op_code[9:0], 1'b0};
221 
  assign pc_sum      = program_counter + pc_incr_mux;
222 17 rehayes 
 
223 2 rehayes 
  assign xgate_address = data_access ? data_address : program_counter;
224 89 rehayes 
 
225 59 rehayes 
  //assign mem_access = data_access || load_next_inst || start_thread;
226 53 rehayes 
  assign mem_access = data_access || load_next_inst || (cpu_state == CONT) ||
227 59 rehayes 
                     (cpu_state == BREAK_2)  || start_thread;
228 17 rehayes 
 
229 12 rehayes 
  // Generate an address for an op code fetch from an odd address or a word Load/Store from/to an odd address.
230 
  assign addr_error = xgate_address[0] && (load_next_inst || (data_access && data_word_op));
231 
 
232 2 rehayes 
  assign write_mem_strb_l = data_access && data_write && (data_word_op || !data_address[0]);
233 
  assign write_mem_strb_h = data_access && data_write && (data_word_op ||  data_address[0]);
234 
  assign write_mem_data   = (write_mem_strb_l || write_mem_strb_h) ? rd_data : 16'b0;
235 12 rehayes 
 
236 17 rehayes 
  assign start_thread = xge && (|int_req) && !debug_active;
237 12 rehayes 
 
238 
  assign cpu_is_idle = (cpu_state == IDLE);
239 15 rehayes 
  assign perif_wrt_ena = (cpu_is_idle && ~xge) || debug_active;
240 12 rehayes 
 
241 2 rehayes 
  // Decode register select for RD and RS
242 
  always @*
243 
    begin
244 26 rehayes 
      case (op_code[10:8]) // synopsys parallel_case
245 2 rehayes 
        3'b001 : rd_data = xgr1;
246 
        3'b010 : rd_data = xgr2;
247 
        3'b011 : rd_data = xgr3;
248 
        3'b100 : rd_data = xgr4;
249 
        3'b101 : rd_data = xgr5;
250 
        3'b110 : rd_data = xgr6;
251 
        3'b111 : rd_data = xgr7;
252 
        default : rd_data = 16'h0;  // XGR0 is always Zero
253 
      endcase
254 
    end
255 
 
256 47 rehayes 
  assign wrt_reg_sel = (cpu_state == BOOT_3) ? 3'b001 :
257 
                       (sel_rd_field ? op_code[10:8] : op_code[4:2]);
258 2 rehayes 
 
259 
  // Decode register write select for eather RD or RI/RS2
260 
  always @*
261 
    begin
262 47 rehayes 
      wrt_sel_xgr1 = (wrt_reg_sel == 3'b001) && mem_req_ack;
263 
      wrt_sel_xgr2 = (wrt_reg_sel == 3'b010) && mem_req_ack;
264 
      wrt_sel_xgr3 = (wrt_reg_sel == 3'b011) && mem_req_ack;
265 
      wrt_sel_xgr4 = (wrt_reg_sel == 3'b100) && mem_req_ack;
266 
      wrt_sel_xgr5 = (wrt_reg_sel == 3'b101) && mem_req_ack;
267 
      wrt_sel_xgr6 = (wrt_reg_sel == 3'b110) && mem_req_ack;
268 
      wrt_sel_xgr7 = (wrt_reg_sel == 3'b111) && mem_req_ack;
269 2 rehayes 
    end
270 
 
271 
  // Decode register select for RS1 and RB
272 
  always @*
273 26 rehayes 
    case (op_code[7:5])  // synopsys parallel_case
274 2 rehayes 
      3'b001 : rs1_data = xgr1;
275 
      3'b010 : rs1_data = xgr2;
276 
      3'b011 : rs1_data = xgr3;
277 
      3'b100 : rs1_data = xgr4;
278 
      3'b101 : rs1_data = xgr5;
279 
      3'b110 : rs1_data = xgr6;
280 
      3'b111 : rs1_data = xgr7;
281 
      default : rs1_data = 16'h0;  // XGR0 is always Zero
282 
    endcase
283 
 
284 
  // Decode register select for RS2 and RI
285 
  always @*
286 26 rehayes 
    case (op_code[4:2])  // synopsys parallel_case
287 2 rehayes 
      3'b001 : rs2_data = xgr1;
288 
      3'b010 : rs2_data = xgr2;
289 
      3'b011 : rs2_data = xgr3;
290 
      3'b100 : rs2_data = xgr4;
291 
      3'b101 : rs2_data = xgr5;
292 
      3'b110 : rs2_data = xgr6;
293 
      3'b111 : rs2_data = xgr7;
294 
      default : rs2_data = 16'h0;  // XGR0 is always Zero
295 
    endcase
296 
 
297 
  // Decode mux select mask for Bit Field Insert Instructions
298 
  always @*
299 
    begin
300 
      k = 0;
301 
      while (k < 16)
302 
        begin
303 
          bf_mux_mask[k] = 1'b0;
304 
          if ((k >= rs2_data[3:0]) && (k <= rs2_data[3:0] + rs2_data[7:4]))
305 
            bf_mux_mask[k] = 1'b1;
306 
          k = k + 1;
307 
        end
308 
    end
309 
 
310 12 rehayes 
  //  Software Error Interrupt Latch
311 
  always @(posedge risc_clk or negedge async_rst_b)
312 
    if ( !async_rst_b )
313 
      software_error <= 1'b0;
314 
    else
315 17 rehayes 
      software_error <= addr_error || op_code_error ||
316 12 rehayes 
                        (brk_set_dbg && brk_irq_ena) || (software_error && !xgsweif_c);
317 17 rehayes 
 
318 12 rehayes 
  assign xg_sw_irq = software_error && xgie;
319 
 
320 64 rehayes 
  //  Latch the need to go to debug state set by xgdb
321 
  always @(posedge risc_clk or negedge async_rst_b)
322 
    if ( !async_rst_b )
323 
      begin
324 
        cmd_dbg  <= 1'b0;
325 
      end
326 
    else
327 
      begin
328 
        cmd_dbg  <= !((cpu_state == LD_INST) || (cpu_state == DEBUG)) &&
329 89 rehayes 
               (cmd_dbg || (xgdbg_set && mem_req_ack && (next_cpu_state == CONT)));
330 64 rehayes 
      end
331 89 rehayes 
 
332 12 rehayes 
  //  Latch the debug state, set by eather xgdb or BRK instructions
333 
  always @(posedge risc_clk or negedge async_rst_b)
334 
    if ( !async_rst_b )
335 53 rehayes 
      begin
336 64 rehayes 
        debug_active  <= 1'b0;
337 
        debug_edge    <= 0;
338 53 rehayes 
      end
339 12 rehayes 
    else
340 53 rehayes 
      begin
341 64 rehayes 
        debug_active  <= !xgdbg_clear && (cmd_dbg ||
342 
                         brk_set_dbg || op_code_error || debug_active);
343 
        debug_edge    <= debug_active;
344 53 rehayes 
      end
345 89 rehayes 
 
346 53 rehayes 
  assign debug_ack = debug_active && !debug_edge; // Posedge of debug_active
347 12 rehayes 
 
348 
  //  Convert xgss (Single Step Pulse) to a one risc_clk wide pulse
349 
  always @(posedge risc_clk or negedge async_rst_b)
350 
    if ( !async_rst_b )
351 
      xgss_edge  <= 1'b0;
352 
    else
353 
      xgss_edge  <= xgss;
354 
 
355 53 rehayes 
  assign single_step = (xgss && !xgss_edge) || (!debug_active && debug_edge);
356 12 rehayes 
 
357 59 rehayes 
  assign stm_auto_advance = (chid_sm != CHID_IDLE);
358 12 rehayes 
 
359 2 rehayes 
  //  CPU State Register
360 
  always @(posedge risc_clk or negedge async_rst_b)
361 
    if ( !async_rst_b )
362 
      cpu_state  <= IDLE;
363 
    else
364 59 rehayes 
      cpu_state  <= (mem_req_ack || stm_auto_advance) ? next_cpu_state : cpu_state;
365 2 rehayes 
 
366 
  //  CPU Instruction Register
367 
  always @(posedge risc_clk or negedge async_rst_b)
368 
    if ( !async_rst_b )
369 
      op_code  <= 16'h0000;
370 
    else
371 5 rehayes 
      op_code  <= (load_next_inst && mem_req_ack) ? read_mem_data : op_code;
372 12 rehayes 
 
373 2 rehayes 
  //  Active Channel Latch
374 
  always @(posedge risc_clk or negedge async_rst_b)
375 
    if ( !async_rst_b )
376 
      xgchid  <= 7'b0;
377 
    else
378 59 rehayes 
      xgchid  <= (write_xgchid && debug_active) ? perif_data[6:0] : (cpu_is_idle ? int_req : xgchid);
379 2 rehayes 
 
380 17 rehayes 
  //  Channel Change Debug state machine register
381 
  always @(posedge risc_clk or negedge async_rst_b)
382 
    if ( !async_rst_b )
383 
      chid_sm  <= CHID_IDLE;
384 
    else
385 
      chid_sm  <= chid_sm_ns;
386 
 
387 
  //  Channel Change Debug next state
388 
  always @*
389 26 rehayes 
    case (chid_sm)  // synopsys parallel_case
390 17 rehayes 
      CHID_IDLE:
391 
        if ( write_xgchid && debug_active )
392 
          chid_sm_ns  = CHID_TEST;
393 89 rehayes 
        else
394 75 rehayes 
          chid_sm_ns  = CHID_IDLE;
395 17 rehayes 
      CHID_TEST:
396 
        if ( !((cpu_state == IDLE) || (cpu_state == CHG_CHID)) && (|xgchid) )
397 
          chid_sm_ns  = CHID_IDLE;
398 
        else
399 
          chid_sm_ns  = CHID_WAIT;
400 
      CHID_WAIT:
401 
        if ( (cpu_state == IDLE) || (cpu_state == CHG_CHID) )
402 
          chid_sm_ns  = CHID_IDLE;
403 
        else
404 
          chid_sm_ns  = CHID_WAIT;
405 
      default : chid_sm_ns  = CHID_IDLE;
406 
    endcase
407 89 rehayes 
 
408 17 rehayes 
  assign chid_goto_idle = (chid_sm == CHID_WAIT);
409 
 
410 2 rehayes 
  //  CPU Read Data Buffer Register
411 
  always @(posedge risc_clk or negedge async_rst_b)
412 
    if ( !async_rst_b )
413 
      load_data  <= 16'h0000;
414 
    else
415 5 rehayes 
      load_data  <= (data_access && !data_write && mem_req_ack) ? read_mem_data : load_data;
416 2 rehayes 
 
417 
  //  Program Counter Register
418 
  always @(posedge risc_clk or negedge async_rst_b)
419 
    if ( !async_rst_b )
420 
      program_counter  <= 16'h0000;
421 
    else
422 41 rehayes 
      program_counter  <= (|write_xgpc && perif_wrt_ena) ?
423 
      {(write_xgpc[1] ? perif_data[15:8]: program_counter[15:8]),
424 
       (write_xgpc[0] ? perif_data[ 7:0]: program_counter[ 7:0])} :
425 
      (mem_req_ack ? next_pc : program_counter);
426 2 rehayes 
 
427 15 rehayes 
  //  Debug Change Program Counter Register
428 
  always @(posedge risc_clk or negedge async_rst_b)
429 
    if ( !async_rst_b )
430 
      cmd_change_pc  <= 1'b0;
431 
    else
432 53 rehayes 
      cmd_change_pc  <= (|write_xgpc && perif_wrt_ena) || (cmd_change_pc && !mem_req_ack);
433 15 rehayes 
 
434 2 rehayes 
  //  ALU Flag Bits
435 
  always @(posedge risc_clk or negedge async_rst_b)
436 
    if ( !async_rst_b )
437 
      begin
438 
        carry_flag    <= 1'b0;
439 
        overflow_flag <= 1'b0;
440 
        zero_flag     <= 1'b0;
441 
        negative_flag <= 1'b0;
442 
      end
443 
    else
444 
      begin
445 12 rehayes 
        carry_flag    <= (write_xgccr && perif_wrt_ena) ? perif_data[0] : (mem_req_ack ? next_carry : carry_flag);
446 
        overflow_flag <= (write_xgccr && perif_wrt_ena) ? perif_data[1] : (mem_req_ack ? next_overflow : overflow_flag);
447 
        zero_flag     <= (write_xgccr && perif_wrt_ena) ? perif_data[2] : (mem_req_ack ? next_zero : zero_flag);
448 
        negative_flag <= (write_xgccr && perif_wrt_ena) ? perif_data[3] : (mem_req_ack ? next_negative : negative_flag);
449 2 rehayes 
      end
450 
 
451 
  //  Interrupt Flag next value
452 
  always @*
453 12 rehayes 
    begin
454 31 rehayes 
      xgif_d = 0;
455 72 rehayes 
      j = 1;
456 
      while (j <= MAX_CHANNEL)  // while loop sets irq bit and maintains previously set bits
457 12 rehayes 
        begin
458 31 rehayes 
         xgif_d[j]  = xgif_status[j] || (set_irq_flag == j);
459 12 rehayes 
         j = j + 1;
460 
        end
461 67 rehayes 
      if (clear_xgif_0)
462 89 rehayes 
        xgif_d[15: 1]  = ~clear_xgif_data & xgif_status[15: 1];
463 67 rehayes 
      if (clear_xgif_1)
464 89 rehayes 
        xgif_d[31:16]  = ~clear_xgif_data & xgif_status[31:16];
465 67 rehayes 
      if (clear_xgif_2)
466 89 rehayes 
        xgif_d[47:32]  = ~clear_xgif_data & xgif_status[47:32];
467 67 rehayes 
      if (clear_xgif_3)
468 89 rehayes 
        xgif_d[63:48]  = ~clear_xgif_data & xgif_status[63:48];
469 67 rehayes 
      if (clear_xgif_4)
470 89 rehayes 
        xgif_d[79:64]  = ~clear_xgif_data & xgif_status[79:64];
471 67 rehayes 
      if (clear_xgif_5)
472 89 rehayes 
        xgif_d[95:80]  = ~clear_xgif_data & xgif_status[95:80];
473 67 rehayes 
      if (clear_xgif_6)
474 89 rehayes 
        xgif_d[111:96]  = ~clear_xgif_data & xgif_status[111:96];
475 67 rehayes 
      if (clear_xgif_7)
476 89 rehayes 
        xgif_d[127:112] = ~clear_xgif_data & xgif_status[127:112];
477 12 rehayes 
    end
478 2 rehayes 
 
479 
  //  Interrupt Flag Registers
480 
  always @(posedge risc_clk or negedge async_rst_b)
481 
    if ( !async_rst_b )
482 31 rehayes 
      xgif_status  <= 0;
483 2 rehayes 
    else
484 31 rehayes 
      xgif_status  <= xgif_d;
485 2 rehayes 
 
486 
 
487 
  //  RISC Data Registers
488 
  always @(posedge risc_clk or negedge async_rst_b)
489 
    if ( !async_rst_b )
490 
      begin
491 
        xgr1 <= 16'b0;
492 
        xgr2 <= 16'b0;
493 
        xgr3 <= 16'b0;
494 
        xgr4 <= 16'b0;
495 
        xgr5 <= 16'b0;
496 
        xgr6 <= 16'b0;
497 
        xgr7 <= 16'b0;
498 
      end
499 
    else
500 
      begin
501 89 rehayes 
        xgr1 <= (|write_xgr1 && perif_wrt_ena) ?
502 
                {(write_xgr1[1] ? perif_data[15:8]: xgr1[15:8]),
503 41 rehayes 
                 (write_xgr1[0] ? perif_data[ 7:0]: xgr1[ 7:0])} :
504 2 rehayes 
                {((wrt_sel_xgr1 && ena_rd_high_byte) ? alu_result[15:8] : xgr1[15:8]),
505 
                 ((wrt_sel_xgr1 && ena_rd_low_byte)  ? alu_result[ 7:0] : xgr1[ 7:0])};
506 89 rehayes 
        xgr2 <= (|write_xgr2 && perif_wrt_ena) ?
507 
                {(write_xgr2[1] ? perif_data[15:8]: xgr2[15:8]),
508 41 rehayes 
                 (write_xgr2[0] ? perif_data[ 7:0]: xgr2[ 7:0])} :
509 2 rehayes 
                {((wrt_sel_xgr2 && ena_rd_high_byte) ? alu_result[15:8] : xgr2[15:8]),
510 
                 ((wrt_sel_xgr2 && ena_rd_low_byte)  ? alu_result[ 7:0] : xgr2[ 7:0])};
511 89 rehayes 
        xgr3 <= (|write_xgr3 && perif_wrt_ena) ?
512 
                {(write_xgr3[1] ? perif_data[15:8]: xgr3[15:8]),
513 41 rehayes 
                 (write_xgr3[0] ? perif_data[ 7:0]: xgr3[ 7:0])} :
514 2 rehayes 
                {((wrt_sel_xgr3 && ena_rd_high_byte) ? alu_result[15:8] : xgr3[15:8]),
515 
                 ((wrt_sel_xgr3 && ena_rd_low_byte)  ? alu_result[ 7:0] : xgr3[ 7:0])};
516 89 rehayes 
        xgr4 <= (|write_xgr4 && perif_wrt_ena) ?
517 
                {(write_xgr4[1] ? perif_data[15:8]: xgr4[15:8]),
518 41 rehayes 
                 (write_xgr4[0] ? perif_data[ 7:0]: xgr4[ 7:0])} :
519 2 rehayes 
                {((wrt_sel_xgr4 && ena_rd_high_byte) ? alu_result[15:8] : xgr4[15:8]),
520 
                 ((wrt_sel_xgr4 && ena_rd_low_byte)  ? alu_result[ 7:0] : xgr4[ 7:0])};
521 89 rehayes 
        xgr5 <= (|write_xgr5 && perif_wrt_ena) ?
522 
                {(write_xgr5[1] ? perif_data[15:8]: xgr5[15:8]),
523 41 rehayes 
                 (write_xgr5[0] ? perif_data[ 7:0]: xgr5[ 7:0])} :
524 2 rehayes 
                {((wrt_sel_xgr5 && ena_rd_high_byte) ? alu_result[15:8] : xgr5[15:8]),
525 
                 ((wrt_sel_xgr5 && ena_rd_low_byte)  ? alu_result[ 7:0] : xgr5[ 7:0])};
526 89 rehayes 
        xgr6 <= (|write_xgr6 && perif_wrt_ena) ?
527 
                {(write_xgr6[1] ? perif_data[15:8]: xgr6[15:8]),
528 41 rehayes 
                 (write_xgr6[0] ? perif_data[ 7:0]: xgr6[ 7:0])} :
529 2 rehayes 
                {((wrt_sel_xgr6 && ena_rd_high_byte) ? alu_result[15:8] : xgr6[15:8]),
530 
                 ((wrt_sel_xgr6 && ena_rd_low_byte)  ? alu_result[ 7:0] : xgr6[ 7:0])};
531 89 rehayes 
        xgr7 <= (|write_xgr7 && perif_wrt_ena) ?
532 
                {(write_xgr7[1] ? perif_data[15:8]: xgr7[15:8]),
533 41 rehayes 
                 (write_xgr7[0] ? perif_data[ 7:0]: xgr7[ 7:0])} :
534 2 rehayes 
                {((wrt_sel_xgr7 && ena_rd_high_byte) ? alu_result[15:8] : xgr7[15:8]),
535 
                 ((wrt_sel_xgr7 && ena_rd_low_byte)  ? alu_result[ 7:0] : xgr7[ 7:0])};
536 
      end
537 
 
538 89 rehayes 
  // V - Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
539 
  // P - Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
540 
  // r - 8-bit data read: lasts for at least one RISC core cycle
541 
  // R - 16-bit data read: lasts for at least one RISC core cycle
542 
  // w - 8-bit data write: lasts for at least one RISC core cycle
543 
  // W - 16-bit data write: lasts for at least one RISC core cycle
544 
  // A - Alignment cycle: no read or write, lasts for zero or one RISC core cycles
545 
  // f - Free cycle: no read or write, lasts for one RISC core cycles
546 2 rehayes 
  // Special Cases
547 89 rehayes 
  // PP/P - Branch: PP if branch taken, P if not taken
548 2 rehayes 
 
549 
  always @*
550 
    begin
551 
      ena_rd_low_byte  = 1'b0;
552 
      ena_rd_high_byte = 1'b0;
553 
 
554 64 rehayes 
      next_cpu_state = (debug_active || cmd_dbg) ? LD_INST : CONT;
555 2 rehayes 
      load_next_inst = 1'b1;
556 64 rehayes 
      pc_incr_mux    = cmd_dbg ? 16'h0000: 16'h0002;  // Verilog Instruction order dependent
557 40 rehayes 
      next_pc        = pc_sum;    // ""
558 2 rehayes 
 
559 
      next_zero      = zero_flag;
560 
      next_negative  = negative_flag;
561 
      next_carry     = carry_flag;
562 
      next_overflow  = overflow_flag;
563 
 
564 12 rehayes 
      brk_set_dbg    = 1'b0;
565 
      op_code_error  = 1'b0;
566 
 
567 2 rehayes 
      alu_result     = 16'h0000;
568 
      sel_rd_field   = 1'b1;
569 12 rehayes 
 
570 2 rehayes 
      data_access    = 1'b0;
571 
      data_word_op   = 1'b0;
572 12 rehayes 
      data_write     = 1'b0;
573 2 rehayes 
      data_address   = 16'h0000;
574 
 
575 
      shift_left     = 1'b0;
576 
      shift_ammount  = 5'b0_0000;
577 
      shift_filler   = 16'h0000;
578 
      shift_in       = rd_data;
579 12 rehayes 
 
580 2 rehayes 
      set_irq_flag   = 7'b0;
581 12 rehayes 
 
582 89 rehayes 
      set_semaph     = 1'b0;
583 
      clear_semaph   = 1'b0;
584 
      semaph_risc    = 3'b0;
585 2 rehayes 
 
586 
  casez ({cpu_state, op_code})
587 
 
588 
      {IDLE, 16'b????????????????} :
589 
         begin
590 
           next_cpu_state   = start_thread ? BOOT_1 : IDLE;
591 40 rehayes 
           pc_incr_mux      = 16'h0000;
592 
           next_pc          = pc_sum;
593 2 rehayes 
           load_next_inst   = 1'b0;
594 
         end
595 
 
596 17 rehayes 
      {CHG_CHID, 16'b????????????????} :
597 
         begin
598 89 rehayes 
           if (!xge)
599 17 rehayes 
             next_cpu_state = IDLE;
600 89 rehayes 
           else if (ss_mem_ack || !debug_active)
601 17 rehayes 
             next_cpu_state = BOOT_1;
602 89 rehayes 
           else
603 
             next_cpu_state = CHG_CHID;
604 17 rehayes 
 
605 40 rehayes 
           pc_incr_mux      = 16'h0000;
606 
           next_pc          = pc_sum;
607 17 rehayes 
           load_next_inst   = 1'b0;
608 
         end
609 
 
610 2 rehayes 
      // Output RAM address for Program Counter
611 
      {BOOT_1, 16'b????????????????} :
612 
         begin
613 
           next_cpu_state   = BOOT_2;
614 40 rehayes 
           pc_incr_mux      = 16'h0000;
615 
           next_pc          = pc_sum;
616 2 rehayes 
           load_next_inst   = 1'b0;
617 
           data_access      = 1'b1;
618 
           data_word_op     = 1'b1;
619 
           data_address     = {xgvbr, 1'b0} + {7'b0, xgchid, 2'b0};
620 
         end
621 
 
622 
      // Load PC value from data buffer register
623 
      // Output RAM address for initial variable pointer
624 
      {BOOT_2, 16'b????????????????} :
625 
         begin
626 
           next_cpu_state   = BOOT_3;
627 
           next_pc          = load_data;
628 
           load_next_inst   = 1'b0;
629 
           data_access      = 1'b1;
630 
           data_word_op     = 1'b1;
631 
           data_address     = {xgvbr, 1'b0} + {7'b0, xgchid, 2'b0} + 2;
632 
         end
633 
 
634 
      // Load R1 with initial variable pointer from data buffer register
635 
      // Load first instruction to op_code register
636 
      // Increment Program Counter
637 
      {BOOT_3, 16'b????????????????} :
638 
         begin
639 
           next_cpu_state   = CONT;
640 
           ena_rd_low_byte  = 1'b1;
641 
           ena_rd_high_byte = 1'b1;
642 
           alu_result       = load_data;
643 
         end
644 
 
645 12 rehayes 
      {BREAK, 16'b????????????????} :
646 
         begin
647 89 rehayes 
           if (!xge)
648 
                   next_cpu_state = IDLE;
649 
           else if (ss_mem_ack || !debug_active)
650 
                   next_cpu_state = BREAK_2;
651 
           else if (chid_goto_idle)
652 
                   next_cpu_state = CHG_CHID;
653 
           else
654 
                   next_cpu_state = BREAK;
655 12 rehayes 
           load_next_inst = 1'b0;
656 40 rehayes 
           pc_incr_mux    = 16'h0000;
657 
           next_pc        = pc_sum;
658 12 rehayes 
         end
659 
 
660 
      {BREAK_2, 16'b????????????????} :
661 
         begin
662 
           next_cpu_state = LD_INST;
663 
           load_next_inst = 1'b0;
664 
         end
665 
 
666 
      {LD_INST, 16'b????????????????} :
667 
         begin
668 
           next_cpu_state = DEBUG;
669 40 rehayes 
           pc_incr_mux    = 16'h0000;
670 
           next_pc        = pc_sum;
671 12 rehayes 
         end
672 
 
673 2 rehayes 
      {DEBUG, 16'b????????????????} :
674 
         begin
675 89 rehayes 
           if (!xge)
676 
                   next_cpu_state = IDLE;
677 
           else if (ss_mem_ack || !debug_active)
678 
                   next_cpu_state = CONT;
679 
           else if (cmd_change_pc)
680 
                   next_cpu_state = LD_INST;
681 
           else if (chid_goto_idle)
682 
                   next_cpu_state = CHG_CHID;
683 
           else
684 
                   next_cpu_state = DEBUG;
685 17 rehayes 
 
686 15 rehayes 
           load_next_inst = cmd_change_pc;
687 40 rehayes 
           pc_incr_mux    = 16'h0000;
688 
           next_pc        = pc_sum;
689 2 rehayes 
         end
690 
 
691 12 rehayes 
      // Pause here for program counter change of flow or memory write access
692 5 rehayes 
      //  Load next instruction and increment PC
693 12 rehayes 
      // Default next_cpu_state is CONT
694 5 rehayes 
      {S_STALL, 16'b????????????????} :
695 
         begin
696 
         end
697 
 
698 
      // Pause here for memory read word access
699 
      //  Load next instruction and increment PC
700 40 rehayes 
      {W_LOAD, 16'b????????????????} :
701 5 rehayes 
         begin
702 
           alu_result       = load_data;
703 
           ena_rd_low_byte  = 1'b1;
704 
           ena_rd_high_byte = 1'b1;
705 
         end
706 
 
707 
      // Pause here for memory read byte access
708 
      //  Load next instruction and increment PC
709 40 rehayes 
      {B_LOAD, 16'b????????????????} :
710 5 rehayes 
         begin
711 
           alu_result       = {8'h00, load_data[15:8]};
712 
           ena_rd_low_byte  = 1'b1;
713 
           ena_rd_high_byte = 1'b1;
714 
         end
715 
 
716 2 rehayes 
      // -----------------------------------------------------------------------
717 
      // Instruction Group -- Return to Scheduler and Others
718 
      // -----------------------------------------------------------------------
719 
 
720 
      // Instruction = BRK, Op Code =  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
721 
      // Cycles - PAff
722 
      {CONT, 16'b0000000000000000} :
723 
         begin
724 12 rehayes 
           next_cpu_state   = BREAK;
725 40 rehayes 
           pc_incr_mux      = 16'hfffe;  // equals -2
726 
           next_pc          = pc_sum;
727 2 rehayes 
           load_next_inst   = 1'b0;
728 12 rehayes 
           brk_set_dbg      = 1'b1;
729 2 rehayes 
         end
730 
 
731 
      // Instruction = NOP, Op Code =  0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
732 
      {CONT, 16'b0000000100000000} :
733 
         begin
734 
         end
735 
 
736 
      // Instruction = RTS, Op Code =  0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
737 
      // Cycles - PA
738 
      {CONT, 16'b0000001000000000} :
739 
         begin
740 
           next_cpu_state   = IDLE;
741 40 rehayes 
           pc_incr_mux      = 16'h0000;
742 
           next_pc          = pc_sum;
743 2 rehayes 
           load_next_inst   = 1'b0;
744 
         end
745 
 
746 
      // Instruction = SIF, Op Code =  0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
747 
      // Sets the Interrupt Flag of the current channel (XGCHID) will be set.
748 
      // Cycles - PA
749 
      {CONT, 16'b0000001100000000} :
750 
         begin
751 
           set_irq_flag = xgchid;
752 
         end
753 
 
754 
      // -----------------------------------------------------------------------
755 
      // Instruction Group -- Semaphore Instructions
756 
      // -----------------------------------------------------------------------
757 
 
758 
      // Instruction = CSEM IMM3, Op Code =  0 0 0 0 0 IMM3 1 1 1 1 0 0 0 0
759 
      // Unlocks a semaphore that was locked by the RISC core.
760 
      // Cycles - PA
761 
      {CONT, 16'b00000???11110000} :
762 
         begin
763 
           clear_semaph = 1'b1;
764 
           semaph_risc  = op_code[10:8];
765 
         end
766 
 
767 
      // Instruction = CSEM RS, Op Code =  0 0 0 0 0 RS 1 1 1 1 0 0 0 1
768 
      // Unlocks a semaphore that was locked by the RISC core.
769 
      // In monadic address mode, bits RS[2:0] select the semaphore to be cleared.
770 
      // Cycles - PA
771 
      {CONT, 16'b00000???11110001} :
772 
         begin
773 
           clear_semaph = 1'b1;
774 
           semaph_risc  = rd_data[2:0];
775 
         end
776 
 
777 
      // Instruction = SSEM IMM3, Op Code =  0 0 0 0 0 IMM3 1 1 1 1 0 0 1 0
778 
      // Attempts to set a semaphore. The state of the semaphore will be stored in the Carry-Flag:
779 
      // 1 = Semaphore is locked by the RISC core
780 
      // 0 = Semaphore is locked by the S12X_CPU
781 
      // Cycles - PA
782 
      {CONT, 16'b00000???11110010} :
783 
         begin
784 
           set_semaph  = 1'b1;
785 
           semaph_risc = op_code[10:8];
786 
 
787 89 rehayes 
           next_carry  = semaph_stat;
788 2 rehayes 
         end
789 
 
790 
      // Instruction = SSEM RS, Op Code =  0 0 0 0 0 RS 1 1 1 1 0 0 1 1
791 
      // Attempts to set a semaphore. The state of the semaphore will be stored in the Carry-Flag:
792 
      // 1 = Semaphore is locked by the RISC core
793 
      // 0 = Semaphore is locked by the S12X_CPU
794 
      // In monadic address mode, bits RS[2:0] select the semaphore to be set.
795 
      // Cycles - PA
796 
      {CONT, 16'b00000???11110011} :
797 
         begin
798 
           set_semaph  = 1'b1;
799 
           semaph_risc = rd_data[2:0];
800 
 
801 89 rehayes 
           next_carry  = semaph_stat;
802 2 rehayes 
         end
803 
 
804 
      // -----------------------------------------------------------------------
805 
      // Instruction Group -- Single Register Instructions
806 
      // -----------------------------------------------------------------------
807 
 
808 
      // Instruction = SEX RD, Op Code =  0 0 0 0 0 RD 1 1 1 1 0 1 0 0
809 
      // SEX - Sign Extend Byte to Word
810 
      // Cycles - P
811 
      {CONT, 16'b00000???11110100} :
812 
         begin
813 
           ena_rd_high_byte = 1'b1;
814 
 
815 
           alu_result    = {{8{rd_data[7]}}, rd_data[7:0]};
816 
           next_zero     = !(|alu_result);
817 
           next_negative = alu_result[15];
818 
           next_overflow = 1'b0;
819 
         end
820 
 
821 
      // Instruction = PAR RD, Op Code =  0 0 0 0 0 RD 1 1 1 1 0 1 0 1
822 
      // PAR - Calculate Parity
823 
      // Set Carry Flag on odd number of bits
824 
      // Cycles - P
825 
      {CONT, 16'b00000???11110101} :
826 
         begin
827 
           next_zero     = !(|rd_data);
828 
           next_negative = 1'b0;
829 
           next_carry    = ^rd_data;
830 
           next_overflow = 1'b0;
831 
         end
832 
 
833 
      // Instruction = JAL RD, Op Code =  0 0 0 0 0 RD 1 1 1 1 0 1 1 0
834 
      // Jump And Link
835 
      // PC + $0002 => RD; RD => PC
836 
      // Jumps to the address stored in RD and saves the return address in RD.
837 
      // Cycles - PP
838 
      {CONT, 16'b00000???11110110} :
839 
         begin
840 5 rehayes 
           next_cpu_state   = S_STALL;
841 2 rehayes 
           load_next_inst   = 1'b0;
842 
           ena_rd_low_byte  = 1'b1;
843 
           ena_rd_high_byte = 1'b1;
844 
           alu_result       = program_counter;
845 
           next_pc          = rd_data;
846 
         end
847 
 
848 
      // Instruction = SIF RS, Op Code =  0 0 0 0 0 RS 1 1 1 1 0 1 1 1
849 
      // Sets the Interrupt Flag associated with the channel id number
850 
      // contained in RS[6:0] is set. The content of RS[15:7] is ignored
851 
      // Cycles - P
852 
      {CONT, 16'b00000???11110111} :
853 89 rehayes 
         set_irq_flag = rd_data[6:0];
854 2 rehayes 
 
855 
      // -----------------------------------------------------------------------
856 
      // Instruction Group -- Special Move instructions
857 
      // -----------------------------------------------------------------------
858 
 
859 
      // Instruction = TFR RD,CCR, Op Code =  0 0 0 0 0 RD 1 1 1 1 1 0 0 0
860 
      // Transfer from and to Special Registers
861 
      // TFR RD,CCR: CCR => RD[3:0], 0 => RD[15:4]
862 
      // Cycles - P
863 
      {CONT, 16'b00000???11111000} :
864 
         begin
865 
           ena_rd_low_byte  = 1'b1;
866 
           ena_rd_high_byte = 1'b1;
867 
           alu_result       = {12'b0, negative_flag, zero_flag, overflow_flag, carry_flag};
868 
         end
869 
 
870 
      // Instruction = TFR CCR,RS, Op Code =  0 0 0 0 0 RS 1 1 1 1 1 0 0 1
871 
      // Transfer from and to Special Registers
872 
      // TFR CCR,RD: RD[3:0] => CCR
873 
      // Cycles - P
874 
      {CONT, 16'b00000???11111001} :
875 
         begin
876 
           next_negative = rd_data[3];
877 
           next_zero     = rd_data[2];
878 
           next_overflow = rd_data[1];
879 
           next_carry    = rd_data[0];
880 
         end
881 
 
882 
      // Instruction = TFR RD,PC, Op Code =  0 0 0 0 0 RD 1 1 1 1 1 0 1 0
883 
      // Transfer from and to Special Registers
884 
      // TFR RD,PC: PC+4 => RD
885 
      // Cycles - P
886 
      {CONT, 16'b00000???11111010} :
887 
         begin
888 
           ena_rd_low_byte  = 1'b1;
889 
           ena_rd_high_byte = 1'b1;
890 
           alu_result       = next_pc;
891 
         end
892 
 
893 
      // -----------------------------------------------------------------------
894 
      // Instruction Group -- Shift instructions Dyadic
895 
      // -----------------------------------------------------------------------
896 
 
897 
      // Instruction = BFFO RD, RS, Op Code =  0 0 0 0 1 RD RS 1 0 0 0 0
898 
      // BFFO - Bit Field Find First One
899 
      // FirstOne (RS) => RD
900 
      // Cycles - P
901 
      {CONT, 16'b00001??????10000} :
902 
         begin
903 
           ena_rd_low_byte  = 1'b1;
904 
           ena_rd_high_byte = 1'b1;
905 
 
906 26 rehayes 
           casez (rs1_data)  // synopsys parallel_case
907 2 rehayes 
             16'b1???_????_????_???? : alu_result = 16'h000f;
908 
             16'b01??_????_????_???? : alu_result = 16'h000e;
909 
             16'b001?_????_????_???? : alu_result = 16'h000d;
910 
             16'b0001_????_????_???? : alu_result = 16'h000c;
911 
             16'b0000_1???_????_???? : alu_result = 16'h000b;
912 
             16'b0000_01??_????_???? : alu_result = 16'h000a;
913 
             16'b0000_001?_????_???? : alu_result = 16'h0009;
914 
             16'b0000_0001_????_???? : alu_result = 16'h0008;
915 
             16'b0000_0000_1???_???? : alu_result = 16'h0007;
916 
             16'b0000_0000_01??_???? : alu_result = 16'h0006;
917 
             16'b0000_0000_001?_???? : alu_result = 16'h0005;
918 
             16'b0000_0000_0001_???? : alu_result = 16'h0004;
919 
             16'b0000_0000_0000_1??? : alu_result = 16'h0003;
920 
             16'b0000_0000_0000_01?? : alu_result = 16'h0002;
921 
             16'b0000_0000_0000_001? : alu_result = 16'h0001;
922 
             16'b0000_0000_0000_0001 : alu_result = 16'h0000;
923 
           endcase
924 
           next_zero     = !(|alu_result);
925 
           next_negative = 1'b0;
926 
           next_carry    = !(|rs1_data);
927 
           next_overflow = 1'b0;
928 
         end
929 
 
930 
      // Instruction = ASR RD, RS, Op Code =  0 0 0 0 1 RD RS 1 0 0 0 1
931 
      // ASR - Arithmetic Shift Right
932 
      // n = RS
933 
      // Cycles - P
934 
      {CONT, 16'b00001??????10001} :
935 
         begin
936 
           shift_ammount  = {|rs1_data[15:4], rs1_data[3:0]};
937 
           shift_filler   = {16{rd_data[15]}};
938 12 rehayes 
 
939 2 rehayes 
           ena_rd_low_byte  = 1'b1;
940 
           ena_rd_high_byte = 1'b1;
941 
           alu_result       = shift_out;
942 
           next_zero        = !(|alu_result);
943 
           next_negative    = alu_result[15];
944 
           next_carry       = |rs1_data ? shift_rollover : carry_flag;
945 
           next_overflow    = rd_data[15] ^ alu_result[15];  // Table and text disagree
946 
         end
947 
 
948 
      // Instruction = CSL RD, RS, Op Code =  0 0 0 0 1 RD RS 1 0 0 1 0
949 
      // CSL - Logical Shift Left with Carry
950 
      // n = RS
951 
      // Cycles - P
952 
      {CONT, 16'b00001??????10010} :
953 
         begin
954 
           shift_left     = 1'b1;
955 
           shift_ammount  = {|rs1_data[15:4], rs1_data[3:0]};
956 
           shift_filler   = {16{carry_flag}};
957 
 
958 
           ena_rd_low_byte  = 1'b1;
959 
           ena_rd_high_byte = 1'b1;
960 
           alu_result       = shift_out;
961 
           next_zero        = !(|alu_result);
962 
           next_negative    = alu_result[15];
963 
           next_carry       = |rs1_data ? shift_rollover : carry_flag;
964 
           next_overflow    = rd_data[15] ^ alu_result[15];
965 
         end
966 
 
967 
      // Instruction = CSR RD, RS, Op Code =  0 0 0 0 1 RD RS 1 0 0 1 1
968 
      // Logical Shift Right with Carry
969 
      // n = RS
970 
      // Cycles - P
971 
      {CONT, 16'b00001??????10011} :
972 
         begin
973 
           shift_ammount  = {|rs1_data[15:4], rs1_data[3:0]};
974 
           shift_filler   = {16{carry_flag}};
975 
 
976 
           ena_rd_low_byte  = 1'b1;
977 
           ena_rd_high_byte = 1'b1;
978 
           alu_result       = shift_out;
979 
           next_zero        = !(|alu_result);
980 
           next_negative    = alu_result[15];
981 
           next_carry       = |rs1_data ? shift_rollover : carry_flag;
982 
           next_overflow    = rd_data[15] ^ alu_result[15];
983 
         end
984 
 
985 
      // Instruction = LSL RD, RS, Op Code =  0 0 0 0 1 RD RS 1 0 1 0 0
986 
      // Logical Shift Left
987 
      // n = RS
988 
      // Cycles - P
989 
      {CONT, 16'b00001??????10100} :
990 
         begin
991 
           shift_left     = 1'b1;
992 
           shift_ammount  = {|rs1_data[15:4], rs1_data[3:0]};
993 
           shift_filler   = 16'h0000;
994 
 
995 
           ena_rd_low_byte  = 1'b1;
996 
           ena_rd_high_byte = 1'b1;
997 
           alu_result       = shift_out;
998 
           next_zero        = !(|alu_result);
999 
           next_negative    = alu_result[15];
1000 
           next_carry       = |rs1_data ? shift_rollover : carry_flag;
1001 
           next_overflow    = rd_data[15] ^ alu_result[15];
1002 
         end
1003 
 
1004 
      // Instruction = LSR RD, RS, Op Code =  0 0 0 0 1 RD RS 1 0 1 0 1
1005 
      // Logical Shift Right
1006 
      // n = RS
1007 
      // Cycles - P
1008 
      {CONT, 16'b00001??????10101} :
1009 
         begin
1010 
           shift_ammount  = {|rs1_data[15:4], rs1_data[3:0]};
1011 
           shift_filler   = 16'h0000;
1012 
 
1013 
           ena_rd_low_byte  = 1'b1;
1014 
           ena_rd_high_byte = 1'b1;
1015 
           alu_result       = shift_out;
1016 
           next_zero        = !(|alu_result);
1017 
           next_negative    = alu_result[15];
1018 
           next_carry       = |rs1_data ? shift_rollover : carry_flag;
1019 
           next_overflow    = rd_data[15] ^ alu_result[15];
1020 
         end
1021 
 
1022 
      // Instruction = ROL RD, RS, Op Code =  0 0 0 0 1 RD RS 1 0 1 1 0
1023 
      // Rotate Left
1024 
      // n = RS
1025 
      // Cycles - P
1026 
      {CONT, 16'b00001??????10110} :
1027 
         begin
1028 
           shift_left     = 1'b1;
1029 
           shift_ammount  = {1'b0, rs1_data[3:0]};
1030 
           shift_filler   = rd_data;
1031 
 
1032 
           ena_rd_low_byte  = 1'b1;
1033 
           ena_rd_high_byte = 1'b1;
1034 
           alu_result       = shift_out;
1035 
           next_zero        = !(|alu_result);
1036 
           next_negative    = alu_result[15];
1037 
           next_overflow    = 1'b0;
1038 
         end
1039 
 
1040 
      // Instruction = ROR RD, RS, Op Code =  0 0 0 0 1 RD RS 1 0 1 1 1
1041 
      // Rotate Right
1042 
      // n = RS
1043 
      // Cycles - P
1044 
      {CONT, 16'b00001??????10111} :
1045 
         begin
1046 
           shift_ammount  = {1'b0, rs1_data[3:0]};
1047 
           shift_filler   = rd_data;
1048 
 
1049 
           ena_rd_low_byte  = 1'b1;
1050 
           ena_rd_high_byte = 1'b1;
1051 
           alu_result       = shift_out;
1052 
           next_zero        = !(|alu_result);
1053 
           next_negative    = alu_result[15];
1054 
           next_overflow    = 1'b0;
1055 
         end
1056 
 
1057 
      // -----------------------------------------------------------------------
1058 
      // Instruction Group -- Shift instructions immediate
1059 
      // -----------------------------------------------------------------------
1060 
 
1061 
      // Instruction = ASR RD, #IMM4, Op Code =  0 0 0 0 1 RD IMM4 1 0 0 1
1062 
      // ASR - Arithmetic Shift Right
1063 
      // n = IMM4
1064 
      // Cycles - P
1065 
      {CONT, 16'b00001???????1001} :
1066 
         begin
1067 
           shift_ammount  = {!(|op_code[7:4]), op_code[7:4]};
1068 
           shift_filler   = {16{rd_data[15]}};
1069 12 rehayes 
 
1070 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1071 
           ena_rd_high_byte = 1'b1;
1072 
           alu_result       = shift_out;
1073 
           next_zero        = !(|alu_result);
1074 
           next_negative    = alu_result[15];
1075 
           next_carry       = shift_rollover;
1076 
           next_overflow    = rd_data[15] ^ alu_result[15];  // Table and text disagree
1077 
         end
1078 
 
1079 
      // Instruction = CSL RD, #IMM4, Op Code =  0 0 0 0 1 RD IMM4 1 0 1 0
1080 
      // CSL - Logical Shift Left with Carry
1081 
      // n = IMM4
1082 
      // Cycles - P
1083 
      {CONT, 16'b00001???????1010} :
1084 
         begin
1085 
           shift_left     = 1'b1;
1086 
           shift_ammount  = {!(|op_code[7:4]), op_code[7:4]};
1087 
           shift_filler   = {16{carry_flag}};
1088 12 rehayes 
 
1089 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1090 
           ena_rd_high_byte = 1'b1;
1091 
           alu_result       = shift_out;
1092 
           next_zero        = !(|alu_result);
1093 
           next_negative    = alu_result[15];
1094 
           next_carry       = shift_rollover;
1095 
           next_overflow    = rd_data[15] ^ alu_result[15];
1096 
         end
1097 
 
1098 
      // Instruction = CSR RD, #IMM4, Op Code =  0 0 0 0 1 RD IMM4 1 0 1 1
1099 
      // CSR - Logical Shift Right with Carry
1100 
      // n = IMM4
1101 
      // Cycles - P
1102 
      {CONT, 16'b00001???????1011} :
1103 
         begin
1104 
           shift_ammount  = {!(|op_code[7:4]), op_code[7:4]};
1105 
           shift_filler   = {16{carry_flag}};
1106 
 
1107 
           ena_rd_low_byte  = 1'b1;
1108 
           ena_rd_high_byte = 1'b1;
1109 
           alu_result       = shift_out;
1110 
           next_zero        = !(|alu_result);
1111 
           next_negative    = alu_result[15];
1112 
           next_carry       = shift_rollover;
1113 
           next_overflow    = rd_data[15] ^ alu_result[15];
1114 
         end
1115 
 
1116 
      // Instruction = LSL RD, #IMM4, Op Code =  0 0 0 0 1 RD IMM4 1 1 0 0
1117 
      // LSL - Logical Shift Left
1118 
      // n = IMM4
1119 
      // Cycles - P
1120 
      {CONT, 16'b00001???????1100} :
1121 
         begin
1122 
           shift_left     = 1'b1;
1123 
           shift_ammount  = {!(|op_code[7:4]), op_code[7:4]};
1124 
           shift_filler   = 16'h0000;
1125 12 rehayes 
 
1126 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1127 
           ena_rd_high_byte = 1'b1;
1128 
           alu_result       = shift_out;
1129 
           next_zero        = !(|alu_result);
1130 
           next_negative    = alu_result[15];
1131 
           next_carry       = shift_rollover;
1132 
           next_overflow    = rd_data[15] ^ alu_result[15];
1133 
         end
1134 
 
1135 
      // Instruction = LSR RD, #IMM4, Op Code =  0 0 0 0 1 RD IMM4 1 1 0 1
1136 
      // LSR - Logical Shift Right
1137 
      // n = IMM4
1138 
      // Cycles - P
1139 
      {CONT, 16'b00001???????1101} :
1140 
         begin
1141 
           shift_ammount  = {!(|op_code[7:4]), op_code[7:4]};
1142 
           shift_filler   = 16'h0000;
1143 12 rehayes 
 
1144 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1145 
           ena_rd_high_byte = 1'b1;
1146 
           alu_result       = shift_out;
1147 
           next_zero        = !(|alu_result);
1148 
           next_negative    = alu_result[15];
1149 
           next_carry       = shift_rollover;
1150 
           next_overflow    = rd_data[15] ^ alu_result[15];
1151 
         end
1152 
 
1153 
      // Instruction = ROL RD, #IMM4, Op Code =  0 0 0 0 1 RD IMM4 1 1 1 0
1154 
      // ROL - Rotate Left
1155 
      // n = IMM4
1156 
      // Cycles - P
1157 
      {CONT, 16'b00001???????1110} :
1158 
         begin
1159 
           shift_left     = 1'b1;
1160 
           shift_ammount  = {1'b0, op_code[7:4]};
1161 
           shift_filler   = rd_data;
1162 12 rehayes 
 
1163 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1164 
           ena_rd_high_byte = 1'b1;
1165 
           alu_result       = shift_out;
1166 
           next_zero        = !(|alu_result);
1167 
           next_negative    = alu_result[15];
1168 
           next_overflow    = 1'b0;
1169 
         end
1170 
 
1171 
      // Instruction = ROR RD, #IMM4, Op Code =  0 0 0 0 1 RD IMM4 1 1 1 1
1172 
      // ROR - Rotate Right
1173 
      // n = IMM4
1174 
      // Cycles - P
1175 
      {CONT, 16'b00001???????1111} :
1176 
         begin
1177 
           shift_ammount  = {1'b0, op_code[7:4]};
1178 
           shift_filler   = rd_data;
1179 12 rehayes 
 
1180 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1181 
           ena_rd_high_byte = 1'b1;
1182 
           alu_result       = shift_out;
1183 
           next_zero        = !(|alu_result);
1184 
           next_negative    = alu_result[15];
1185 
           next_overflow    = 1'b0;
1186 
         end
1187 
 
1188 
      // -----------------------------------------------------------------------
1189 
      // Instruction Group -- Logical Triadic
1190 
      // -----------------------------------------------------------------------
1191 
 
1192 
      // Instruction = AND RD, RS1, RS2, Op Code =  0 0 0 1 0 RD RS1 RS2 0 0
1193 
      // AND - Logical AND
1194 
      // RS1 & RS2 => RD
1195 
      // Cycles - P
1196 
      {CONT, 16'b00010?????????00} :
1197 
         begin
1198 
           ena_rd_low_byte  = 1'b1;
1199 
           ena_rd_high_byte = 1'b1;
1200 
 
1201 
           alu_result    = rs1_data & rs2_data;
1202 
           next_zero     = !(|alu_result);
1203 
           next_negative = alu_result[15];
1204 
           next_overflow = 1'b0;
1205 
         end
1206 
 
1207 
      // Instruction = OR RD, RS1, RS2, Op Code =  0 0 0 1 0 RD RS1 RS2 1 0
1208 
      // OR - Logical OR
1209 
      // RS1 | RS2 => RD
1210 
      // Cycles - P
1211 
      {CONT, 16'b00010?????????10} :
1212 
         begin
1213 
           ena_rd_low_byte  = 1'b1;
1214 
           ena_rd_high_byte = 1'b1;
1215 
 
1216 
           alu_result    = rs1_data | rs2_data;
1217 
           next_zero     = !(|alu_result);
1218 
           next_negative = alu_result[15];
1219 
           next_overflow = 1'b0;
1220 
          end
1221 
 
1222 
      // Instruction = XNOR RD, RS1, RS2, Op Code =  0 0 0 1 0 RD RS1 RS2 1 1
1223 
      // XNOR - Logical Exclusive NOR
1224 
      // ~(RS1 ^ RS2) => RD
1225 
      // Cycles - P
1226 
      {CONT, 16'b00010?????????11} :
1227 
         begin
1228 
           ena_rd_low_byte  = 1'b1;
1229 
           ena_rd_high_byte = 1'b1;
1230 
 
1231 
           alu_result    = ~(rs1_data ^ rs2_data);
1232 
           next_zero     = !(|alu_result);
1233 
           next_negative = alu_result[15];
1234 
           next_overflow = 1'b0;
1235 
         end
1236 
 
1237 
      // -----------------------------------------------------------------------
1238 
      // Instruction Group -- Arithmetic Triadic
1239 
      // -----------------------------------------------------------------------
1240 
 
1241 
      // Instruction = SUB RD, RS1, RS2, Op Code =  0 0 0 1 1 RD RS1 RS2 0 0
1242 
      // SUB - Subtract without Carry
1243 
      // RS1 - RS2 => RD
1244 
      // Cycles - P
1245 
      {CONT, 16'b00011?????????00} :
1246 
         begin
1247 
           ena_rd_low_byte  = 1'b1;
1248 
           ena_rd_high_byte = 1'b1;
1249 
 
1250 
           {next_carry, alu_result}    = rs1_data - rs2_data;
1251 
           next_zero     = !(|alu_result);
1252 
           next_negative = alu_result[15];
1253 
           next_overflow = (rs1_data[15] && !rs2_data[15] && !alu_result[15]) || (!rs1_data[15] && rs2_data[15] && alu_result[15]);
1254 
         end
1255 
 
1256 
      // Instruction = SBC RD, RS1, RS2, Op Code =  0 0 0 1 1 RD RS1 RS2 0 1
1257 
      // SBC - Subtract with Carry
1258 
      // RS1 - RS2 - C => RD
1259 
      // Cycles - P
1260 
      {CONT, 16'b00011?????????01} :
1261 
         begin
1262 
           ena_rd_low_byte  = 1'b1;
1263 
           ena_rd_high_byte = 1'b1;
1264 
 
1265 
           {next_carry, alu_result}    = rs1_data - rs2_data - {15'b0, carry_flag};
1266 47 rehayes 
           next_zero     = !(|alu_result) && zero_flag;
1267 2 rehayes 
           next_negative = alu_result[15];
1268 
           next_overflow = (rs1_data[15] && !rs2_data[15] && !alu_result[15]) || (!rs1_data[15] && rs2_data[15] && alu_result[15]);
1269 
         end
1270 
 
1271 
      // Instruction = ADD RD, RS1, RS2, Op Code =  0 0 0 1 1 RD RS1 RS2 1 0
1272 
      // ADD - ADD without carry
1273 
      // RS1 + RS2 => RD
1274 
      // Cycles - P
1275 
      {CONT, 16'b00011?????????10} :
1276 
         begin
1277 
           ena_rd_low_byte  = 1'b1;
1278 
           ena_rd_high_byte = 1'b1;
1279 
 
1280 
           {next_carry, alu_result}    = rs1_data + rs2_data;
1281 
           next_zero     = !(|alu_result);
1282 
           next_negative = alu_result[15];
1283 
           next_overflow = (rs1_data[15] && rs2_data[15] && !alu_result[15]) || (!rs1_data[15] && !rs2_data[15] && alu_result[15]);
1284 
         end
1285 
 
1286 
      // Instruction = ADC RD, RS1, RS2, Op Code =  0 0 0 1 1 RD RS1 RS2 1 1
1287 
      // ADC - add with carry
1288 
      // RS1 + RS2 + C => RD
1289 
      // Cycles - P
1290 
      {CONT, 16'b00011?????????11} :
1291 
         begin
1292 
           ena_rd_low_byte  = 1'b1;
1293 
           ena_rd_high_byte = 1'b1;
1294 
 
1295 
           {next_carry, alu_result}    = rs1_data + rs2_data + {15'b0, carry_flag};
1296 47 rehayes 
           next_zero     = !(|alu_result) && zero_flag;
1297 2 rehayes 
           next_negative = alu_result[15];
1298 
           next_overflow = (rs1_data[15] && rs2_data[15] && !alu_result[15]) || (!rs1_data[15] && !rs2_data[15] && alu_result[15]);
1299 
         end
1300 
 
1301 
      // -----------------------------------------------------------------------
1302 
      // Instruction Group -- Branches
1303 
      // -----------------------------------------------------------------------
1304 
 
1305 
      // Instruction = BCC REL9, Op Code =  0 0 1 0 0 0 0 REL9
1306 
      // Branch if Carry Cleared
1307 
      // If C = 0, then PC + $0002 + (REL9 << 1) => PC
1308 
      // Cycles - PP/P
1309 
      {CONT, 16'b0010000?????????} :
1310 89 rehayes 
         if (!carry_flag)
1311 
           begin
1312 
             next_cpu_state = S_STALL;
1313 
             load_next_inst = 1'b0;
1314 
             pc_incr_mux    = jump_offset;
1315 
             next_pc        = pc_sum;  // There is a race condition when the default declaration is used
1316 
           end
1317 2 rehayes 
 
1318 
      // Instruction = BCS REL9, Op Code =  0 0 1 0 0 0 1 REL9
1319 
      // Branch if Carry Set
1320 
      // If C = 1, then PC + $0002 + (REL9 << 1) => PC
1321 
      // Cycles - PP/P
1322 
      {CONT, 16'b0010001?????????} :
1323 89 rehayes 
         if (carry_flag)
1324 
           begin
1325 
             next_cpu_state = S_STALL;
1326 
             load_next_inst = 1'b0;
1327 
             pc_incr_mux    = jump_offset;
1328 
             next_pc        = pc_sum;
1329 
           end
1330 2 rehayes 
 
1331 
      // Instruction = BNE REL9, Op Code =  0 0 1 0 0 1 0 REL9
1332 
      // Branch if Not Equal
1333 
      // If Z = 0, then PC + $0002 + (REL9 << 1) => PC
1334 
      // Cycles - PP/P
1335 
      {CONT, 16'b0010010?????????} :
1336 89 rehayes 
         if (!zero_flag)
1337 
           begin
1338 
             next_cpu_state = S_STALL;
1339 
             load_next_inst = 1'b0;
1340 
             pc_incr_mux    = jump_offset;
1341 
             next_pc        = pc_sum;
1342 
           end
1343 2 rehayes 
 
1344 
      // Instruction = BEQ REL9, Op Code =  0 0 1 0 0 1 1 REL9
1345 
      // Branch if Equal
1346 
      // If Z = 1, then PC + $0002 + (REL9 << 1) => PC
1347 
      // Cycles - PP/P
1348 
      {CONT, 16'b0010011?????????} :
1349 89 rehayes 
         if (zero_flag)
1350 
           begin
1351 
             next_cpu_state = S_STALL;
1352 
             load_next_inst = 1'b0;
1353 
             pc_incr_mux    = jump_offset;
1354 
             next_pc        = pc_sum;
1355 
           end
1356 2 rehayes 
 
1357 
      // Instruction = BPL REL9, Op Code =  0 0 1 0 1 0 0 REL9
1358 
      // Branch if Plus
1359 
      // If N = 0, then PC + $0002 + (REL9 << 1) => PC
1360 
      // Cycles - PP/P
1361 
      {CONT, 16'b0010100?????????} :
1362 89 rehayes 
         if (!negative_flag)
1363 
           begin
1364 
             next_cpu_state = S_STALL;
1365 
             load_next_inst = 1'b0;
1366 
             pc_incr_mux    = jump_offset;
1367 
             next_pc        = pc_sum;
1368 
           end
1369 2 rehayes 
 
1370 
      // Instruction = BMI REL9, Op Code =  0 0 1 0 1 0 1 REL9
1371 
      // Branch if Minus
1372 
      // If N = 1, then PC + $0002 + (REL9 << 1) => PC
1373 
      // Cycles - PP/P
1374 
      {CONT, 16'b0010101?????????} :
1375 89 rehayes 
         if (negative_flag)
1376 
           begin
1377 
             next_cpu_state = S_STALL;
1378 
             load_next_inst = 1'b0;
1379 
             pc_incr_mux    = jump_offset;
1380 
             next_pc        = pc_sum;
1381 
           end
1382 2 rehayes 
 
1383 
      // Instruction = BVC REL9, Op Code =  0 0 1 0 1 1 0 REL9
1384 
      // Branch if Overflow Cleared
1385 
      // If V = 0, then PC + $0002 + (REL9 << 1) => PC
1386 
      // Cycles - PP/P
1387 
      {CONT, 16'b0010110?????????} :
1388 89 rehayes 
         if (!overflow_flag)
1389 
           begin
1390 
             next_cpu_state = S_STALL;
1391 
             load_next_inst = 1'b0;
1392 
             pc_incr_mux    = jump_offset;
1393 
             next_pc        = pc_sum;
1394 
           end
1395 2 rehayes 
 
1396 
      // Instruction = BVS REL9, Op Code =  0 0 1 0 1 1 1 REL9
1397 
      // Branch if Overflow Set
1398 
      // If V = 1, then PC + $0002 + (REL9 << 1) => PC
1399 
      // Cycles - PP/P
1400 
      {CONT, 16'b0010111?????????} :
1401 89 rehayes 
         if (overflow_flag)
1402 
           begin
1403 
             next_cpu_state = S_STALL;
1404 
             load_next_inst = 1'b0;
1405 
             pc_incr_mux    = jump_offset;
1406 
             next_pc        = pc_sum;
1407 
           end
1408 2 rehayes 
 
1409 
      // Instruction = BHI REL9, Op Code =  0 0 1 1 0 0 0 REL9
1410 
      // Branch if Higher
1411 
      // If C | Z = 0, then PC + $0002 + (REL9 << 1) => PC
1412 
      // Cycles - PP/P
1413 
      {CONT, 16'b0011000?????????} :
1414 89 rehayes 
         if (!(carry_flag || zero_flag))
1415 
           begin
1416 
             next_cpu_state = S_STALL;
1417 
             load_next_inst = 1'b0;
1418 
             pc_incr_mux    = jump_offset;
1419 
             next_pc        = pc_sum;
1420 
           end
1421 2 rehayes 
 
1422 
      // Instruction = BLS REL9, Op Code =  0 0 1 1 0 0 1 REL9
1423 
      // Branch if Lower or Same
1424 
      // If C | Z = 1, then PC + $0002 + (REL9 << 1) => PC
1425 
      // Cycles - PP/P
1426 
      {CONT, 16'b0011001?????????} :
1427 89 rehayes 
         if (carry_flag || zero_flag)
1428 
           begin
1429 
             next_cpu_state = S_STALL;
1430 
             load_next_inst = 1'b0;
1431 
             pc_incr_mux    = jump_offset;
1432 
             next_pc        = pc_sum;
1433 
           end
1434 2 rehayes 
 
1435 
      // Instruction = BGE REL9, Op Code =  0 0 1 1 0 1 0 REL9
1436 
      // Branch if Greater than or Equal to Zero
1437 
      // If N ^ V = 0, then PC + $0002 + (REL9 << 1) => PC
1438 
      // Cycles - PP/P
1439 
      {CONT, 16'b0011010?????????} :
1440 89 rehayes 
         if (!(negative_flag ^ overflow_flag))
1441 
           begin
1442 
             next_cpu_state = S_STALL;
1443 
             load_next_inst = 1'b0;
1444 
             pc_incr_mux    = jump_offset;
1445 
             next_pc        = pc_sum;
1446 
           end
1447 2 rehayes 
 
1448 
      // Instruction = BLT REL9, Op Code =  0 0 1 1 0 1 1 REL9
1449 
      // Branch if Lower than Zero
1450 
      // If N ^ V = 1, then PC + $0002 + (REL9 << 1) => PC
1451 
      // Cycles - PP/P
1452 
      {CONT, 16'b0011011?????????} :
1453 89 rehayes 
         if (negative_flag ^ overflow_flag)
1454 
           begin
1455 
             next_cpu_state = S_STALL;
1456 
             load_next_inst = 1'b0;
1457 
             pc_incr_mux    = jump_offset;
1458 
             next_pc        = pc_sum;
1459 
           end
1460 2 rehayes 
 
1461 
      // Instruction = BGT REL9, Op Code =  0 0 1 1 1 0 0 REL9
1462 
      // Branch if Greater than Zero
1463 
      // If Z | (N ^ V) = 0, then PC + $0002 + (REL9 << 1) => PC
1464 
      // Cycles - PP/P
1465 
      {CONT, 16'b0011100?????????} :
1466 89 rehayes 
         if (!(zero_flag || (negative_flag ^ overflow_flag)))
1467 
           begin
1468 
             next_cpu_state = S_STALL;
1469 
             load_next_inst = 1'b0;
1470 
             pc_incr_mux    = jump_offset;
1471 
             next_pc        = pc_sum;
1472 
           end
1473 2 rehayes 
 
1474 
      // Instruction = BLE REL9, Op Code =  0 0 1 1 1 0 1 REL9
1475 
      // Branch if Less or Equal to Zero
1476 
      // If Z | (N ^ V) = 1, then PC + $0002 + (REL9 << 1) => PC
1477 
      // Cycles - PP/P
1478 
      {CONT, 16'b0011101?????????} :
1479 89 rehayes 
         if (zero_flag || (negative_flag ^ overflow_flag))
1480 
           begin
1481 
             next_cpu_state = S_STALL;
1482 
             load_next_inst = 1'b0;
1483 
             pc_incr_mux    = jump_offset;
1484 
             next_pc        = pc_sum;
1485 
           end
1486 2 rehayes 
 
1487 
      // Instruction = BRA REL10, Op Code =  0 0 1 1 1 1 REL10
1488 
      // Branch Always, signed offset
1489 
      // PC + $0002 + (REL10 << 1) => PC
1490 
      // Cycles - PP
1491 
      {CONT, 16'b001111??????????} :
1492 
         begin
1493 5 rehayes 
           next_cpu_state = S_STALL;
1494 2 rehayes 
           load_next_inst = 1'b0;
1495 40 rehayes 
           pc_incr_mux    = bra_offset;
1496 
           next_pc        = pc_sum;
1497 2 rehayes 
         end
1498 
 
1499 
 
1500 
      // -----------------------------------------------------------------------
1501 
      // Instruction Group -- Load and Store Instructions
1502 
      // -----------------------------------------------------------------------
1503 
 
1504 
      // Instruction = LDB RD, (RB, #OFFS5), Op Code =  0 1 0 0 0 RD RB OFFS5
1505 
      // Load Byte from Memory, unsigned offset
1506 
      // M[RB, #OFFS5] => RD.L; $00 => RD.H
1507 
      // RB field == RS1 field
1508 
      // Cycles - Pr
1509 
      {CONT, 16'b01000???????????} :
1510 
         begin
1511 40 rehayes 
           next_cpu_state = B_LOAD;
1512 2 rehayes 
           load_next_inst = 1'b0;
1513 40 rehayes 
           pc_incr_mux    = 16'h0000;
1514 
           next_pc        = pc_sum;
1515 2 rehayes 
           data_access    = 1'b1;
1516 
           data_address   = rs1_data + {11'b0, op_code[4:0]};
1517 
         end
1518 
 
1519 
      // Instruction = LDW RD, (RB, #OFFS5), Op Code =  0 1 0 0 1 RD RB OFFS5
1520 
      // Load Word from Memory, unsigned offset
1521 
      // M[RB, #OFFS5] => RD
1522 
      // RB field == RS1 field
1523 
      // Cycles - PR
1524 
      {CONT, 16'b01001???????????} :
1525 
         begin
1526 40 rehayes 
           next_cpu_state = W_LOAD;
1527 2 rehayes 
           load_next_inst = 1'b0;
1528 40 rehayes 
           pc_incr_mux    = 16'h0000;
1529 
           next_pc        = pc_sum;
1530 2 rehayes 
           data_access    = 1'b1;
1531 
           data_address   = rs1_data + {11'b0, op_code[4:0]};
1532 
           data_word_op   = 1'b1;
1533 
         end
1534 
 
1535 
      // Instruction = STB RS, (RB, #OFFS5), Op Code =  0 1 0 1 0 RS RB OFFS5
1536 
      // Store Byte to Memory, unsigned offset
1537 
      // RS.L => M[RB, #OFFS5]
1538 
      // RS field == RD fieild, RB field == RS1 field
1539 
      // Cycles - Pw
1540 
      {CONT, 16'b01010???????????} :
1541 
         begin
1542 5 rehayes 
           next_cpu_state = S_STALL;
1543 2 rehayes 
           load_next_inst = 1'b0;
1544 40 rehayes 
           pc_incr_mux    = 16'h0000;
1545 
           next_pc        = pc_sum;
1546 2 rehayes 
           data_access    = 1'b1;
1547 
           data_write     = 1'b1;
1548 
           data_address   = rs1_data + {11'b0, op_code[4:0]};
1549 
         end
1550 
 
1551 
      // Instruction = STW RS, (RB, #OFFS5), Op Code =  0 1 0 1 1 RS RB OFFS5
1552 
      // Store Word to Memory, unsigned offset
1553 
      // RS => M[RB, #OFFS5]
1554 
      // RS field == RD fieild, RB field == RS1 field
1555 
      // Cycles - PW
1556 
      {CONT, 16'b01011???????????} :
1557 
         begin
1558 5 rehayes 
           next_cpu_state = S_STALL;
1559 2 rehayes 
           load_next_inst = 1'b0;
1560 40 rehayes 
           pc_incr_mux    = 16'h0000;
1561 
           next_pc        = pc_sum;
1562 2 rehayes 
           data_access    = 1'b1;
1563 
           data_write     = 1'b1;
1564 
           data_address   = rs1_data + {11'b0, op_code[4:0]};
1565 
           data_word_op   = 1'b1;
1566 
         end
1567 
 
1568 
      // Instruction = LDB RD, (RB, RI), Op Code =  0 1 1 0 0 RD RB RI 0 0
1569 
      // Load Byte from Memory
1570 
      // M[RB, RI] => RD.L; $00 => RD.H
1571 
      // RB field == RS1 field, RI field == RS2 field
1572 
      // Cycles - Pr
1573 
      {CONT, 16'b01100?????????00} :
1574 
         begin
1575 40 rehayes 
           next_cpu_state = B_LOAD;
1576 2 rehayes 
           load_next_inst = 1'b0;
1577 40 rehayes 
           pc_incr_mux    = 16'h0000;
1578 
           next_pc        = pc_sum;
1579 2 rehayes 
           data_access    = 1'b1;
1580 
           data_address   = rs1_data + rs2_data;
1581 
         end
1582 
 
1583 
      // Instruction = LDW RD, (RB, RI), Op Code =  0 1 1 0 1 RD RB RI 0 0
1584 
      // Load Word from Memory
1585 
      // M[RB, RI] => RD
1586 
      // RB field == RS1 field, RI field == RS2 field
1587 
      // Cycles - PR
1588 
      {CONT, 16'b01101?????????00} :
1589 
         begin
1590 40 rehayes 
           next_cpu_state = W_LOAD;
1591 2 rehayes 
           load_next_inst = 1'b0;
1592 40 rehayes 
           pc_incr_mux    = 16'h0000;
1593 
           next_pc        = pc_sum;
1594 2 rehayes 
           data_access    = 1'b1;
1595 
           data_address   = rs1_data + rs2_data;
1596 
           data_word_op   = 1'b1;
1597 
         end
1598 
 
1599 
      // Instruction = STB RS, (RB, RI), Op Code =  0 1 1 1 0 RS RB RI 0 0
1600 
      // RS.L => M[RB, RI]
1601 
      // Store Byte to Memory
1602 
      // RS field == RD fieild, RB field == RS1 field, RI field == RS2 field
1603 
      // Cycles - Pw
1604 
      {CONT, 16'b01110?????????00} :
1605 
         begin
1606 5 rehayes 
           next_cpu_state = S_STALL;
1607 2 rehayes 
           load_next_inst = 1'b0;
1608 40 rehayes 
           pc_incr_mux    = 16'h0000;
1609 
           next_pc        = pc_sum;
1610 2 rehayes 
           data_access    = 1'b1;
1611 
           data_write     = 1'b1;
1612 
           data_address   = rs1_data + rs2_data;
1613 
         end
1614 
 
1615 
      // Instruction = STW RS, (RB, RI), Op Code =  0 1 1 1 1 RS RB RI 0 0
1616 
      // Store Word to Memory
1617 
      // RS => M[RB, RI]
1618 
      // RS field == RD fieild, RB field == RS1 field, RI field == RS2 field
1619 
      // Cycles - PW
1620 
      {CONT, 16'b01111?????????00} :
1621 
         begin
1622 5 rehayes 
           next_cpu_state = S_STALL;
1623 2 rehayes 
           load_next_inst = 1'b0;
1624 40 rehayes 
           pc_incr_mux    = 16'h0000;
1625 
           next_pc        = pc_sum;
1626 2 rehayes 
           data_access    = 1'b1;
1627 
           data_write     = 1'b1;
1628 
           data_address   = rs1_data + rs2_data;
1629 
           data_word_op   = 1'b1;
1630 
         end
1631 
 
1632 
      // Instruction = LDB RD, (RB, RI+), Op Code =  0 1 1 0 0 RD RB RI 0 1
1633 
      // Load Byte from Memory
1634 
      // M[RB, RI] => RD.L; $00 => RD.H; RI+1 => RI
1635 
      //  If the same general purpose register is used as index (RI) and destination register (RD),
1636 
      //  the content of the register will not be incremented after the data move: M[RB, RI] => RD.L; $00 => RD.H
1637 
      // RB field == RS1 field, RI field == RS2 field
1638 
      // Cycles - Pr
1639 
      {CONT, 16'b01100?????????01} :
1640 
         begin
1641 40 rehayes 
           next_cpu_state   = B_LOAD;
1642 2 rehayes 
           load_next_inst   = 1'b0;
1643 40 rehayes 
           pc_incr_mux      = 16'h0000;
1644 
           next_pc          = pc_sum;
1645 2 rehayes 
           data_access      = 1'b1;
1646 
           data_address     = rs1_data + rs2_data;
1647 
           alu_result       = rs2_data + 16'h0001;
1648 12 rehayes 
           sel_rd_field     = 1'b0;
1649 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1650 
           ena_rd_high_byte = 1'b1;
1651 
         end
1652 
 
1653 
      // Instruction = LDW RD, (RB, RI+), Op Code =  0 1 1 0 1 RD RB RI 0 1
1654 
      // Load Word from Memory
1655 
      // M[RB, RI] => RD; RI+2 => RI
1656 
      //  If the same general purpose register is used as index (RI) and destination register (RD),
1657 
      //  the content of the register will not be incremented after the data move: M[RB, RI] => RD
1658 
      // RB field == RS1 field, RI field == RS2 field
1659 
      // Cycles - PR
1660 
      {CONT, 16'b01101?????????01} :
1661 
         begin
1662 40 rehayes 
           next_cpu_state   = W_LOAD;
1663 2 rehayes 
           load_next_inst   = 1'b0;
1664 40 rehayes 
           pc_incr_mux      = 16'h0000;
1665 
           next_pc          = pc_sum;
1666 2 rehayes 
           data_access      = 1'b1;
1667 
           data_address     = rs1_data + rs2_data;
1668 
           data_word_op     = 1'b1;
1669 
           alu_result       = rs2_data + 16'h0002;
1670 12 rehayes 
           sel_rd_field     = 1'b0;
1671 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1672 
           ena_rd_high_byte = 1'b1;
1673 
         end
1674 
 
1675 
      // Instruction = STB RS, (RB, RI+), Op Code =  0 1 1 1 0 RS RB RI 0 1
1676 
      // Store Byte to Memory
1677 
      // RS.L => M[RB, RI]; RI+1 => RI
1678 
      // RS field == RD fieild, RB field == RS1 field, RI field == RS2 field
1679 
      // Cycles - Pw
1680 
      {CONT, 16'b01110?????????01} :
1681 
         begin
1682 5 rehayes 
           next_cpu_state   = S_STALL;
1683 2 rehayes 
           load_next_inst   = 1'b0;
1684 40 rehayes 
           pc_incr_mux      = 16'h0000;
1685 
           next_pc          = pc_sum;
1686 2 rehayes 
           data_access      = 1'b1;
1687 
           data_write       = 1'b1;
1688 
           data_address     = rs1_data + rs2_data;
1689 
           alu_result       = rs2_data + 16'h0001;
1690 12 rehayes 
           sel_rd_field     = 1'b0;
1691 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1692 
           ena_rd_high_byte = 1'b1;
1693 
         end
1694 
 
1695 
      // Instruction = STW RS, (RB, RI+), Op Code =  0 1 1 1 1 RS RB RI 0 1
1696 
      // Store Word to Memory
1697 
      // RS => M[RB, RI]; RI+2 => RI
1698 
      // RS field == RD fieild, RB field == RS1 field, RI field == RS2 field
1699 
      // Cycles - PW
1700 
      {CONT, 16'b01111?????????01} :
1701 
         begin
1702 5 rehayes 
           next_cpu_state   = S_STALL;
1703 2 rehayes 
           load_next_inst   = 1'b0;
1704 40 rehayes 
           pc_incr_mux      = 16'h0000;
1705 
           next_pc          = pc_sum;
1706 2 rehayes 
           data_access      = 1'b1;
1707 
           data_write       = 1'b1;
1708 
           data_word_op     = 1'b1;
1709 
           data_address     = rs1_data + rs2_data;
1710 
           alu_result       = rs2_data + 16'h0002;
1711 12 rehayes 
           sel_rd_field     = 1'b0;
1712 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1713 
           ena_rd_high_byte = 1'b1;
1714 
         end
1715 
 
1716 
      // Instruction = LDB RD, (RB, -RI), Op Code =  0 1 1 0 0 RD RB RI 1 0
1717 
      // Load Byte from Memory
1718 
      // RI-1 => RI; M[RS, RI]  => RD.L; $00 => RD.H
1719 
      // RB field == RS1 field, RI field == RS2 field
1720 
      // Cycles - Pr
1721 
      {CONT, 16'b01100?????????10} :
1722 
         begin
1723 40 rehayes 
           next_cpu_state   = B_LOAD;
1724 2 rehayes 
           load_next_inst   = 1'b0;
1725 40 rehayes 
           pc_incr_mux      = 16'h0000;
1726 
           next_pc          = pc_sum;
1727 2 rehayes 
           data_access      = 1'b1;
1728 
           alu_result       = rs2_data + 16'hffff;
1729 
           data_address     = rs1_data + alu_result;
1730 12 rehayes 
           sel_rd_field     = 1'b0;
1731 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1732 
           ena_rd_high_byte = 1'b1;
1733 
         end
1734 
 
1735 
      // Instruction = LDW RD, (RB, -RI), Op Code =  0 1 1 0 1 RD RB RI 1 0
1736 
      // Load Word from Memory
1737 
      // RI-2 => RI; M[RS, RI] => RD
1738 
      // RB field == RS1 field, RI field == RS2 field
1739 
      // Cycles - PR
1740 
      {CONT, 16'b01101?????????10} :
1741 
         begin
1742 40 rehayes 
           next_cpu_state   = W_LOAD;
1743 2 rehayes 
           load_next_inst   = 1'b0;
1744 40 rehayes 
           pc_incr_mux      = 16'h0000;
1745 
           next_pc          = pc_sum;
1746 2 rehayes 
           data_access      = 1'b1;
1747 
           alu_result       = rs2_data + 16'hfffe;
1748 
           data_address     = rs1_data + alu_result;
1749 
           data_word_op     = 1'b1;
1750 12 rehayes 
           sel_rd_field     = 1'b0;
1751 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1752 
           ena_rd_high_byte = 1'b1;
1753 
         end
1754 
 
1755 
      // Instruction = STB RS, (RB, -RI), Op Code =  0 1 1 1 0 RS RB RI 1 0
1756 
      // Store Byte to Memory
1757 
      // RI-1 => RI; RS.L => M[RB, RI]
1758 
      //  If the same general purpose register is used as index (RI) and source register (RS),
1759 
      //  the unmodified content of the source register is written to the memory: RS.L => M[RB, RS-1]; RS-1 => RS
1760 
      // RS field == RD fieild, RB field == RS1 field, RI field == RS2 field
1761 
      // Cycles - Pw
1762 
      {CONT, 16'b01110?????????10} :
1763 
         begin
1764 5 rehayes 
           next_cpu_state   = S_STALL;
1765 2 rehayes 
           load_next_inst   = 1'b0;
1766 40 rehayes 
           pc_incr_mux      = 16'h0000;
1767 
           next_pc          = pc_sum;
1768 2 rehayes 
           data_access      = 1'b1;
1769 
           data_write       = 1'b1;
1770 
           alu_result       = rs2_data + 16'hffff;
1771 
           data_address     = rs1_data + alu_result;
1772 12 rehayes 
           sel_rd_field     = 1'b0;
1773 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1774 
           ena_rd_high_byte = 1'b1;
1775 
         end
1776 
 
1777 
      // Instruction = STW RS, (RB, -RI), Op Code =  0 1 1 1 1 RS RB RI 1 0
1778 
      // Store Word to Memory
1779 
      // RI-2 => RI; RS => M[RB, RI]
1780 
      //  If the same general purpose register is used as index (RI) and source register (RS),
1781 
      //  the unmodified content of the source register is written to the memory: RS => M[RB, RS-2]; RS-2 => RS
1782 
      // RS field == RD fieild, RB field == RS1 field, RI field == RS2 field
1783 
      // Cycles - PW
1784 
      {CONT, 16'b01111?????????10} :
1785 
         begin
1786 5 rehayes 
           next_cpu_state   = S_STALL;
1787 2 rehayes 
           load_next_inst   = 1'b0;
1788 40 rehayes 
           pc_incr_mux      = 16'h0000;
1789 
           next_pc          = pc_sum;
1790 2 rehayes 
           data_access      = 1'b1;
1791 
           data_write       = 1'b1;
1792 
           data_word_op     = 1'b1;
1793 
           alu_result       = rs2_data + 16'hfffe;
1794 
           data_address     = rs1_data + alu_result;
1795 12 rehayes 
           sel_rd_field     = 1'b0;
1796 2 rehayes 
           ena_rd_low_byte  = 1'b1;
1797 
           ena_rd_high_byte = 1'b1;
1798 
         end
1799 
 
1800 
      // -----------------------------------------------------------------------
1801 
      // Instruction Group -- Bit Field Instructions
1802 
      // -----------------------------------------------------------------------
1803 
 
1804 
      // Instruction = BFEXT RD, RS1, RS2, Op Code =  0 1 1 0 0 RD RS1 RS2 1 1
1805 
      // BFEXT - Bit Field Extract
1806 
      // RS1[(o+w):o] => RD[w:0]; 0 => RD[15:(w+1)]
1807 
      // Cycles - P
1808 
      {CONT, 16'b01100?????????11} :
1809 
         begin
1810 5 rehayes 
           ena_rd_low_byte  = 1'b1;
1811 2 rehayes 
           ena_rd_high_byte = 1'b1;
1812 
           shift_ammount  = {1'b0, rs2_data[3:0]};
1813 
           for (bfi = 0; bfi <= 15; bfi = bfi + 1)
1814 
             shift_in[bfi] = bf_mux_mask[bfi] ? rs1_data[bfi] : 1'b0;
1815 
 
1816 
           alu_result    = shift_out;
1817 
           next_zero     = !(|alu_result);
1818 
           next_negative = alu_result[15];
1819 
           next_overflow = 1'b0;
1820 
         end
1821 
 
1822 
      // Instruction = BFINS RD, RS1, RS2, Op Code =  0 1 1 0 1 RD RS1 RS2 1 1
1823 
      // BFINS - Bit Field Insert
1824 
      // RS1[w:0] => RD[(w+o):o
1825 
      // Cycles - P
1826 
      {CONT, 16'b01101?????????11} :
1827 
         begin
1828 
           ena_rd_low_byte  = 1'b1;
1829 
           ena_rd_high_byte = 1'b1;
1830 
           shift_left     = 1'b1;
1831 
           shift_ammount  = {1'b0, rs2_data[3:0]};
1832 
           shift_in       = rs1_data;
1833 
 
1834 
           for (bfi = 0; bfi <= 15; bfi = bfi + 1)
1835 
             alu_result[bfi] = bf_mux_mask[bfi] ? shift_out[bfi] : rd_data[bfi];
1836 
           next_zero     = !(|alu_result);
1837 
           next_negative = alu_result[15];
1838 
           next_overflow = 1'b0;
1839 
         end
1840 
 
1841 
      // Instruction = BFINSI RD, RS1, RS2, Op Code =  0 1 1 1 0 RD RS1 RS2 1 1
1842 
      // BFINSI - Bit Field Insert and Invert
1843 
      // !RS1[w:0] => RD[w+o:o]
1844 
      // Cycles - P
1845 
      {CONT, 16'b01110?????????11} :
1846 
         begin
1847 
           ena_rd_low_byte  = 1'b1;
1848 
           ena_rd_high_byte = 1'b1;
1849 
           shift_left     = 1'b1;
1850 
           shift_ammount  = {1'b0, rs2_data[3:0]};
1851 
           shift_in       = rs1_data;
1852 
 
1853 
           for (bfi = 0; bfi <= 15; bfi = bfi + 1)
1854 
             alu_result[bfi] = bf_mux_mask[bfi] ? !shift_out[bfi] : rd_data[bfi];
1855 
           next_zero     = !(|alu_result);
1856 
           next_negative = alu_result[15];
1857 
           next_overflow = 1'b0;
1858 
         end
1859 
 
1860 
      // Instruction = BFINSX RD, RS1, RS2, Op Code =  0 1 1 1 1 RD RS1 RS2 1 1
1861 
      // BFINSX - Bit Field Insert and XNOR
1862 
      // !(RS1[w:0] ^ RD[w+o:o]) => RD[w+o:o]
1863 
      // Cycles - P
1864 
      {CONT, 16'b01111?????????11} :
1865 
         begin
1866 
           ena_rd_low_byte  = 1'b1;
1867 
           ena_rd_high_byte = 1'b1;
1868 
           shift_left     = 1'b1;
1869 
           shift_ammount  = {1'b0, rs2_data[3:0]};
1870 
           shift_in       = rs1_data;
1871 
 
1872 26 rehayes 
           for (bfii = 0; bfii <= 15; bfii = bfii + 1)
1873 
             alu_result[bfii] = bf_mux_mask[bfii] ? !(shift_out[bfii] ^ rd_data[bfii]) : rd_data[bfii];
1874 2 rehayes 
           next_zero     = !(|alu_result);
1875 
           next_negative = alu_result[15];
1876 
           next_overflow = 1'b0;
1877 
        end
1878 
 
1879 
      // -----------------------------------------------------------------------
1880 
      // Instruction Group -- Logic Immediate Instructions
1881 
      // -----------------------------------------------------------------------
1882 
 
1883 
      // Instruction = ANDL RD, #IMM8, Op Code =  1 0 0 0 0 RD IMM8
1884 
      // AND - Logical AND
1885 
      // RD.L & IMM8 => RD.L
1886 
      // Cycles - P
1887 
      {CONT, 16'b10000???????????} :
1888 
         begin
1889 
           ena_rd_low_byte = 1'b1;
1890 
 
1891 
           alu_result    = rd_data & {8'b0, op_code[7:0]};
1892 
           next_zero     = !(|alu_result[7:0]);
1893 
           next_negative = alu_result[7];
1894 
           next_overflow = 1'b0;
1895 
         end
1896 
 
1897 
      // Instruction = ANDH RD, #IMM8, Op Code =  1 0 0 0 1 RD IMM8
1898 
      // AND - Logical AND
1899 
      // RD.H & IMM8 => RD.H
1900 
      // Cycles - P
1901 
      {CONT, 16'b10001???????????} :
1902 
         begin
1903 
           ena_rd_high_byte = 1'b1;
1904 
 
1905 
           alu_result    = rd_data & {op_code[7:0], 8'b0};
1906 
           next_zero     = !(|alu_result[15:8]);
1907 
           next_negative = alu_result[15];
1908 
           next_overflow = 1'b0;
1909 
         end
1910 
 
1911 
      // Instruction = BITL RD, #IMM8, Op Code =  1 0 0 1 0 RD IMM8
1912 
      // RD.L & IMM8 => NONE
1913 
      {CONT, 16'b10010???????????} :
1914 
         begin
1915 
 
1916 
           next_zero     = !(|(rd_data[7:0] & op_code[7:0]));
1917 
           next_negative = rd_data[7] && op_code[7];
1918 
           next_overflow = 1'b0;
1919 
         end
1920 
 
1921 
      // Instruction = BITH RD, #IMM8, Op Code =  1 0 0 1 1 RD IMM8
1922 
      // RD.H & IMM8 => NONE
1923 
      {CONT, 16'b10011???????????} :
1924 
         begin
1925 
 
1926 
           next_zero     = !(|(rd_data[15:8] & op_code[7:0]));
1927 
           next_negative = rd_data[15] && op_code[7];
1928 
           next_overflow = 1'b0;
1929 
         end
1930 
 
1931 
      // Instruction = ORL RD, #IMM8, Op Code =  1 0 1 0 0 RD IMM8
1932 
      // OR - Logical OR
1933 
      // RD.L | IMM8 => RD.L
1934 
      {CONT, 16'b10100???????????} :
1935 
         begin
1936 
           ena_rd_low_byte = 1'b1;
1937 
 
1938 
           alu_result    = rd_data | {8'b0, op_code[7:0]};
1939 
           next_zero     = !(|alu_result[7:0]);
1940 
           next_negative = alu_result[7];
1941 
           next_overflow = 1'b0;
1942 
         end
1943 
 
1944 
      // Instruction = ORH RD, #IMM8, Op Code =  1 0 1 0 1 RD IMM8
1945 
      // OR - Logical OR
1946 
      // RD.H | IMM8 => RD.H
1947 
      {CONT, 16'b10101???????????} :
1948 
         begin
1949 
           ena_rd_high_byte = 1'b1;
1950 
 
1951 
           alu_result    = rd_data | {op_code[7:0], 8'b0};
1952 
           next_zero     = !(|alu_result[15:8]);
1953 
           next_negative = alu_result[15];
1954 
           next_overflow = 1'b0;
1955 
         end
1956 
 
1957 
      // Instruction = XNORL RD, #IMM8, Op Code =  1 0 1 1 0 RD IMM8
1958 
      // XNOR - Logical Exclusive NOR
1959 
      // ~(RD.L ^ IMM8) => RD.L
1960 
      {CONT, 16'b10110???????????} :
1961 
         begin
1962 
           ena_rd_low_byte = 1'b1;
1963 
 
1964 
           alu_result    = ~(rd_data ^ {8'b0, op_code[7:0]});
1965 
           next_zero     = !(|alu_result[7:0]);
1966 
           next_negative = alu_result[7];
1967 
           next_overflow = 1'b0;
1968 
         end
1969 
 
1970 
      // Instruction = XNORH RD, #IMM8, Op Code =  1 0 1 1 1 RD IMM8
1971 
      // XNOR - Logical Exclusive NOR
1972 
      // ~(RD.H ^ IMM8) => RD.H
1973 
      {CONT, 16'b10111???????????} :
1974 
         begin
1975 
           ena_rd_high_byte = 1'b1;
1976 
 
1977 
           alu_result    = ~(rd_data ^ {op_code[7:0], 8'b0});
1978 
           next_zero     = !(|alu_result[15:8]);
1979 
           next_negative = alu_result[15];
1980 
           next_overflow = 1'b0;
1981 
         end
1982 
 
1983 
      // -----------------------------------------------------------------------
1984 
      // Instruction Group -- Arithmetic Immediate Instructions
1985 
      // -----------------------------------------------------------------------
1986 
 
1987 
      // Instruction = SUBL RD, #IMM8, Op Code =  1 1 0 0 0 RD IMM8
1988 
      // SUB - Subtract without Carry
1989 
      // RD - $00:IMM8 => RD
1990 
      // Cycles - P
1991 
      {CONT, 16'b11000???????????} :
1992 
         begin
1993 
           ena_rd_low_byte  = 1'b1;
1994 
           ena_rd_high_byte = 1'b1;
1995 
 
1996 
           alu_result    = rd_data - {8'b0, op_code[7:0]};
1997 
           next_zero     = !(|alu_result);
1998 
           next_negative = alu_result[15];
1999 
           next_carry    = (!rd_data[7] && op_code[7]) || (!rd_data[7] && alu_result[7]) || (op_code[7] && alu_result[7]);
2000 
           next_overflow = (rd_data[7] && !op_code[7] && !alu_result[7]) || (!rd_data[7] && op_code[7] && alu_result[7]);
2001 
         end
2002 
 
2003 
      // Instruction = SUBH RD, #IMM8, Op Code =  1 1 0 0 1 RD IMM8
2004 
      // SUB - Subtract without Carry
2005 
      // RD - IMM8:$00 => RD
2006 
      // Cycles - P
2007 
      {CONT, 16'b11001???????????} :
2008 
         begin
2009 
           ena_rd_low_byte  = 1'b1;
2010 
           ena_rd_high_byte = 1'b1;
2011 
 
2012 
           {next_carry, alu_result} = rd_data - {op_code[7:0], 8'b0};
2013 
           next_zero     = !(|alu_result);
2014 
           next_negative = alu_result[15];
2015 
           next_overflow = (rd_data[15] && !op_code[7] && !alu_result[15]) || (!rd_data[15] && op_code[7] && alu_result[15]);
2016 
         end
2017 
 
2018 
      // Instruction = CMPL RS, #IMM8, Op Code =  1 1 0 1 0 RS IMM8
2019 
      // RS.L - IMM8 => NONE, only condition code flags get updated
2020 
      // RS field == RD field
2021 
      // Cycles - P
2022 
      {CONT, 16'b11010???????????} :
2023 
         begin
2024 
 
2025 
           alu_result    = {8'b0, rd_data[7:0] - op_code[7:0]};
2026 
           next_zero     = !(|alu_result[7:0]);
2027 
           next_negative = alu_result[7];
2028 
           next_carry    = (!rd_data[7] && op_code[7]) || (!rd_data[7] && alu_result[7]) || (op_code[7] && alu_result[7]);
2029 
           next_overflow = (rd_data[7] && !op_code[7] && !alu_result[7]) || (!rd_data[7] && op_code[7] && alu_result[7]);
2030 
         end
2031 
 
2032 
      // Instruction = CPCH RS, #IMM8, Op Code =  1 1 0 1 1 RS IMM8
2033 
      // RS.H - IMM8 - C => NONE, only condition code flags get updated
2034 
      // RS field == RD field
2035 
      // Cycles - P
2036 
      {CONT, 16'b11011???????????} :
2037 
         begin
2038 
 
2039 
           alu_result    = {rd_data[15:8], 8'b0} - {op_code[7:0], 8'b0} - {7'b0, carry_flag, 8'b0};
2040 
           next_zero     = !(|alu_result[15:8]) && zero_flag;
2041 
           next_negative = alu_result[15];
2042 
           next_carry    = (!rd_data[15] && op_code[7]) || (!rd_data[15] && alu_result[15]) || (op_code[7] && alu_result[15]);
2043 
           next_overflow = (rd_data[15] && !op_code[7] && !alu_result[15]) || (!rd_data[15] && op_code[7] && alu_result[15]);
2044 
         end
2045 
 
2046 
      // Instruction = ADDL RD, #IMM8, Op Code =  1 1 1 0 0 RD IMM8
2047 
      // ADD - ADD without carry
2048 
      // RD + $00:IMM8 => RD
2049 
      // Cycles - P
2050 
      {CONT, 16'b11100???????????} :
2051 
         begin
2052 
           ena_rd_low_byte  = 1'b1;
2053 
           ena_rd_high_byte = 1'b1;
2054 
 
2055 
           alu_result    = rd_data + {8'b0, op_code[7:0]};
2056 
           next_zero     = !(|alu_result);
2057 
           next_negative = alu_result[15];
2058 
           next_carry    = (rd_data[7] && op_code[7]) || (rd_data[7] && !alu_result[7]) || (op_code[7] && !alu_result[7]);
2059 
           next_overflow = (!rd_data[7] && !op_code[7] && alu_result[7]) || (rd_data[7] && op_code[7] && !alu_result[7]);
2060 
         end
2061 
 
2062 
      // Instruction = ADDH RD, #IMM8, Op Code =  1 1 1 0 1 RD IMM8
2063 
      // ADD - ADD without carry
2064 
      // RD + IMM8:$00 => RD
2065 
      // Cycles - P
2066 
      {CONT, 16'b11101???????????} :
2067 
         begin
2068 
           ena_rd_low_byte  = 1'b1;
2069 
           ena_rd_high_byte = 1'b1;
2070 
 
2071 
           {next_carry, alu_result} = rd_data + {op_code[7:0], 8'b0};
2072 
           next_zero     = !(|alu_result);
2073 
           next_negative = alu_result[15];
2074 
           next_overflow = (rd_data[15] && op_code[7] && !alu_result[15]) || (!rd_data[15] && !op_code[7] && alu_result[15]);
2075 
         end
2076 
 
2077 
      // Instruction = LDL RD, #IMM8, Op Code =  1 1 1 1 0 RD IMM8
2078 
      // IMM8 => RD.L; $00 => RD.H, High Byte is cleared
2079 
      // Cycles - P
2080 
      {CONT, 16'b11110???????????} :
2081 
         begin
2082 
           ena_rd_low_byte  = 1'b1;
2083 
           ena_rd_high_byte = 1'b1;
2084 
 
2085 
           alu_result    = {8'b0, op_code[7:0]};
2086 
         end
2087 
 
2088 
      // Instruction = LDH RD, #IMM8, Op Code =  1 1 1 1 1 RD IMM8
2089 
      // IMM8 => RD.H, Low Byte is unchanged
2090 
      // Cycles - P
2091 
      {CONT, 16'b11111???????????} :
2092 
         begin
2093 
           ena_rd_high_byte = 1'b1;
2094 
 
2095 
           alu_result    = {op_code[7:0], 8'b0};
2096 
         end
2097 
      default :
2098 
        begin
2099 89 rehayes 
          // synopsys translate_off
2100 2 rehayes 
          $display("\nOP Code Error\n");
2101 89 rehayes 
          // synopsys translate_on
2102 12 rehayes 
          next_cpu_state   = DEBUG;
2103 40 rehayes 
          pc_incr_mux      = 16'h0000;
2104 
          next_pc          = pc_sum;
2105 12 rehayes 
          load_next_inst   = 1'b0;
2106 17 rehayes 
          op_code_error    = 1'b1;
2107 2 rehayes 
        end
2108 
    endcase
2109 89 rehayes 
 
2110 2 rehayes 
    end  // always
2111 
 
2112 
  xgate_barrel_shift barrel_shift(
2113 
    // outputs
2114 
    .shift_out( shift_out ),
2115 
    .shift_rollover( shift_rollover ),
2116 
    // inputs
2117 
    .shift_left( shift_left ),
2118 
    .shift_ammount( shift_ammount ),
2119 
    .shift_in( shift_in ),
2120 
    .shift_filler( shift_filler )
2121 
  );
2122 
 
2123 
  // Three to Eight line decoder
2124 
  always @*
2125 26 rehayes 
    case (semaph_risc)  // synopsys parallel_case
2126 2 rehayes 
      4'h0 : semap_risc_bit = 8'b0000_0001;
2127 
      4'h1 : semap_risc_bit = 8'b0000_0010;
2128 
      4'h2 : semap_risc_bit = 8'b0000_0100;
2129 
      4'h3 : semap_risc_bit = 8'b0000_1000;
2130 
      4'h4 : semap_risc_bit = 8'b0001_0000;
2131 
      4'h5 : semap_risc_bit = 8'b0010_0000;
2132 
      4'h6 : semap_risc_bit = 8'b0100_0000;
2133 
      4'h7 : semap_risc_bit = 8'b1000_0000;
2134 
    endcase
2135 12 rehayes 
 
2136 2 rehayes 
  assign semaph_stat = |risc_semap;
2137 
 
2138 59 rehayes 
  // Semaphore Bits
2139 
  genvar sem_gen_count;
2140 
  generate
2141 
    for (sem_gen_count = 0; sem_gen_count < 8; sem_gen_count = sem_gen_count + 1)
2142 
      begin:semaphore_
2143 89 rehayes 
        semaphore_bit sbit(
2144 
          // outputs
2145 
          .host_status( host_semap[sem_gen_count] ),
2146 
          .risc_status( risc_semap[sem_gen_count] ),
2147 
          // inputs
2148 
          .risc_clk( risc_clk ),
2149 
          .async_rst_b( async_rst_b ),
2150 
          .risc_bit_sel( semap_risc_bit[sem_gen_count] ),
2151 
          .csem( clear_semaph ),
2152 
          .ssem( set_semaph ),
2153 
          .host_wrt( write_xgsem ),
2154 
          .host_bit_mask( perif_data[sem_gen_count+8] ),
2155 
          .host_bit( perif_data[sem_gen_count] )
2156 
        );
2157 59 rehayes 
      end
2158 
  endgenerate
2159 2 rehayes 
 
2160 
  endmodule  // xgate_inst_decode
2161 
 
2162 
// -----------------------------------------------------------------------------
2163 
// -----------------------------------------------------------------------------
2164 
// -----------------------------------------------------------------------------
2165 
 
2166 
module xgate_barrel_shift (
2167 
  output reg [15:0] shift_out,
2168 
  output reg        shift_rollover,
2169 
 
2170 
  input             shift_left,
2171 
  input      [ 4:0] shift_ammount,
2172 
  input      [15:0] shift_in,
2173 
  input      [15:0] shift_filler
2174 
  );
2175 
 
2176 
  always @*
2177 26 rehayes 
    casez ({shift_left, shift_ammount})  // synopsys parallel_case
2178 2 rehayes 
     // Start Right Shifts
2179 
      6'b0_0_0000 :
2180 
        begin
2181 
          shift_out      = shift_in;
2182 
          shift_rollover = 1'b0;
2183 
        end
2184 
      6'b0_0_0001 :
2185 
        begin
2186 
          shift_out      = {shift_filler[ 0], shift_in[15: 1]};
2187 
          shift_rollover =  shift_in[ 0];
2188 
        end
2189 
      6'b0_0_0010 :
2190 
        begin
2191 
          shift_out      = {shift_filler[ 1:0], shift_in[15: 2]};
2192 
          shift_rollover =  shift_in[ 1];
2193 
        end
2194 
      6'b0_0_0011 :
2195 
        begin
2196 
          shift_out      = {shift_filler[ 2:0], shift_in[15: 3]};
2197 
          shift_rollover =  shift_in[ 2];
2198 
        end
2199 
      6'b0_0_0100 :
2200 
        begin
2201 
          shift_out      = {shift_filler[ 3:0], shift_in[15: 4]};
2202 
          shift_rollover =  shift_in[ 3];
2203 
        end
2204 
      6'b0_0_0101 :
2205 
        begin
2206 
          shift_out      = {shift_filler[ 4:0], shift_in[15: 5]};
2207 
          shift_rollover =  shift_in[ 4];
2208 
        end
2209 
      6'b0_0_0110 :
2210 
        begin
2211 
          shift_out      = {shift_filler[ 5:0], shift_in[15: 6]};
2212 
          shift_rollover =  shift_in[ 5];
2213 
        end
2214 
      6'b0_0_0111 :
2215 
        begin
2216 
          shift_out      = {shift_filler[ 6:0], shift_in[15: 7]};
2217 
          shift_rollover =  shift_in[ 6];
2218 
        end
2219 
      6'b0_0_1000 :
2220 
        begin
2221 
          shift_out      = {shift_filler[ 7:0], shift_in[15: 8]};
2222 
          shift_rollover =  shift_in[ 7];
2223 
        end
2224 
      6'b0_0_1001 :
2225 
        begin
2226 
          shift_out      = {shift_filler[ 8:0], shift_in[15: 9]};
2227 
          shift_rollover =  shift_in[ 8];
2228 
        end
2229 
      6'b0_0_1010 :
2230 
        begin
2231 
          shift_out      = {shift_filler[ 9:0], shift_in[15:10]};
2232 
          shift_rollover =  shift_in[ 9];
2233 
        end
2234 
      6'b0_0_1011 :
2235 
        begin
2236 
          shift_out      = {shift_filler[10:0], shift_in[15:11]};
2237 
          shift_rollover =  shift_in[10];
2238 
        end
2239 
      6'b0_0_1100 :
2240 
        begin
2241 
          shift_out      = {shift_filler[11:0], shift_in[15:12]};
2242 
          shift_rollover =  shift_in[11];
2243 
        end
2244 
      6'b0_0_1101 :
2245 
        begin
2246 
          shift_out      = {shift_filler[12:0], shift_in[15:13]};
2247 
          shift_rollover =  shift_in[12];
2248 
        end
2249 
      6'b0_0_1110 :
2250 
        begin
2251 
          shift_out      = {shift_filler[13:0], shift_in[15:14]};
2252 
          shift_rollover =  shift_in[13];
2253 
        end
2254 
      6'b0_0_1111 :
2255 
        begin
2256 
          shift_out      = {shift_filler[14:0], shift_in[15]};
2257 
          shift_rollover =  shift_in[14];
2258 
        end
2259 
      6'b0_1_???? :
2260 
        begin
2261 
          shift_out      = shift_filler[15:0];
2262 
          shift_rollover = shift_in[15];
2263 
        end
2264 12 rehayes 
 
2265 2 rehayes 
     // Start Left Shifts
2266 12 rehayes 
 
2267 2 rehayes 
      6'b1_0_0000 :
2268 
        begin
2269 
          shift_out      =  shift_in;
2270 
          shift_rollover  = 1'b0;
2271 
        end
2272 
      6'b1_0_0001 :
2273 
        begin
2274 
          shift_out      = {shift_in[14:0], shift_filler[15]};
2275 
          shift_rollover =  shift_in[15];
2276 
        end
2277 
      6'b1_0_0010 :
2278 
        begin
2279 
          shift_out      = {shift_in[13:0], shift_filler[15:14]};
2280 
          shift_rollover =  shift_in[14];
2281 
        end
2282 
      6'b1_0_0011 :
2283 
        begin
2284 
          shift_out      = {shift_in[12:0], shift_filler[15:13]};
2285 
          shift_rollover =  shift_in[13];
2286 
        end
2287 
      6'b1_0_0100 :
2288 
        begin
2289 
          shift_out      = {shift_in[11:0], shift_filler[15:12]};
2290 
          shift_rollover =  shift_in[12];
2291 
        end
2292 
      6'b1_0_0101 :
2293 
        begin
2294 
          shift_out      = {shift_in[10:0], shift_filler[15:11]};
2295 
          shift_rollover =  shift_in[11];
2296 
        end
2297 
      6'b1_0_0110 :
2298 
        begin
2299 
          shift_out      = {shift_in[ 9:0], shift_filler[15:10]};
2300 
          shift_rollover =  shift_in[10];
2301 
        end
2302 
      6'b1_0_0111 :
2303 
        begin
2304 
          shift_out      = {shift_in[ 8:0], shift_filler[15: 9]};
2305 
          shift_rollover =  shift_in[ 9];
2306 
        end
2307 
      6'b1_0_1000 :
2308 
        begin
2309 
          shift_out      = {shift_in[ 7:0], shift_filler[15: 8]};
2310 
          shift_rollover =  shift_in[ 8];
2311 
        end
2312 
      6'b1_0_1001 :
2313 
        begin
2314 
          shift_out      = {shift_in[ 6:0], shift_filler[15: 7]};
2315 
          shift_rollover =  shift_in[ 7];
2316 
        end
2317 
      6'b1_0_1010 :
2318 
        begin
2319 
          shift_out      = {shift_in[ 5:0], shift_filler[15: 6]};
2320 
          shift_rollover =  shift_in[ 6];
2321 
        end
2322 
      6'b1_0_1011 :
2323 
        begin
2324 
          shift_out      = {shift_in[ 4:0], shift_filler[15: 5]};
2325 
          shift_rollover =  shift_in[ 5];
2326 
        end
2327 
      6'b1_0_1100 :
2328 
        begin
2329 
          shift_out      = {shift_in[ 3:0], shift_filler[15 :4]};
2330 
          shift_rollover =  shift_in[ 4];
2331 
        end
2332 
      6'b1_0_1101 :
2333 
        begin
2334 
          shift_out      = {shift_in[ 2:0], shift_filler[15: 3]};
2335 
          shift_rollover =  shift_in[ 3];
2336 
        end
2337 
      6'b1_0_1110 :
2338 
        begin
2339 
          shift_out      = {shift_in[ 1:0], shift_filler[15: 2]};
2340 
          shift_rollover =  shift_in[ 2];
2341 
        end
2342 
      6'b1_0_1111 :
2343 
        begin
2344 
          shift_out      = {shift_in[ 0], shift_filler[15: 1]};
2345 
          shift_rollover =  shift_in[ 1];
2346 
        end
2347 
      6'b1_1_???? :
2348 
        begin
2349 
          shift_out      = shift_filler[15: 0];
2350 
          shift_rollover = shift_in[ 0];
2351 
        end
2352 75 rehayes 
      default :
2353 
        begin
2354 
          shift_out      =  shift_in;
2355 
          shift_rollover  = 1'b0;
2356 
        end
2357 2 rehayes 
    endcase
2358 12 rehayes 
 
2359 
 
2360 2 rehayes 
endmodule  // xgate_barrel_shift
2361 
 
2362 
// -----------------------------------------------------------------------------
2363 
// -----------------------------------------------------------------------------
2364 
// -----------------------------------------------------------------------------
2365 
 
2366 
module semaphore_bit #(parameter NO_LOCK   = 2'b00,
2367 
                       parameter RISC_LOCK = 2'b10,
2368 12 rehayes 
                       parameter HOST_LOCK = 2'b11)
2369 2 rehayes 
  (
2370 
  output      host_status,   // Return status for Host processor
2371 
  output      risc_status,   // Return Status for RISC processor
2372 
 
2373 
  input       risc_clk,      // Semaphore register clock
2374 
  input       async_rst_b,   // Async reset signal
2375 
  input       risc_bit_sel,  // Bit selected by RISC
2376 
  input       csem,          // RISC Clear Semaphore Bit
2377 
  input       ssem,          // RISC Set Semaphore Bit
2378 
  input       host_wrt,      // Host write to the Semaphore Register
2379 
  input       host_bit_mask, // Host mask bit written to the Semaphore bit
2380 
  input       host_bit       // Host bit written to the Semaphore bit
2381 
  );
2382 
 
2383 
  reg [1:0] next_semap_state;
2384 
  reg [1:0] semap_state;
2385 12 rehayes 
 
2386 2 rehayes 
  assign host_status = semap_state == HOST_LOCK;
2387 
  assign risc_status = ssem && risc_bit_sel && ((semap_state == RISC_LOCK) || (next_semap_state == RISC_LOCK));
2388 
 
2389 
  always @(posedge risc_clk or negedge async_rst_b)
2390 
    if (!async_rst_b)
2391 
      semap_state <= NO_LOCK;
2392 
    else
2393 
      semap_state <= next_semap_state;
2394 
 
2395 
  always @*
2396 
    begin
2397 
      case(semap_state)
2398 12 rehayes 
        NO_LOCK:
2399 
          begin
2400 
            if (host_wrt && host_bit_mask && host_bit)
2401 
              next_semap_state = HOST_LOCK;
2402 
            else if (ssem && risc_bit_sel)
2403 
              next_semap_state = RISC_LOCK;
2404 
            else
2405 
              next_semap_state = NO_LOCK;
2406 
          end
2407 
        RISC_LOCK:
2408 
          begin
2409 
            if (csem && risc_bit_sel)
2410 
              next_semap_state = NO_LOCK;
2411 26 rehayes 
            else
2412 
              next_semap_state = RISC_LOCK;
2413 
           end
2414 12 rehayes 
        HOST_LOCK:
2415 
          begin
2416 
            if (host_wrt && host_bit_mask && !host_bit)
2417 
              next_semap_state = NO_LOCK;
2418 26 rehayes 
            else
2419 
              next_semap_state = HOST_LOCK;
2420 
           end
2421 12 rehayes 
        default:
2422 
          next_semap_state = NO_LOCK;
2423 2 rehayes 
      endcase
2424 
    end
2425 12 rehayes 
 
2426 2 rehayes 
endmodule  // semaphore_bit
2427 
 
2428 
 

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