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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_top.v] - Blame information for rev 13

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1 2 rehayes
////////////////////////////////////////////////////////////////////////////////
2
//
3
//  XGATE Coprocessor - XGATE Top Level Module
4
//
5
//  Author: Robert Hayes
6
//          rehayes@opencores.org
7
//
8
//  Downloaded from: http://www.opencores.org/projects/xgate.....
9
//
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////////////////////////////////////////////////////////////////////////////////
11
// Copyright (c) 2009, Robert Hayes
12
//
13
// This source file is free software: you can redistribute it and/or modify
14
// it under the terms of the GNU Lesser General Public License as published
15
// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// Supplemental terms.
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//     * Redistributions of source code must retain the above copyright
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//       notice, this list of conditions and the following disclaimer.
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//     * Neither the name of the <organization> nor the
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//       names of its contributors may be used to endorse or promote products
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//       derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
31
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
40
 
41
module xgate_top #(parameter ARST_LVL = 1'b0,      // asynchronous reset level
42
                   parameter SINGLE_CYCLE = 1'b0,  // 
43
                   parameter MAX_CHANNEL = 127,    // Max XGATE Interrupt Channel Number
44
                   parameter DWIDTH = 16)          // Data bus width
45
  (
46 5 rehayes
  // Wishbone Slave Signals
47
  output    [DWIDTH-1:0] wbs_dat_o,     // databus output
48
  output                 wbs_ack_o,     // bus cycle acknowledge output
49
  input                  wbs_clk_i,     // master clock input
50
  input                  wbs_rst_i,     // synchronous active high reset
51
  input                  arst_i,        // asynchronous reset
52
  input            [4:0] wbs_adr_i,     // lower address bits
53
  input     [DWIDTH-1:0] wbs_dat_i,     // databus input
54
  input                  wbs_we_i,      // write enable input
55
  input                  wbs_stb_i,     // stobe/core select signal
56
  input                  wbs_cyc_i,     // valid bus cycle input
57
  input            [1:0] wbs_sel_i,     // Select byte in word bus transaction
58
  // Wishbone Master Signals
59
  output    [DWIDTH-1:0] wbm_dat_o,     // databus output
60
  output                 wbm_we_o,      // write enable output
61
  output                 wbm_stb_o,     // stobe/core select signal
62
  output                 wbm_cyc_o,     // valid bus cycle output
63
  output          [ 1:0] wbm_sel_o,     // Select byte in word bus transaction
64
  output          [15:0] wbm_adr_o,     // Address bits
65
  input     [DWIDTH-1:0] wbm_dat_i,     // databus input
66
  input                  wbm_ack_i,     // bus cycle acknowledge input
67 2 rehayes
  // XGATE IO Signals
68 5 rehayes
  output          [ 7:0] xgswt,         // XGATE Software Trigger Register
69 2 rehayes
  output                 write_mem_strb_l, // Strobe for writing low data byte
70
  output                 write_mem_strb_h, // Strobe for writing high data bye
71 12 rehayes
  output                 xg_sw_irq,        // Xgate Software interrupt
72 2 rehayes
  output [MAX_CHANNEL:0] xgif,             // XGATE Interrupt Flag
73
  input  [MAX_CHANNEL:0] chan_req_i,       // XGATE Interrupt request
74
  input                  risc_clk,         // Clock for RISC core
75
  input                  scantestmode      // Chip in in scan test mode
76
  );
77
 
78
  wire        zero_flag;
79
  wire        negative_flag;
80
  wire        carry_flag;
81
  wire        overflow_flag;
82
  wire [15:0] xgr1;          // XGATE Register #1
83
  wire [15:0] xgr2;          // XGATE Register #2
84
  wire [15:0] xgr3;          // XGATE Register #3
85
  wire [15:0] xgr4;          // XGATE Register #4
86
  wire [15:0] xgr5;          // XGATE Register #5
87
  wire [15:0] xgr6;          // XGATE Register #6
88
  wire [15:0] xgr7;          // XGATE Register #7
89
 
90
  wire [15:0] xgisp74;       // XGATE Interrupt level 7-4 stack pointer
91
  wire [15:0] xgisp30;       // XGATE Interrupt level 3-0 stack pointer
92
 
93
  wire        write_xgmctl;  // Write Strobe for XGMCTL register
94
  wire        write_xgisp74; // Write Strobe for XGISP74 register
95
  wire        write_xgisp31; // Write Strobe for XGISP31 register
96
  wire        write_xgvbr;   // Write Strobe for XGVBR_LO register
97
  wire        write_xgif_7;  // Write Strobe for Interrupt Flag Register 7
98
  wire        write_xgif_6;  // Write Strobe for Interrupt Flag Register 6
99
  wire        write_xgif_5;  // Write Strobe for Interrupt Flag Register 5
100
  wire        write_xgif_4;  // Write Strobe for Interrupt Flag Register 4
101
  wire        write_xgif_3;  // Write Strobe for Interrupt Flag Register 3
102
  wire        write_xgif_2;  // Write Strobe for Interrupt Flag Register 2
103
  wire        write_xgif_1;  // Write Strobe for Interrupt Flag Register 1
104
  wire        write_xgif_0;  // Write Strobe for Interrupt Flag Register 0
105
  wire        write_xgswt;   // Write Strobe for XGSWT register
106
  wire        write_xgsem;   // Write Strobe for XGSEM register
107
  wire        write_xgccr;   // Write Strobe for XGATE Condition Code Register
108
  wire        write_xgpc;    // Write Strobe for XGATE Program Counter
109
  wire        write_xgr7;    // Write Strobe for XGATE Data Register R7
110
  wire        write_xgr6;    // Write Strobe for XGATE Data Register R6
111
  wire        write_xgr5;    // Write Strobe for XGATE Data Register R5
112
  wire        write_xgr4;    // Write Strobe for XGATE Data Register R4
113
  wire        write_xgr3;    // Write Strobe for XGATE Data Register R3
114
  wire        write_xgr2;    // Write Strobe for XGATE Data Register R2
115
  wire        write_xgr1;    // Write Strobe for XGATE Data Register R1
116
 
117
  wire        clear_xgif_7;    // Strobe for decode to clear interrupt flag bank 7
118
  wire        clear_xgif_6;    // Strobe for decode to clear interrupt flag bank 6
119
  wire        clear_xgif_5;    // Strobe for decode to clear interrupt flag bank 5
120
  wire        clear_xgif_4;    // Strobe for decode to clear interrupt flag bank 4
121
  wire        clear_xgif_3;    // Strobe for decode to clear interrupt flag bank 3
122
  wire        clear_xgif_2;    // Strobe for decode to clear interrupt flag bank 2
123
  wire        clear_xgif_1;    // Strobe for decode to clear interrupt flag bank 1
124
  wire        clear_xgif_0;    // Strobe for decode to clear interrupt flag bank 0
125
  wire [15:0] clear_xgif_data; // Data for decode to clear interrupt flag
126
 
127
  wire        xge;           // XGATE Module Enable
128
  wire        xgfrz;         // Stop XGATE in Freeze Mode
129
  wire        xgdbg;         // XGATE Debug Mode
130
  wire        xgss;          // XGATE Single Step
131
  wire        xgsweif_c;     // Clear XGATE Software Error Interrupt FLag
132
  wire        xgie;          // XGATE Interrupt Enable
133
  wire [ 6:0] int_req;       // Encoded interrupt request
134
  wire [ 6:0] xgchid;        // Channel actively being processed
135
  wire [15:1] xgvbr;         // XGATE vector Base Address Register
136 12 rehayes
  wire        brk_irq_ena;   // Enable BRK instruction to generate interrupt
137 2 rehayes
 
138 5 rehayes
  wire [15:0] xgate_address;   //
139
  wire [15:0] write_mem_data;  //
140
  wire [15:0] read_mem_data;   //
141
  wire        mem_req_ack;     //
142 12 rehayes
 
143
  wire        debug_active;    // RISC state machine in Debug mode 
144 5 rehayes
 
145 2 rehayes
  wire [ 7:0] host_semap;    // Semaphore status for host
146
//  wire [15:0] write_mem_data;
147
//  wire [15:0] read_mem_data;
148
//  wire [15:0] perif_data;
149
 
150
 
151
  // ---------------------------------------------------------------------------
152
  // Wishbone Slave Bus interface
153
  xgate_wbs_bus #(.ARST_LVL(ARST_LVL),
154 5 rehayes
                  .SINGLE_CYCLE(SINGLE_CYCLE))
155 2 rehayes
    wishbone_s(
156
    .wbs_dat_o( wbs_dat_o ),
157
    .wbs_ack_o( wbs_ack_o ),
158
    .wbs_clk_i( wbs_clk_i ),
159
    .wbs_rst_i( wbs_rst_i ),
160
    .arst_i( arst_i ),
161
    .wbs_adr_i( wbs_adr_i ),
162
    .wbs_dat_i( wbs_dat_i ),
163
    .wbs_we_i( wbs_we_i ),
164
    .wbs_stb_i( wbs_stb_i ),
165
    .wbs_cyc_i( wbs_cyc_i ),
166
    .wbs_sel_i( wbs_sel_i ),
167
 
168
    // outputs
169
    .sync_reset( sync_reset ),
170
    .write_xgmctl( write_xgmctl ),
171
    .write_xgisp74( write_xgisp74 ),
172
    .write_xgisp30( write_xgisp30 ),
173
    .write_xgvbr( write_xgvbr ),
174
    .write_xgif_7( write_xgif_7 ),
175
    .write_xgif_6( write_xgif_6 ),
176
    .write_xgif_5( write_xgif_5 ),
177
    .write_xgif_4( write_xgif_4 ),
178
    .write_xgif_3( write_xgif_3 ),
179
    .write_xgif_2( write_xgif_2 ),
180
    .write_xgif_1( write_xgif_1 ),
181
    .write_xgif_0( write_xgif_0 ),
182
    .write_xgswt( write_xgswt ),
183
    .write_xgsem( write_xgsem ),
184
    .write_xgccr( write_xgccr ),
185
    .write_xgpc( write_xgpc ),
186
    .write_xgr7( write_xgr7 ),
187
    .write_xgr6( write_xgr6 ),
188
    .write_xgr5( write_xgr5 ),
189
    .write_xgr4( write_xgr4 ),
190
    .write_xgr3( write_xgr3 ),
191
    .write_xgr2( write_xgr2 ),
192
    .write_xgr1( write_xgr1 ),
193
    // inputs    
194
    .async_rst_b  ( async_rst_b ),
195
    .read_regs    (               // in  -- read register bits
196
                   { xgr7,             // XGR7
197
                     xgr6,             // XGR6
198
                     xgr5,             // XGR5
199
                     xgr4,             // XGR4
200
                     xgr3,             // XGR3
201
                     xgr2,             // XGR2
202
                     xgr1,             // XGR1
203
                     16'b0,            // Reserved (XGR0)
204
                     xgate_address,    // XGPC
205
                     {12'h000,  negative_flag, zero_flag, overflow_flag, carry_flag},  // XGCCR
206
                     16'b0,  // Reserved
207
                     {8'h00, host_semap},  // XGSEM
208
                     {8'h00, xgswt},  // XGSWT
209
                     xgif[ 15:  0],  // XGIF_0
210
                     xgif[ 31: 16],  // XGIF_1
211
                     xgif[ 47: 32],  // XGIF_2
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                     xgif[ 63: 48],  // XGIF_3
213
                     xgif[ 79: 64],  // XGIF_4
214
                     xgif[ 95: 80],  // XGIF_5
215
                     xgif[111: 96],  // XGIF_6
216
                     xgif[127:112],  // XGIF_7
217
                     {xgvbr[15:1], 1'b0},  // XGVBR
218
                     xgisp30,  // Reserved
219
                     xgisp74,  // Reserved
220
                     {8'b0, 1'b0, xgchid},  // XGCHID
221 12 rehayes
                     {8'b0, xge, xgfrz, debug_active, 1'b0, 2'b0, xg_sw_irq, xgie}  // XGMCTL
222 2 rehayes
                   }
223
                  )
224
  );
225
 
226
  // ---------------------------------------------------------------------------
227
  xgate_regs #(.ARST_LVL(ARST_LVL),
228
               .MAX_CHANNEL(MAX_CHANNEL))
229
    regs(
230
    // outputs
231
    .xge( xge ),
232
    .xgfrz( xgfrz ),
233
    .xgdbg( xgdbg ),
234
    .xgss( xgss ),
235
    .xgsweif_c( xgsweif_c ),
236
    .xgie( xgie ),
237 12 rehayes
    .brk_irq_ena( brk_irq_ena ),
238 2 rehayes
    .xgvbr( xgvbr ),
239
    .xgswt( xgswt ),
240
    .xgisp74( xgisp74 ),
241
    .xgisp30( xgisp30 ),
242
    .clear_xgif_7( clear_xgif_7 ),
243
    .clear_xgif_6( clear_xgif_6 ),
244
    .clear_xgif_5( clear_xgif_5 ),
245
    .clear_xgif_4( clear_xgif_4 ),
246
    .clear_xgif_3( clear_xgif_3 ),
247
    .clear_xgif_2( clear_xgif_2 ),
248
    .clear_xgif_1( clear_xgif_1 ),
249
    .clear_xgif_0( clear_xgif_0 ),
250
    .clear_xgif_data( clear_xgif_data ),
251
 
252
    // inputs
253
    .async_rst_b( async_rst_b ),
254
    .sync_reset( sync_reset ),
255
    .bus_clk( wbs_clk_i ),
256
    .write_bus( wbs_dat_i ),
257
    .write_xgmctl( write_xgmctl ),
258
    .write_xgisp74( write_xgisp74 ),
259
    .write_xgisp30( write_xgisp30 ),
260
    .write_xgvbr( write_xgvbr ),
261
    .write_xgif_7( write_xgif_7 ),
262
    .write_xgif_6( write_xgif_6 ),
263
    .write_xgif_5( write_xgif_5 ),
264
    .write_xgif_4( write_xgif_4 ),
265
    .write_xgif_3( write_xgif_3 ),
266
    .write_xgif_2( write_xgif_2 ),
267
    .write_xgif_1( write_xgif_1 ),
268
    .write_xgif_0( write_xgif_0 ),
269
    .write_xgswt( write_xgswt )
270
 
271
 
272
  );
273
 
274
  // ---------------------------------------------------------------------------
275
  xgate_risc #(.MAX_CHANNEL(MAX_CHANNEL))
276
    risc(
277
    // outputs
278
    .xgate_address( xgate_address ),
279
    .write_mem_strb_l( write_mem_strb_l ),
280
    .write_mem_strb_h( write_mem_strb_h ),
281
    .write_mem_data( write_mem_data ),
282
    .zero_flag( zero_flag ),
283
    .negative_flag( negative_flag ),
284
    .carry_flag( carry_flag ),
285
    .overflow_flag( overflow_flag ),
286
    .xgchid( xgchid ),
287
    .host_semap( host_semap ),
288
    .xgr1( xgr1 ),
289
    .xgr2( xgr2 ),
290
    .xgr3( xgr3 ),
291
    .xgr4( xgr4 ),
292
    .xgr5( xgr5 ),
293
    .xgr6( xgr6 ),
294
    .xgr7( xgr7 ),
295
    .xgif( xgif ),
296 12 rehayes
    .debug_active( debug_active ),
297
    .xg_sw_irq( xg_sw_irq ),
298 2 rehayes
 
299
    // inputs
300
    .risc_clk( risc_clk ),
301
    .perif_data( wbs_dat_i ),
302
    .async_rst_b( async_rst_b ),
303
    .read_mem_data( read_mem_data ),
304 5 rehayes
    .mem_req_ack( mem_req_ack ),
305 2 rehayes
    .xge( xge ),
306
    .xgfrz( xgfrz ),
307
    .xgdbg( xgdbg ),
308
    .xgss( xgss ),
309
    .xgvbr( xgvbr ),
310 5 rehayes
    .int_req( int_req ),
311 12 rehayes
    .xgie( xgie ),
312
    .brk_irq_ena( brk_irq_ena ),
313 2 rehayes
    .write_xgsem( write_xgsem ),
314
    .write_xgccr( write_xgccr ),
315
    .write_xgpc( write_xgpc ),
316
    .write_xgr7( write_xgr7 ),
317
    .write_xgr6( write_xgr6 ),
318
    .write_xgr5( write_xgr5 ),
319
    .write_xgr4( write_xgr4 ),
320
    .write_xgr3( write_xgr3 ),
321
    .write_xgr2( write_xgr2 ),
322
    .write_xgr1( write_xgr1 ),
323
    .clear_xgif_7( clear_xgif_7 ),
324
    .clear_xgif_6( clear_xgif_6 ),
325
    .clear_xgif_5( clear_xgif_5 ),
326
    .clear_xgif_4( clear_xgif_4 ),
327
    .clear_xgif_3( clear_xgif_3 ),
328
    .clear_xgif_2( clear_xgif_2 ),
329
    .clear_xgif_1( clear_xgif_1 ),
330
    .clear_xgif_0( clear_xgif_0 ),
331 12 rehayes
    .xgsweif_c( xgsweif_c ),
332 2 rehayes
    .clear_xgif_data( clear_xgif_data )
333
  );
334
 
335
  xgate_irq_encode #(.MAX_CHANNEL(MAX_CHANNEL))
336
    irq_encode(
337
    // outputs
338
    .int_req( int_req ),
339
    // inputs
340
    .chan_req_i( chan_req_i )
341
  );
342
 
343 5 rehayes
  // ---------------------------------------------------------------------------
344
  // Wishbone Master Bus interface
345
  xgate_wbm_bus #(.ARST_LVL(ARST_LVL))
346
    wishbone_m(
347
  // Wishbone Master Signals
348
    .wbm_dat_o( wbm_dat_o ),
349
    .wbm_we_o( wbm_we_o ),
350
    .wbm_stb_o( wbm_stb_o ),
351
    .wbm_cyc_o( wbm_cyc_o ),
352
    .wbm_sel_o( wbm_sel_o ),
353
    .wbm_adr_o( wbm_adr_o ),
354
    .wbm_dat_i( wbm_dat_i ),
355
    .wbm_ack_i( wbm_ack_i ),
356
    .wbs_clk_i( wbs_clk_i ),
357
    .wbs_rst_i( wbs_rst_i ),
358
    .arst_i( arst_i ),
359
 // XGATE Control Signals
360
    .read_mem_data( read_mem_data ),
361
    .xgate_address( xgate_address ),
362
    .mem_req_ack( mem_req_ack ),
363
    .write_mem_strb_l( write_mem_strb_l ),
364
    .write_mem_strb_h( write_mem_strb_h ),
365
    .write_mem_data( write_mem_data )
366
  );
367 2 rehayes
 
368 5 rehayes
 
369 2 rehayes
endmodule  // xgate_top
370
 

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