URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_top.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log


////////////////////////////////////////////////////////////////////////////////
//
//  XGATE Coprocessor - XGATE Top Level Module
//
//  Author: Robert Hayes
//          rehayes@opencores.org
//
//  Downloaded from: http://www.opencores.org/projects/xgate.....
//
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009, Robert Hayes
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Supplemental terms.
//     * Redistributions of source code must retain the above copyright
//       notice, this list of conditions and the following disclaimer.
//     * Neither the name of the <organization> nor the
//       names of its contributors may be used to endorse or promote products
//       derived from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// You should have received a copy of the GNU General Public License
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
 
module xgate_top #(parameter ARST_LVL = 1'b0,      // asynchronous reset level
                   parameter SINGLE_CYCLE = 1'b0,  // 
                   parameter MAX_CHANNEL = 127,    // Max XGATE Interrupt Channel Number
                   parameter DWIDTH = 16)          // Data bus width
  (
  // Wishbone Signals
  output [DWIDTH-1:0] wbs_dat_o,     // databus output
  output              wbs_ack_o,     // bus cycle acknowledge output
  input               wbs_clk_i,     // master clock input
  input               wbs_rst_i,     // synchronous active high reset
  input               arst_i,        // asynchronous reset
  input         [4:0] wbs_adr_i,     // lower address bits
  input  [DWIDTH-1:0] wbs_dat_i,     // databus input
  input               wbs_we_i,      // write enable input
  input               wbs_stb_i,     // stobe/core select signal
  input               wbs_cyc_i,     // valid bus cycle input
  input         [1:0] wbs_sel_i,     // Select byte in word bus transaction
  // XGATE IO Signals
  output          [ 7:0] xgswt,        // XGATE Software Trigger Register
  output          [15:0] xgate_address,
  output                 write_mem_strb_l, // Strobe for writing low data byte
  output                 write_mem_strb_h, // Strobe for writing high data bye
  output          [15:0] write_mem_data,
  output [MAX_CHANNEL:0] xgif,             // XGATE Interrupt Flag
  input           [15:0] read_mem_data,
  input  [MAX_CHANNEL:0] chan_req_i,       // XGATE Interrupt request
  input                  risc_clk,         // Clock for RISC core
  input                  scantestmode      // Chip in in scan test mode
  );
 
 
  wire        zero_flag;
  wire        negative_flag;
  wire        carry_flag;
  wire        overflow_flag;
  wire [15:0] xgr1;          // XGATE Register #1
  wire [15:0] xgr2;          // XGATE Register #2
  wire [15:0] xgr3;          // XGATE Register #3
  wire [15:0] xgr4;          // XGATE Register #4
  wire [15:0] xgr5;          // XGATE Register #5
  wire [15:0] xgr6;          // XGATE Register #6
  wire [15:0] xgr7;          // XGATE Register #7
 
  wire [15:0] xgisp74;       // XGATE Interrupt level 7-4 stack pointer
  wire [15:0] xgisp30;       // XGATE Interrupt level 3-0 stack pointer
 
  wire        write_xgmctl;  // Write Strobe for XGMCTL register
  wire        write_xgisp74; // Write Strobe for XGISP74 register
  wire        write_xgisp31; // Write Strobe for XGISP31 register
  wire        write_xgvbr;   // Write Strobe for XGVBR_LO register
  wire        write_xgif_7;  // Write Strobe for Interrupt Flag Register 7
  wire        write_xgif_6;  // Write Strobe for Interrupt Flag Register 6
  wire        write_xgif_5;  // Write Strobe for Interrupt Flag Register 5
  wire        write_xgif_4;  // Write Strobe for Interrupt Flag Register 4
  wire        write_xgif_3;  // Write Strobe for Interrupt Flag Register 3
  wire        write_xgif_2;  // Write Strobe for Interrupt Flag Register 2
  wire        write_xgif_1;  // Write Strobe for Interrupt Flag Register 1
  wire        write_xgif_0;  // Write Strobe for Interrupt Flag Register 0
  wire        write_xgswt;   // Write Strobe for XGSWT register
  wire        write_xgsem;   // Write Strobe for XGSEM register
  wire        write_xgccr;   // Write Strobe for XGATE Condition Code Register
  wire        write_xgpc;    // Write Strobe for XGATE Program Counter
  wire        write_xgr7;    // Write Strobe for XGATE Data Register R7
  wire        write_xgr6;    // Write Strobe for XGATE Data Register R6
  wire        write_xgr5;    // Write Strobe for XGATE Data Register R5
  wire        write_xgr4;    // Write Strobe for XGATE Data Register R4
  wire        write_xgr3;    // Write Strobe for XGATE Data Register R3
  wire        write_xgr2;    // Write Strobe for XGATE Data Register R2
  wire        write_xgr1;    // Write Strobe for XGATE Data Register R1
 
  wire        clear_xgif_7;    // Strobe for decode to clear interrupt flag bank 7
  wire        clear_xgif_6;    // Strobe for decode to clear interrupt flag bank 6
  wire        clear_xgif_5;    // Strobe for decode to clear interrupt flag bank 5
  wire        clear_xgif_4;    // Strobe for decode to clear interrupt flag bank 4
  wire        clear_xgif_3;    // Strobe for decode to clear interrupt flag bank 3
  wire        clear_xgif_2;    // Strobe for decode to clear interrupt flag bank 2
  wire        clear_xgif_1;    // Strobe for decode to clear interrupt flag bank 1
  wire        clear_xgif_0;    // Strobe for decode to clear interrupt flag bank 0
  wire [15:0] clear_xgif_data; // Data for decode to clear interrupt flag
 
  wire        xge;           // XGATE Module Enable
  wire        xgfrz;         // Stop XGATE in Freeze Mode
  wire        xgdbg;         // XGATE Debug Mode
  wire        xgss;          // XGATE Single Step
  wire        xgsweif_c;     // Clear XGATE Software Error Interrupt FLag
  wire        xgie;          // XGATE Interrupt Enable
  wire [ 6:0] int_req;       // Encoded interrupt request
  wire [ 6:0] xgchid;        // Channel actively being processed
  wire [15:1] xgvbr;         // XGATE vector Base Address Register
 
  wire [ 2:0] semaph_risc;   // Semaphore register select from RISC
  wire [ 7:0] host_semap;    // Semaphore status for host
//  wire [15:0] write_mem_data;
//  wire [15:0] read_mem_data;
//  wire [15:0] perif_data;
 
 
  // ---------------------------------------------------------------------------
  // Wishbone Slave Bus interface
  xgate_wbs_bus #(.ARST_LVL(ARST_LVL),
                 .SINGLE_CYCLE(SINGLE_CYCLE))
    wishbone_s(
    .wbs_dat_o( wbs_dat_o ),
    .wbs_ack_o( wbs_ack_o ),
    .wbs_clk_i( wbs_clk_i ),
    .wbs_rst_i( wbs_rst_i ),
    .arst_i( arst_i ),
    .wbs_adr_i( wbs_adr_i ),
    .wbs_dat_i( wbs_dat_i ),
    .wbs_we_i( wbs_we_i ),
    .wbs_stb_i( wbs_stb_i ),
    .wbs_cyc_i( wbs_cyc_i ),
    .wbs_sel_i( wbs_sel_i ),
 
    // outputs
    .sync_reset( sync_reset ),
    .write_xgmctl( write_xgmctl ),
    .write_xgisp74( write_xgisp74 ),
    .write_xgisp30( write_xgisp30 ),
    .write_xgvbr( write_xgvbr ),
    .write_xgif_7( write_xgif_7 ),
    .write_xgif_6( write_xgif_6 ),
    .write_xgif_5( write_xgif_5 ),
    .write_xgif_4( write_xgif_4 ),
    .write_xgif_3( write_xgif_3 ),
    .write_xgif_2( write_xgif_2 ),
    .write_xgif_1( write_xgif_1 ),
    .write_xgif_0( write_xgif_0 ),
    .write_xgswt( write_xgswt ),
    .write_xgsem( write_xgsem ),
    .write_xgccr( write_xgccr ),
    .write_xgpc( write_xgpc ),
    .write_xgr7( write_xgr7 ),
    .write_xgr6( write_xgr6 ),
    .write_xgr5( write_xgr5 ),
    .write_xgr4( write_xgr4 ),
    .write_xgr3( write_xgr3 ),
    .write_xgr2( write_xgr2 ),
    .write_xgr1( write_xgr1 ),
    // inputs    
    .async_rst_b  ( async_rst_b ),
    .read_regs    (               // in  -- read register bits
                   { xgr7,             // XGR7
                     xgr6,             // XGR6
                     xgr5,             // XGR5
                     xgr4,             // XGR4
                     xgr3,             // XGR3
                     xgr2,             // XGR2
                     xgr1,             // XGR1
                     16'b0,            // Reserved (XGR0)
                     xgate_address,    // XGPC
                     {12'h000,  negative_flag, zero_flag, overflow_flag, carry_flag},  // XGCCR
                     16'b0,  // Reserved
                     {8'h00, host_semap},  // XGSEM
                     {8'h00, xgswt},  // XGSWT
                     xgif[ 15:  0],  // XGIF_0
                     xgif[ 31: 16],  // XGIF_1
                     xgif[ 47: 32],  // XGIF_2
                     xgif[ 63: 48],  // XGIF_3
                     xgif[ 79: 64],  // XGIF_4
                     xgif[ 95: 80],  // XGIF_5
                     xgif[111: 96],  // XGIF_6
                     xgif[127:112],  // XGIF_7
                     {xgvbr[15:1], 1'b0},  // XGVBR
                     xgisp30,  // Reserved
                     xgisp74,  // Reserved
                     {8'b0, 1'b0, xgchid},  // XGCHID
                     {8'b0, xge, xgfrz, 1'b0, xgdbg, 2'b0, 1'b0, xgie}  // XGMCTL
                   }
                  )
  );
 
  // ---------------------------------------------------------------------------
  xgate_regs #(.ARST_LVL(ARST_LVL),
               .MAX_CHANNEL(MAX_CHANNEL))
    regs(
    // outputs
    .xge( xge ),
    .xgfrz( xgfrz ),
    .xgdbg( xgdbg ),
    .xgss( xgss ),
    .xgsweif_c( xgsweif_c ),
    .xgie( xgie ),
    .xgvbr( xgvbr ),
    .xgswt( xgswt ),
    .xgisp74( xgisp74 ),
    .xgisp30( xgisp30 ),
    .clear_xgif_7( clear_xgif_7 ),
    .clear_xgif_6( clear_xgif_6 ),
    .clear_xgif_5( clear_xgif_5 ),
    .clear_xgif_4( clear_xgif_4 ),
    .clear_xgif_3( clear_xgif_3 ),
    .clear_xgif_2( clear_xgif_2 ),
    .clear_xgif_1( clear_xgif_1 ),
    .clear_xgif_0( clear_xgif_0 ),
    .clear_xgif_data( clear_xgif_data ),
 
    // inputs
    .async_rst_b( async_rst_b ),
    .sync_reset( sync_reset ),
    .bus_clk( wbs_clk_i ),
    .write_bus( wbs_dat_i ),
    .write_xgmctl( write_xgmctl ),
    .write_xgisp74( write_xgisp74 ),
    .write_xgisp30( write_xgisp30 ),
    .write_xgvbr( write_xgvbr ),
    .write_xgif_7( write_xgif_7 ),
    .write_xgif_6( write_xgif_6 ),
    .write_xgif_5( write_xgif_5 ),
    .write_xgif_4( write_xgif_4 ),
    .write_xgif_3( write_xgif_3 ),
    .write_xgif_2( write_xgif_2 ),
    .write_xgif_1( write_xgif_1 ),
    .write_xgif_0( write_xgif_0 ),
    .write_xgswt( write_xgswt )
 
 
  );
 
  // ---------------------------------------------------------------------------
  xgate_risc #(.MAX_CHANNEL(MAX_CHANNEL))
    risc(
    // outputs
    .xgate_address( xgate_address ),
    .write_mem_strb_l( write_mem_strb_l ),
    .write_mem_strb_h( write_mem_strb_h ),
    .write_mem_data( write_mem_data ),
    .zero_flag( zero_flag ),
    .negative_flag( negative_flag ),
    .carry_flag( carry_flag ),
    .overflow_flag( overflow_flag ),
    .xgchid( xgchid ),
    .host_semap( host_semap ),
    .xgr1( xgr1 ),
    .xgr2( xgr2 ),
    .xgr3( xgr3 ),
    .xgr4( xgr4 ),
    .xgr5( xgr5 ),
    .xgr6( xgr6 ),
    .xgr7( xgr7 ),
    .xgif( xgif ),
 
    // inputs
    .risc_clk( risc_clk ),
    .perif_data( wbs_dat_i ),
    .async_rst_b( async_rst_b ),
    .read_mem_data( read_mem_data ),
    .xge( xge ),
    .xgfrz( xgfrz ),
    .xgdbg( xgdbg ),
    .xgss( xgss ),
    .xgvbr( xgvbr ),
    .int_req(int_req),
    .write_xgsem( write_xgsem ),
    .write_xgccr( write_xgccr ),
    .write_xgpc( write_xgpc ),
    .write_xgr7( write_xgr7 ),
    .write_xgr6( write_xgr6 ),
    .write_xgr5( write_xgr5 ),
    .write_xgr4( write_xgr4 ),
    .write_xgr3( write_xgr3 ),
    .write_xgr2( write_xgr2 ),
    .write_xgr1( write_xgr1 ),
    .clear_xgif_7( clear_xgif_7 ),
    .clear_xgif_6( clear_xgif_6 ),
    .clear_xgif_5( clear_xgif_5 ),
    .clear_xgif_4( clear_xgif_4 ),
    .clear_xgif_3( clear_xgif_3 ),
    .clear_xgif_2( clear_xgif_2 ),
    .clear_xgif_1( clear_xgif_1 ),
    .clear_xgif_0( clear_xgif_0 ),
    .clear_xgif_data( clear_xgif_data )
  );
 
  xgate_irq_encode #(.MAX_CHANNEL(MAX_CHANNEL))
    irq_encode(
    // outputs
    .int_req( int_req ),
    // inputs
    .chan_req_i( chan_req_i )
  );
 
 
endmodule  // xgate_top
 

Browse

Tools

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_top.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	rehayes	`////////////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// XGATE Coprocessor - XGATE Top Level Module`
4			`//`
5			`// Author: Robert Hayes`
6			`// rehayes@opencores.org`
7			`//`
8			`// Downloaded from: http://www.opencores.org/projects/xgate.....`
9			`//`
10			`////////////////////////////////////////////////////////////////////////////////`
11			`// Copyright (c) 2009, Robert Hayes`
12			`//`
13			`// This source file is free software: you can redistribute it and/or modify`
14			`// it under the terms of the GNU Lesser General Public License as published`
15			`// by the Free Software Foundation, either version 3 of the License, or`
16			`// (at your option) any later version.`
17			`//`
18			`// Supplemental terms.`
19			`// * Redistributions of source code must retain the above copyright`
20			`// notice, this list of conditions and the following disclaimer.`
21			`// * Neither the name of the <organization> nor the`
22			`// names of its contributors may be used to endorse or promote products`
23			`// derived from this software without specific prior written permission.`
24			`//`
25			`// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY`
26			`// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED`
27			`// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE`
28			`// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY`
29			`// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES`
30			`// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;`
31			`// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND`
32			`// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT`
33			`// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS`
34			`// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
35			`//`
36			`// You should have received a copy of the GNU General Public License`
37			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
38			`////////////////////////////////////////////////////////////////////////////////`
39			`// 45678901234567890123456789012345678901234567890123456789012345678901234567890`
40
41			`module xgate_top #(parameter ARST_LVL = 1'b0, // asynchronous reset level`
42			`parameter SINGLE_CYCLE = 1'b0, //`
43			`parameter MAX_CHANNEL = 127, // Max XGATE Interrupt Channel Number`
44			`parameter DWIDTH = 16) // Data bus width`
45			`(`
46			`// Wishbone Signals`
47			`output [DWIDTH-1:0] wbs_dat_o, // databus output`
48			`output wbs_ack_o, // bus cycle acknowledge output`
49			`input wbs_clk_i, // master clock input`
50			`input wbs_rst_i, // synchronous active high reset`
51			`input arst_i, // asynchronous reset`
52			`input [4:0] wbs_adr_i, // lower address bits`
53			`input [DWIDTH-1:0] wbs_dat_i, // databus input`
54			`input wbs_we_i, // write enable input`
55			`input wbs_stb_i, // stobe/core select signal`
56			`input wbs_cyc_i, // valid bus cycle input`
57			`input [1:0] wbs_sel_i, // Select byte in word bus transaction`
58			`// XGATE IO Signals`
59			`output [ 7:0] xgswt, // XGATE Software Trigger Register`
60			`output [15:0] xgate_address,`
61			`output write_mem_strb_l, // Strobe for writing low data byte`
62			`output write_mem_strb_h, // Strobe for writing high data bye`
63			`output [15:0] write_mem_data,`
64			`output [MAX_CHANNEL:0] xgif, // XGATE Interrupt Flag`
65			`input [15:0] read_mem_data,`
66			`input [MAX_CHANNEL:0] chan_req_i, // XGATE Interrupt request`
67			`input risc_clk, // Clock for RISC core`
68			`input scantestmode // Chip in in scan test mode`
69			`);`
70
71
72			`wire zero_flag;`
73			`wire negative_flag;`
74			`wire carry_flag;`
75			`wire overflow_flag;`
76			`wire [15:0] xgr1; // XGATE Register #1`
77			`wire [15:0] xgr2; // XGATE Register #2`
78			`wire [15:0] xgr3; // XGATE Register #3`
79			`wire [15:0] xgr4; // XGATE Register #4`
80			`wire [15:0] xgr5; // XGATE Register #5`
81			`wire [15:0] xgr6; // XGATE Register #6`
82			`wire [15:0] xgr7; // XGATE Register #7`
83
84			`wire [15:0] xgisp74; // XGATE Interrupt level 7-4 stack pointer`
85			`wire [15:0] xgisp30; // XGATE Interrupt level 3-0 stack pointer`
86
87			`wire write_xgmctl; // Write Strobe for XGMCTL register`
88			`wire write_xgisp74; // Write Strobe for XGISP74 register`
89			`wire write_xgisp31; // Write Strobe for XGISP31 register`
90			`wire write_xgvbr; // Write Strobe for XGVBR_LO register`
91			`wire write_xgif_7; // Write Strobe for Interrupt Flag Register 7`
92			`wire write_xgif_6; // Write Strobe for Interrupt Flag Register 6`
93			`wire write_xgif_5; // Write Strobe for Interrupt Flag Register 5`
94			`wire write_xgif_4; // Write Strobe for Interrupt Flag Register 4`
95			`wire write_xgif_3; // Write Strobe for Interrupt Flag Register 3`
96			`wire write_xgif_2; // Write Strobe for Interrupt Flag Register 2`
97			`wire write_xgif_1; // Write Strobe for Interrupt Flag Register 1`
98			`wire write_xgif_0; // Write Strobe for Interrupt Flag Register 0`
99			`wire write_xgswt; // Write Strobe for XGSWT register`
100			`wire write_xgsem; // Write Strobe for XGSEM register`
101			`wire write_xgccr; // Write Strobe for XGATE Condition Code Register`
102			`wire write_xgpc; // Write Strobe for XGATE Program Counter`
103			`wire write_xgr7; // Write Strobe for XGATE Data Register R7`
104			`wire write_xgr6; // Write Strobe for XGATE Data Register R6`
105			`wire write_xgr5; // Write Strobe for XGATE Data Register R5`
106			`wire write_xgr4; // Write Strobe for XGATE Data Register R4`
107			`wire write_xgr3; // Write Strobe for XGATE Data Register R3`
108			`wire write_xgr2; // Write Strobe for XGATE Data Register R2`
109			`wire write_xgr1; // Write Strobe for XGATE Data Register R1`
110
111			`wire clear_xgif_7; // Strobe for decode to clear interrupt flag bank 7`
112			`wire clear_xgif_6; // Strobe for decode to clear interrupt flag bank 6`
113			`wire clear_xgif_5; // Strobe for decode to clear interrupt flag bank 5`
114			`wire clear_xgif_4; // Strobe for decode to clear interrupt flag bank 4`
115			`wire clear_xgif_3; // Strobe for decode to clear interrupt flag bank 3`
116			`wire clear_xgif_2; // Strobe for decode to clear interrupt flag bank 2`
117			`wire clear_xgif_1; // Strobe for decode to clear interrupt flag bank 1`
118			`wire clear_xgif_0; // Strobe for decode to clear interrupt flag bank 0`
119			`wire [15:0] clear_xgif_data; // Data for decode to clear interrupt flag`
120
121			`wire xge; // XGATE Module Enable`
122			`wire xgfrz; // Stop XGATE in Freeze Mode`
123			`wire xgdbg; // XGATE Debug Mode`
124			`wire xgss; // XGATE Single Step`
125			`wire xgsweif_c; // Clear XGATE Software Error Interrupt FLag`
126			`wire xgie; // XGATE Interrupt Enable`
127			`wire [ 6:0] int_req; // Encoded interrupt request`
128			`wire [ 6:0] xgchid; // Channel actively being processed`
129			`wire [15:1] xgvbr; // XGATE vector Base Address Register`
130
131			`wire [ 2:0] semaph_risc; // Semaphore register select from RISC`
132			`wire [ 7:0] host_semap; // Semaphore status for host`
133			`// wire [15:0] write_mem_data;`
134			`// wire [15:0] read_mem_data;`
135			`// wire [15:0] perif_data;`
136
137
138			`// ---------------------------------------------------------------------------`
139			`// Wishbone Slave Bus interface`
140			`xgate_wbs_bus #(.ARST_LVL(ARST_LVL),`
141			`.SINGLE_CYCLE(SINGLE_CYCLE))`
142			`wishbone_s(`
143			`.wbs_dat_o( wbs_dat_o ),`
144			`.wbs_ack_o( wbs_ack_o ),`
145			`.wbs_clk_i( wbs_clk_i ),`
146			`.wbs_rst_i( wbs_rst_i ),`
147			`.arst_i( arst_i ),`
148			`.wbs_adr_i( wbs_adr_i ),`
149			`.wbs_dat_i( wbs_dat_i ),`
150			`.wbs_we_i( wbs_we_i ),`
151			`.wbs_stb_i( wbs_stb_i ),`
152			`.wbs_cyc_i( wbs_cyc_i ),`
153			`.wbs_sel_i( wbs_sel_i ),`
154
155			`// outputs`
156			`.sync_reset( sync_reset ),`
157			`.write_xgmctl( write_xgmctl ),`
158			`.write_xgisp74( write_xgisp74 ),`
159			`.write_xgisp30( write_xgisp30 ),`
160			`.write_xgvbr( write_xgvbr ),`
161			`.write_xgif_7( write_xgif_7 ),`
162			`.write_xgif_6( write_xgif_6 ),`
163			`.write_xgif_5( write_xgif_5 ),`
164			`.write_xgif_4( write_xgif_4 ),`
165			`.write_xgif_3( write_xgif_3 ),`
166			`.write_xgif_2( write_xgif_2 ),`
167			`.write_xgif_1( write_xgif_1 ),`
168			`.write_xgif_0( write_xgif_0 ),`
169			`.write_xgswt( write_xgswt ),`
170			`.write_xgsem( write_xgsem ),`
171			`.write_xgccr( write_xgccr ),`
172			`.write_xgpc( write_xgpc ),`
173			`.write_xgr7( write_xgr7 ),`
174			`.write_xgr6( write_xgr6 ),`
175			`.write_xgr5( write_xgr5 ),`
176			`.write_xgr4( write_xgr4 ),`
177			`.write_xgr3( write_xgr3 ),`
178			`.write_xgr2( write_xgr2 ),`
179			`.write_xgr1( write_xgr1 ),`
180			`// inputs`
181			`.async_rst_b ( async_rst_b ),`
182			`.read_regs ( // in -- read register bits`
183			`{ xgr7, // XGR7`
184			`xgr6, // XGR6`
185			`xgr5, // XGR5`
186			`xgr4, // XGR4`
187			`xgr3, // XGR3`
188			`xgr2, // XGR2`
189			`xgr1, // XGR1`
190			`16'b0, // Reserved (XGR0)`
191			`xgate_address, // XGPC`
192			`{12'h000, negative_flag, zero_flag, overflow_flag, carry_flag}, // XGCCR`
193			`16'b0, // Reserved`
194			`{8'h00, host_semap}, // XGSEM`
195			`{8'h00, xgswt}, // XGSWT`
196			`xgif[ 15: 0], // XGIF_0`
197			`xgif[ 31: 16], // XGIF_1`
198			`xgif[ 47: 32], // XGIF_2`
199			`xgif[ 63: 48], // XGIF_3`
200			`xgif[ 79: 64], // XGIF_4`
201			`xgif[ 95: 80], // XGIF_5`
202			`xgif[111: 96], // XGIF_6`
203			`xgif[127:112], // XGIF_7`
204			`{xgvbr[15:1], 1'b0}, // XGVBR`
205			`xgisp30, // Reserved`
206			`xgisp74, // Reserved`
207			`{8'b0, 1'b0, xgchid}, // XGCHID`
208			`{8'b0, xge, xgfrz, 1'b0, xgdbg, 2'b0, 1'b0, xgie} // XGMCTL`
209			`}`
210			`)`
211			`);`
212
213			`// ---------------------------------------------------------------------------`
214			`xgate_regs #(.ARST_LVL(ARST_LVL),`
215			`.MAX_CHANNEL(MAX_CHANNEL))`
216			`regs(`
217			`// outputs`
218			`.xge( xge ),`
219			`.xgfrz( xgfrz ),`
220			`.xgdbg( xgdbg ),`
221			`.xgss( xgss ),`
222			`.xgsweif_c( xgsweif_c ),`
223			`.xgie( xgie ),`
224			`.xgvbr( xgvbr ),`
225			`.xgswt( xgswt ),`
226			`.xgisp74( xgisp74 ),`
227			`.xgisp30( xgisp30 ),`
228			`.clear_xgif_7( clear_xgif_7 ),`
229			`.clear_xgif_6( clear_xgif_6 ),`
230			`.clear_xgif_5( clear_xgif_5 ),`
231			`.clear_xgif_4( clear_xgif_4 ),`
232			`.clear_xgif_3( clear_xgif_3 ),`
233			`.clear_xgif_2( clear_xgif_2 ),`
234			`.clear_xgif_1( clear_xgif_1 ),`
235			`.clear_xgif_0( clear_xgif_0 ),`
236			`.clear_xgif_data( clear_xgif_data ),`
237
238			`// inputs`
239			`.async_rst_b( async_rst_b ),`
240			`.sync_reset( sync_reset ),`
241			`.bus_clk( wbs_clk_i ),`
242			`.write_bus( wbs_dat_i ),`
243			`.write_xgmctl( write_xgmctl ),`
244			`.write_xgisp74( write_xgisp74 ),`
245			`.write_xgisp30( write_xgisp30 ),`
246			`.write_xgvbr( write_xgvbr ),`
247			`.write_xgif_7( write_xgif_7 ),`
248			`.write_xgif_6( write_xgif_6 ),`
249			`.write_xgif_5( write_xgif_5 ),`
250			`.write_xgif_4( write_xgif_4 ),`
251			`.write_xgif_3( write_xgif_3 ),`
252			`.write_xgif_2( write_xgif_2 ),`
253			`.write_xgif_1( write_xgif_1 ),`
254			`.write_xgif_0( write_xgif_0 ),`
255			`.write_xgswt( write_xgswt )`
256
257
258			`);`
259
260			`// ---------------------------------------------------------------------------`
261			`xgate_risc #(.MAX_CHANNEL(MAX_CHANNEL))`
262			`risc(`
263			`// outputs`
264			`.xgate_address( xgate_address ),`
265			`.write_mem_strb_l( write_mem_strb_l ),`
266			`.write_mem_strb_h( write_mem_strb_h ),`
267			`.write_mem_data( write_mem_data ),`
268			`.zero_flag( zero_flag ),`
269			`.negative_flag( negative_flag ),`
270			`.carry_flag( carry_flag ),`
271			`.overflow_flag( overflow_flag ),`
272			`.xgchid( xgchid ),`
273			`.host_semap( host_semap ),`
274			`.xgr1( xgr1 ),`
275			`.xgr2( xgr2 ),`
276			`.xgr3( xgr3 ),`
277			`.xgr4( xgr4 ),`
278			`.xgr5( xgr5 ),`
279			`.xgr6( xgr6 ),`
280			`.xgr7( xgr7 ),`
281			`.xgif( xgif ),`
282
283			`// inputs`
284			`.risc_clk( risc_clk ),`
285			`.perif_data( wbs_dat_i ),`
286			`.async_rst_b( async_rst_b ),`
287			`.read_mem_data( read_mem_data ),`
288			`.xge( xge ),`
289			`.xgfrz( xgfrz ),`
290			`.xgdbg( xgdbg ),`
291			`.xgss( xgss ),`
292			`.xgvbr( xgvbr ),`
293			`.int_req(int_req),`
294			`.write_xgsem( write_xgsem ),`
295			`.write_xgccr( write_xgccr ),`
296			`.write_xgpc( write_xgpc ),`
297			`.write_xgr7( write_xgr7 ),`
298			`.write_xgr6( write_xgr6 ),`
299			`.write_xgr5( write_xgr5 ),`
300			`.write_xgr4( write_xgr4 ),`
301			`.write_xgr3( write_xgr3 ),`
302			`.write_xgr2( write_xgr2 ),`
303			`.write_xgr1( write_xgr1 ),`
304			`.clear_xgif_7( clear_xgif_7 ),`
305			`.clear_xgif_6( clear_xgif_6 ),`
306			`.clear_xgif_5( clear_xgif_5 ),`
307			`.clear_xgif_4( clear_xgif_4 ),`
308			`.clear_xgif_3( clear_xgif_3 ),`
309			`.clear_xgif_2( clear_xgif_2 ),`
310			`.clear_xgif_1( clear_xgif_1 ),`
311			`.clear_xgif_0( clear_xgif_0 ),`
312			`.clear_xgif_data( clear_xgif_data )`
313			`);`
314
315			`xgate_irq_encode #(.MAX_CHANNEL(MAX_CHANNEL))`
316			`irq_encode(`
317			`// outputs`
318			`.int_req( int_req ),`
319			`// inputs`
320			`.chan_req_i( chan_req_i )`
321			`);`
322
323
324			`endmodule // xgate_top`
325