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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_top.v] - Blame information for rev 30

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Line No. Rev Author Line
1 2 rehayes
////////////////////////////////////////////////////////////////////////////////
2
//
3
//  XGATE Coprocessor - XGATE Top Level Module
4
//
5
//  Author: Robert Hayes
6
//          rehayes@opencores.org
7
//
8
//  Downloaded from: http://www.opencores.org/projects/xgate.....
9
//
10
////////////////////////////////////////////////////////////////////////////////
11
// Copyright (c) 2009, Robert Hayes
12
//
13
// This source file is free software: you can redistribute it and/or modify
14
// it under the terms of the GNU Lesser General Public License as published
15
// by the Free Software Foundation, either version 3 of the License, or
16
// (at your option) any later version.
17
//
18
// Supplemental terms.
19
//     * Redistributions of source code must retain the above copyright
20
//       notice, this list of conditions and the following disclaimer.
21
//     * Neither the name of the <organization> nor the
22
//       names of its contributors may be used to endorse or promote products
23
//       derived from this software without specific prior written permission.
24
//
25
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
31
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35
//
36
// You should have received a copy of the GNU General Public License
37
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
38
////////////////////////////////////////////////////////////////////////////////
39
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
40
 
41
module xgate_top #(parameter ARST_LVL = 1'b0,      // asynchronous reset level
42
                   parameter SINGLE_CYCLE = 1'b0,  // 
43
                   parameter MAX_CHANNEL = 127,    // Max XGATE Interrupt Channel Number
44
                   parameter DWIDTH = 16)          // Data bus width
45
  (
46 5 rehayes
  // Wishbone Slave Signals
47
  output    [DWIDTH-1:0] wbs_dat_o,     // databus output
48
  output                 wbs_ack_o,     // bus cycle acknowledge output
49
  input                  wbs_clk_i,     // master clock input
50
  input                  wbs_rst_i,     // synchronous active high reset
51
  input                  arst_i,        // asynchronous reset
52
  input            [4:0] wbs_adr_i,     // lower address bits
53
  input     [DWIDTH-1:0] wbs_dat_i,     // databus input
54
  input                  wbs_we_i,      // write enable input
55
  input                  wbs_stb_i,     // stobe/core select signal
56
  input                  wbs_cyc_i,     // valid bus cycle input
57
  input            [1:0] wbs_sel_i,     // Select byte in word bus transaction
58
  // Wishbone Master Signals
59
  output    [DWIDTH-1:0] wbm_dat_o,     // databus output
60
  output                 wbm_we_o,      // write enable output
61
  output                 wbm_stb_o,     // stobe/core select signal
62
  output                 wbm_cyc_o,     // valid bus cycle output
63
  output          [ 1:0] wbm_sel_o,     // Select byte in word bus transaction
64
  output          [15:0] wbm_adr_o,     // Address bits
65
  input     [DWIDTH-1:0] wbm_dat_i,     // databus input
66
  input                  wbm_ack_i,     // bus cycle acknowledge input
67 2 rehayes
  // XGATE IO Signals
68 5 rehayes
  output          [ 7:0] xgswt,         // XGATE Software Trigger Register
69 2 rehayes
  output                 write_mem_strb_l, // Strobe for writing low data byte
70
  output                 write_mem_strb_h, // Strobe for writing high data bye
71 12 rehayes
  output                 xg_sw_irq,        // Xgate Software interrupt
72 2 rehayes
  output [MAX_CHANNEL:0] xgif,             // XGATE Interrupt Flag
73
  input  [MAX_CHANNEL:0] chan_req_i,       // XGATE Interrupt request
74
  input                  risc_clk,         // Clock for RISC core
75 30 rehayes
  input                  debug_mode_i,     // Force RISC core into debug mode
76
  input                  secure_mode_i,    // Limit host asscess to Xgate RISC registers
77 2 rehayes
  input                  scantestmode      // Chip in in scan test mode
78
  );
79
 
80
  wire        zero_flag;
81
  wire        negative_flag;
82
  wire        carry_flag;
83
  wire        overflow_flag;
84
  wire [15:0] xgr1;          // XGATE Register #1
85
  wire [15:0] xgr2;          // XGATE Register #2
86
  wire [15:0] xgr3;          // XGATE Register #3
87
  wire [15:0] xgr4;          // XGATE Register #4
88
  wire [15:0] xgr5;          // XGATE Register #5
89
  wire [15:0] xgr6;          // XGATE Register #6
90
  wire [15:0] xgr7;          // XGATE Register #7
91
 
92
  wire [15:0] xgisp74;       // XGATE Interrupt level 7-4 stack pointer
93
  wire [15:0] xgisp30;       // XGATE Interrupt level 3-0 stack pointer
94
 
95
  wire        write_xgmctl;  // Write Strobe for XGMCTL register
96 17 rehayes
  wire        write_xgchid;  // Write Strobe for XGCHID register
97 2 rehayes
  wire        write_xgisp74; // Write Strobe for XGISP74 register
98 25 rehayes
  wire        write_xgisp30; // Write Strobe for XGISP30 register
99 2 rehayes
  wire        write_xgvbr;   // Write Strobe for XGVBR_LO register
100
  wire        write_xgif_7;  // Write Strobe for Interrupt Flag Register 7
101
  wire        write_xgif_6;  // Write Strobe for Interrupt Flag Register 6
102
  wire        write_xgif_5;  // Write Strobe for Interrupt Flag Register 5
103
  wire        write_xgif_4;  // Write Strobe for Interrupt Flag Register 4
104
  wire        write_xgif_3;  // Write Strobe for Interrupt Flag Register 3
105
  wire        write_xgif_2;  // Write Strobe for Interrupt Flag Register 2
106
  wire        write_xgif_1;  // Write Strobe for Interrupt Flag Register 1
107
  wire        write_xgif_0;  // Write Strobe for Interrupt Flag Register 0
108
  wire        write_xgswt;   // Write Strobe for XGSWT register
109
  wire        write_xgsem;   // Write Strobe for XGSEM register
110
  wire        write_xgccr;   // Write Strobe for XGATE Condition Code Register
111
  wire        write_xgpc;    // Write Strobe for XGATE Program Counter
112
  wire        write_xgr7;    // Write Strobe for XGATE Data Register R7
113
  wire        write_xgr6;    // Write Strobe for XGATE Data Register R6
114
  wire        write_xgr5;    // Write Strobe for XGATE Data Register R5
115
  wire        write_xgr4;    // Write Strobe for XGATE Data Register R4
116
  wire        write_xgr3;    // Write Strobe for XGATE Data Register R3
117
  wire        write_xgr2;    // Write Strobe for XGATE Data Register R2
118
  wire        write_xgr1;    // Write Strobe for XGATE Data Register R1
119
 
120
  wire        clear_xgif_7;    // Strobe for decode to clear interrupt flag bank 7
121
  wire        clear_xgif_6;    // Strobe for decode to clear interrupt flag bank 6
122
  wire        clear_xgif_5;    // Strobe for decode to clear interrupt flag bank 5
123
  wire        clear_xgif_4;    // Strobe for decode to clear interrupt flag bank 4
124
  wire        clear_xgif_3;    // Strobe for decode to clear interrupt flag bank 3
125
  wire        clear_xgif_2;    // Strobe for decode to clear interrupt flag bank 2
126
  wire        clear_xgif_1;    // Strobe for decode to clear interrupt flag bank 1
127
  wire        clear_xgif_0;    // Strobe for decode to clear interrupt flag bank 0
128
  wire [15:0] clear_xgif_data; // Data for decode to clear interrupt flag
129
 
130
  wire        xge;           // XGATE Module Enable
131
  wire        xgfrz;         // Stop XGATE in Freeze Mode
132 15 rehayes
  wire        xgdbg_set;     // Enter XGATE Debug Mode
133
  wire        xgdbg_clear;   // Leave XGATE Debug Mode
134 2 rehayes
  wire        xgss;          // XGATE Single Step
135
  wire        xgsweif_c;     // Clear XGATE Software Error Interrupt FLag
136
  wire        xgie;          // XGATE Interrupt Enable
137
  wire [ 6:0] int_req;       // Encoded interrupt request
138
  wire [ 6:0] xgchid;        // Channel actively being processed
139 30 rehayes
  wire [127:0] xgif_status;   // Status bits of interrupt output flags that have been set
140 2 rehayes
  wire [15:1] xgvbr;         // XGATE vector Base Address Register
141 12 rehayes
  wire        brk_irq_ena;   // Enable BRK instruction to generate interrupt
142 2 rehayes
 
143 5 rehayes
  wire [15:0] xgate_address;   //
144
  wire [15:0] write_mem_data;  //
145
  wire [15:0] read_mem_data;   //
146
  wire        mem_req_ack;     //
147 12 rehayes
 
148
  wire        debug_active;    // RISC state machine in Debug mode 
149 5 rehayes
 
150 2 rehayes
  wire [ 7:0] host_semap;    // Semaphore status for host
151
//  wire [15:0] write_mem_data;
152
//  wire [15:0] read_mem_data;
153
//  wire [15:0] perif_data;
154
 
155 30 rehayes
  assign xgif = xgif_status[MAX_CHANNEL:0];
156 2 rehayes
  // ---------------------------------------------------------------------------
157
  // Wishbone Slave Bus interface
158
  xgate_wbs_bus #(.ARST_LVL(ARST_LVL),
159 5 rehayes
                  .SINGLE_CYCLE(SINGLE_CYCLE))
160 2 rehayes
    wishbone_s(
161
    .wbs_dat_o( wbs_dat_o ),
162
    .wbs_ack_o( wbs_ack_o ),
163
    .wbs_clk_i( wbs_clk_i ),
164
    .wbs_rst_i( wbs_rst_i ),
165
    .arst_i( arst_i ),
166
    .wbs_adr_i( wbs_adr_i ),
167
    .wbs_dat_i( wbs_dat_i ),
168
    .wbs_we_i( wbs_we_i ),
169
    .wbs_stb_i( wbs_stb_i ),
170
    .wbs_cyc_i( wbs_cyc_i ),
171
    .wbs_sel_i( wbs_sel_i ),
172
 
173
    // outputs
174
    .sync_reset( sync_reset ),
175
    .write_xgmctl( write_xgmctl ),
176 17 rehayes
    .write_xgchid( write_xgchid ),
177 2 rehayes
    .write_xgisp74( write_xgisp74 ),
178
    .write_xgisp30( write_xgisp30 ),
179
    .write_xgvbr( write_xgvbr ),
180
    .write_xgif_7( write_xgif_7 ),
181
    .write_xgif_6( write_xgif_6 ),
182
    .write_xgif_5( write_xgif_5 ),
183
    .write_xgif_4( write_xgif_4 ),
184
    .write_xgif_3( write_xgif_3 ),
185
    .write_xgif_2( write_xgif_2 ),
186
    .write_xgif_1( write_xgif_1 ),
187
    .write_xgif_0( write_xgif_0 ),
188
    .write_xgswt( write_xgswt ),
189
    .write_xgsem( write_xgsem ),
190
    .write_xgccr( write_xgccr ),
191
    .write_xgpc( write_xgpc ),
192
    .write_xgr7( write_xgr7 ),
193
    .write_xgr6( write_xgr6 ),
194
    .write_xgr5( write_xgr5 ),
195
    .write_xgr4( write_xgr4 ),
196
    .write_xgr3( write_xgr3 ),
197
    .write_xgr2( write_xgr2 ),
198
    .write_xgr1( write_xgr1 ),
199
    // inputs    
200
    .async_rst_b  ( async_rst_b ),
201
    .read_regs    (               // in  -- read register bits
202
                   { xgr7,             // XGR7
203
                     xgr6,             // XGR6
204
                     xgr5,             // XGR5
205
                     xgr4,             // XGR4
206
                     xgr3,             // XGR3
207
                     xgr2,             // XGR2
208
                     xgr1,             // XGR1
209
                     16'b0,            // Reserved (XGR0)
210
                     xgate_address,    // XGPC
211
                     {12'h000,  negative_flag, zero_flag, overflow_flag, carry_flag},  // XGCCR
212 17 rehayes
                     16'b0,                // Reserved
213 2 rehayes
                     {8'h00, host_semap},  // XGSEM
214 17 rehayes
                     {8'h00, xgswt},       // XGSWT
215 30 rehayes
                     xgif_status[ 15:  0], // XGIF_0
216
                     xgif_status[ 31: 16], // XGIF_1
217
                     xgif_status[ 47: 32], // XGIF_2
218
                     xgif_status[ 63: 48], // XGIF_3
219
                     xgif_status[ 79: 64], // XGIF_4
220
                     xgif_status[ 95: 80], // XGIF_5
221
                     xgif_status[111: 96], // XGIF_6
222
                     xgif_status[127:112], // XGIF_7
223 2 rehayes
                     {xgvbr[15:1], 1'b0},  // XGVBR
224 17 rehayes
                     xgisp30,              // Reserved
225
                     xgisp74,              // Reserved
226
                     {8'b0, 1'b0, xgchid}, // XGCHID
227
                     {8'b0, xge, xgfrz, debug_active, 1'b0, 1'b0, brk_irq_ena, xg_sw_irq, xgie}  // XGMCTL
228 2 rehayes
                   }
229
                  )
230
  );
231
 
232
  // ---------------------------------------------------------------------------
233
  xgate_regs #(.ARST_LVL(ARST_LVL),
234
               .MAX_CHANNEL(MAX_CHANNEL))
235
    regs(
236
    // outputs
237
    .xge( xge ),
238
    .xgfrz( xgfrz ),
239 15 rehayes
    .xgdbg_set( xgdbg_set ),
240
    .xgdbg_clear( xgdbg_clear ),
241 2 rehayes
    .xgss( xgss ),
242
    .xgsweif_c( xgsweif_c ),
243
    .xgie( xgie ),
244 12 rehayes
    .brk_irq_ena( brk_irq_ena ),
245 2 rehayes
    .xgvbr( xgvbr ),
246
    .xgswt( xgswt ),
247
    .xgisp74( xgisp74 ),
248
    .xgisp30( xgisp30 ),
249
    .clear_xgif_7( clear_xgif_7 ),
250
    .clear_xgif_6( clear_xgif_6 ),
251
    .clear_xgif_5( clear_xgif_5 ),
252
    .clear_xgif_4( clear_xgif_4 ),
253
    .clear_xgif_3( clear_xgif_3 ),
254
    .clear_xgif_2( clear_xgif_2 ),
255
    .clear_xgif_1( clear_xgif_1 ),
256
    .clear_xgif_0( clear_xgif_0 ),
257
    .clear_xgif_data( clear_xgif_data ),
258
 
259
    // inputs
260
    .async_rst_b( async_rst_b ),
261
    .sync_reset( sync_reset ),
262
    .bus_clk( wbs_clk_i ),
263
    .write_bus( wbs_dat_i ),
264
    .write_xgmctl( write_xgmctl ),
265
    .write_xgisp74( write_xgisp74 ),
266
    .write_xgisp30( write_xgisp30 ),
267
    .write_xgvbr( write_xgvbr ),
268
    .write_xgif_7( write_xgif_7 ),
269
    .write_xgif_6( write_xgif_6 ),
270
    .write_xgif_5( write_xgif_5 ),
271
    .write_xgif_4( write_xgif_4 ),
272
    .write_xgif_3( write_xgif_3 ),
273
    .write_xgif_2( write_xgif_2 ),
274
    .write_xgif_1( write_xgif_1 ),
275
    .write_xgif_0( write_xgif_0 ),
276
    .write_xgswt( write_xgswt )
277
  );
278
 
279
  // ---------------------------------------------------------------------------
280
  xgate_risc #(.MAX_CHANNEL(MAX_CHANNEL))
281
    risc(
282
    // outputs
283
    .xgate_address( xgate_address ),
284
    .write_mem_strb_l( write_mem_strb_l ),
285
    .write_mem_strb_h( write_mem_strb_h ),
286
    .write_mem_data( write_mem_data ),
287
    .zero_flag( zero_flag ),
288
    .negative_flag( negative_flag ),
289
    .carry_flag( carry_flag ),
290
    .overflow_flag( overflow_flag ),
291
    .xgchid( xgchid ),
292
    .host_semap( host_semap ),
293
    .xgr1( xgr1 ),
294
    .xgr2( xgr2 ),
295
    .xgr3( xgr3 ),
296
    .xgr4( xgr4 ),
297
    .xgr5( xgr5 ),
298
    .xgr6( xgr6 ),
299
    .xgr7( xgr7 ),
300 30 rehayes
    .xgif_status( xgif_status ),
301 12 rehayes
    .debug_active( debug_active ),
302
    .xg_sw_irq( xg_sw_irq ),
303 2 rehayes
 
304
    // inputs
305
    .risc_clk( risc_clk ),
306
    .perif_data( wbs_dat_i ),
307
    .async_rst_b( async_rst_b ),
308
    .read_mem_data( read_mem_data ),
309 5 rehayes
    .mem_req_ack( mem_req_ack ),
310 2 rehayes
    .xge( xge ),
311
    .xgfrz( xgfrz ),
312 15 rehayes
    .xgdbg_set( xgdbg_set ),
313
    .xgdbg_clear( xgdbg_clear ),
314 30 rehayes
    .debug_mode_i(debug_mode_i),
315 2 rehayes
    .xgss( xgss ),
316
    .xgvbr( xgvbr ),
317 5 rehayes
    .int_req( int_req ),
318 12 rehayes
    .xgie( xgie ),
319
    .brk_irq_ena( brk_irq_ena ),
320 2 rehayes
    .write_xgsem( write_xgsem ),
321 17 rehayes
    .write_xgchid( write_xgchid ),
322 2 rehayes
    .write_xgccr( write_xgccr ),
323
    .write_xgpc( write_xgpc ),
324
    .write_xgr7( write_xgr7 ),
325
    .write_xgr6( write_xgr6 ),
326
    .write_xgr5( write_xgr5 ),
327
    .write_xgr4( write_xgr4 ),
328
    .write_xgr3( write_xgr3 ),
329
    .write_xgr2( write_xgr2 ),
330
    .write_xgr1( write_xgr1 ),
331
    .clear_xgif_7( clear_xgif_7 ),
332
    .clear_xgif_6( clear_xgif_6 ),
333
    .clear_xgif_5( clear_xgif_5 ),
334
    .clear_xgif_4( clear_xgif_4 ),
335
    .clear_xgif_3( clear_xgif_3 ),
336
    .clear_xgif_2( clear_xgif_2 ),
337
    .clear_xgif_1( clear_xgif_1 ),
338
    .clear_xgif_0( clear_xgif_0 ),
339 12 rehayes
    .xgsweif_c( xgsweif_c ),
340 2 rehayes
    .clear_xgif_data( clear_xgif_data )
341
  );
342
 
343
  xgate_irq_encode #(.MAX_CHANNEL(MAX_CHANNEL))
344
    irq_encode(
345
    // outputs
346
    .int_req( int_req ),
347
    // inputs
348
    .chan_req_i( chan_req_i )
349
  );
350
 
351 5 rehayes
  // ---------------------------------------------------------------------------
352
  // Wishbone Master Bus interface
353
  xgate_wbm_bus #(.ARST_LVL(ARST_LVL))
354
    wishbone_m(
355
  // Wishbone Master Signals
356
    .wbm_dat_o( wbm_dat_o ),
357
    .wbm_we_o( wbm_we_o ),
358
    .wbm_stb_o( wbm_stb_o ),
359
    .wbm_cyc_o( wbm_cyc_o ),
360
    .wbm_sel_o( wbm_sel_o ),
361
    .wbm_adr_o( wbm_adr_o ),
362
    .wbm_dat_i( wbm_dat_i ),
363
    .wbm_ack_i( wbm_ack_i ),
364
    .wbs_clk_i( wbs_clk_i ),
365
    .wbs_rst_i( wbs_rst_i ),
366
    .arst_i( arst_i ),
367
 // XGATE Control Signals
368
    .read_mem_data( read_mem_data ),
369
    .xgate_address( xgate_address ),
370
    .mem_req_ack( mem_req_ack ),
371
    .write_mem_strb_l( write_mem_strb_l ),
372
    .write_mem_strb_h( write_mem_strb_h ),
373
    .write_mem_data( write_mem_data )
374
  );
375 2 rehayes
 
376 5 rehayes
 
377 2 rehayes
endmodule  // xgate_top
378
 

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