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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_top.v] - Blame information for rev 63

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1 2 rehayes
////////////////////////////////////////////////////////////////////////////////
2
//
3
//  XGATE Coprocessor - XGATE Top Level Module
4
//
5
//  Author: Robert Hayes
6
//          rehayes@opencores.org
7
//
8
//  Downloaded from: http://www.opencores.org/projects/xgate.....
9
//
10
////////////////////////////////////////////////////////////////////////////////
11
// Copyright (c) 2009, Robert Hayes
12
//
13
// This source file is free software: you can redistribute it and/or modify
14
// it under the terms of the GNU Lesser General Public License as published
15
// by the Free Software Foundation, either version 3 of the License, or
16
// (at your option) any later version.
17
//
18
// Supplemental terms.
19
//     * Redistributions of source code must retain the above copyright
20
//       notice, this list of conditions and the following disclaimer.
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//     * Neither the name of the <organization> nor the
22
//       names of its contributors may be used to endorse or promote products
23
//       derived from this software without specific prior written permission.
24
//
25
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28
// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
31
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35
//
36
// You should have received a copy of the GNU General Public License
37
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
38
////////////////////////////////////////////////////////////////////////////////
39
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
40
 
41
module xgate_top #(parameter ARST_LVL = 1'b0,      // asynchronous reset level
42
                   parameter SINGLE_CYCLE = 1'b0,  // 
43
                   parameter MAX_CHANNEL = 127,    // Max XGATE Interrupt Channel Number
44
                   parameter DWIDTH = 16)          // Data bus width
45
  (
46 5 rehayes
  // Wishbone Slave Signals
47
  output    [DWIDTH-1:0] wbs_dat_o,     // databus output
48
  output                 wbs_ack_o,     // bus cycle acknowledge output
49 53 rehayes
  output                 wbs_err_o,     // bus error, lost module select durning wait state
50 5 rehayes
  input                  wbs_clk_i,     // master clock input
51
  input                  wbs_rst_i,     // synchronous active high reset
52
  input                  arst_i,        // asynchronous reset
53 41 rehayes
  input            [5:1] wbs_adr_i,     // lower address bits
54 5 rehayes
  input     [DWIDTH-1:0] wbs_dat_i,     // databus input
55
  input                  wbs_we_i,      // write enable input
56
  input                  wbs_stb_i,     // stobe/core select signal
57
  input                  wbs_cyc_i,     // valid bus cycle input
58
  input            [1:0] wbs_sel_i,     // Select byte in word bus transaction
59
  // Wishbone Master Signals
60
  output    [DWIDTH-1:0] wbm_dat_o,     // databus output
61
  output                 wbm_we_o,      // write enable output
62
  output                 wbm_stb_o,     // stobe/core select signal
63
  output                 wbm_cyc_o,     // valid bus cycle output
64
  output          [ 1:0] wbm_sel_o,     // Select byte in word bus transaction
65
  output          [15:0] wbm_adr_o,     // Address bits
66
  input     [DWIDTH-1:0] wbm_dat_i,     // databus input
67
  input                  wbm_ack_i,     // bus cycle acknowledge input
68 2 rehayes
  // XGATE IO Signals
69 5 rehayes
  output          [ 7:0] xgswt,         // XGATE Software Trigger Register
70 12 rehayes
  output                 xg_sw_irq,        // Xgate Software interrupt
71 2 rehayes
  output [MAX_CHANNEL:0] xgif,             // XGATE Interrupt Flag
72
  input  [MAX_CHANNEL:0] chan_req_i,       // XGATE Interrupt request
73
  input                  risc_clk,         // Clock for RISC core
74 30 rehayes
  input                  debug_mode_i,     // Force RISC core into debug mode
75
  input                  secure_mode_i,    // Limit host asscess to Xgate RISC registers
76 2 rehayes
  input                  scantestmode      // Chip in in scan test mode
77
  );
78
 
79
  wire        zero_flag;
80
  wire        negative_flag;
81
  wire        carry_flag;
82
  wire        overflow_flag;
83
  wire [15:0] xgr1;          // XGATE Register #1
84
  wire [15:0] xgr2;          // XGATE Register #2
85
  wire [15:0] xgr3;          // XGATE Register #3
86
  wire [15:0] xgr4;          // XGATE Register #4
87
  wire [15:0] xgr5;          // XGATE Register #5
88
  wire [15:0] xgr6;          // XGATE Register #6
89
  wire [15:0] xgr7;          // XGATE Register #7
90
 
91
  wire        write_xgmctl;  // Write Strobe for XGMCTL register
92 17 rehayes
  wire        write_xgchid;  // Write Strobe for XGCHID register
93 41 rehayes
  wire  [1:0] write_xgvbr;   // Write Strobe for XGVBR register
94
  wire  [1:0] write_xgif_7;  // Write Strobe for Interrupt Flag Register 7
95
  wire  [1:0] write_xgif_6;  // Write Strobe for Interrupt Flag Register 6
96
  wire  [1:0] write_xgif_5;  // Write Strobe for Interrupt Flag Register 5
97
  wire  [1:0] write_xgif_4;  // Write Strobe for Interrupt Flag Register 4
98
  wire  [1:0] write_xgif_3;  // Write Strobe for Interrupt Flag Register 3
99
  wire  [1:0] write_xgif_2;  // Write Strobe for Interrupt Flag Register 2
100
  wire  [1:0] write_xgif_1;  // Write Strobe for Interrupt Flag Register 1
101
  wire  [1:0] write_xgif_0;  // Write Strobe for Interrupt Flag Register 0
102 2 rehayes
  wire        write_xgswt;   // Write Strobe for XGSWT register
103
  wire        write_xgsem;   // Write Strobe for XGSEM register
104
  wire        write_xgccr;   // Write Strobe for XGATE Condition Code Register
105 41 rehayes
  wire  [1:0] write_xgpc;    // Write Strobe for XGATE Program Counter
106
  wire  [1:0] write_xgr7;    // Write Strobe for XGATE Data Register R7
107
  wire  [1:0] write_xgr6;    // Write Strobe for XGATE Data Register R6
108
  wire  [1:0] write_xgr5;    // Write Strobe for XGATE Data Register R5
109
  wire  [1:0] write_xgr4;    // Write Strobe for XGATE Data Register R4
110
  wire  [1:0] write_xgr3;    // Write Strobe for XGATE Data Register R3
111
  wire  [1:0] write_xgr2;    // Write Strobe for XGATE Data Register R2
112
  wire  [1:0] write_xgr1;    // Write Strobe for XGATE Data Register R1
113 2 rehayes
 
114
  wire        clear_xgif_7;    // Strobe for decode to clear interrupt flag bank 7
115
  wire        clear_xgif_6;    // Strobe for decode to clear interrupt flag bank 6
116
  wire        clear_xgif_5;    // Strobe for decode to clear interrupt flag bank 5
117
  wire        clear_xgif_4;    // Strobe for decode to clear interrupt flag bank 4
118
  wire        clear_xgif_3;    // Strobe for decode to clear interrupt flag bank 3
119
  wire        clear_xgif_2;    // Strobe for decode to clear interrupt flag bank 2
120
  wire        clear_xgif_1;    // Strobe for decode to clear interrupt flag bank 1
121
  wire        clear_xgif_0;    // Strobe for decode to clear interrupt flag bank 0
122
  wire [15:0] clear_xgif_data; // Data for decode to clear interrupt flag
123
 
124
  wire        xge;           // XGATE Module Enable
125
  wire        xgfrz;         // Stop XGATE in Freeze Mode
126 15 rehayes
  wire        xgdbg_set;     // Enter XGATE Debug Mode
127
  wire        xgdbg_clear;   // Leave XGATE Debug Mode
128 41 rehayes
  wire        xgfact;        // Fake Activity
129 2 rehayes
  wire        xgss;          // XGATE Single Step
130
  wire        xgsweif_c;     // Clear XGATE Software Error Interrupt FLag
131
  wire        xgie;          // XGATE Interrupt Enable
132
  wire [ 6:0] int_req;       // Encoded interrupt request
133
  wire [ 6:0] xgchid;        // Channel actively being processed
134 30 rehayes
  wire [127:0] xgif_status;   // Status bits of interrupt output flags that have been set
135 2 rehayes
  wire [15:1] xgvbr;         // XGATE vector Base Address Register
136 12 rehayes
  wire        brk_irq_ena;   // Enable BRK instruction to generate interrupt
137 2 rehayes
 
138 5 rehayes
  wire [15:0] xgate_address;   //
139
  wire [15:0] write_mem_data;  //
140
  wire [15:0] read_mem_data;   //
141 34 rehayes
  wire        mem_access;      //
142 5 rehayes
  wire        mem_req_ack;     //
143 12 rehayes
 
144
  wire        debug_active;    // RISC state machine in Debug mode 
145 53 rehayes
  wire        debug_ack;       // Clear debug register
146
  wire        single_step;     // Pulse to trigger a single instruction execution in debug mode
147
  wire        ss_mem_ack;      // WISHBONE Bus has granted single step memory access
148 5 rehayes
 
149 63 rehayes
  wire [ 7:0] host_semap;       // Semaphore status for host
150
  wire        write_mem_strb_l; // Strobe for writing low data byte
151
  wire        write_mem_strb_h; // Strobe for writing high data bye
152 2 rehayes
 
153 30 rehayes
  assign xgif = xgif_status[MAX_CHANNEL:0];
154 2 rehayes
  // ---------------------------------------------------------------------------
155
  // Wishbone Slave Bus interface
156
  xgate_wbs_bus #(.ARST_LVL(ARST_LVL),
157 5 rehayes
                  .SINGLE_CYCLE(SINGLE_CYCLE))
158 2 rehayes
    wishbone_s(
159
    .wbs_dat_o( wbs_dat_o ),
160
    .wbs_ack_o( wbs_ack_o ),
161 53 rehayes
    .wbs_err_o( wbs_err_o ),
162 2 rehayes
    .wbs_clk_i( wbs_clk_i ),
163
    .wbs_rst_i( wbs_rst_i ),
164
    .arst_i( arst_i ),
165
    .wbs_adr_i( wbs_adr_i ),
166
    .wbs_dat_i( wbs_dat_i ),
167
    .wbs_we_i( wbs_we_i ),
168
    .wbs_stb_i( wbs_stb_i ),
169
    .wbs_cyc_i( wbs_cyc_i ),
170
    .wbs_sel_i( wbs_sel_i ),
171
 
172
    // outputs
173
    .sync_reset( sync_reset ),
174
    .write_xgmctl( write_xgmctl ),
175 17 rehayes
    .write_xgchid( write_xgchid ),
176 2 rehayes
    .write_xgvbr( write_xgvbr ),
177
    .write_xgif_7( write_xgif_7 ),
178
    .write_xgif_6( write_xgif_6 ),
179
    .write_xgif_5( write_xgif_5 ),
180
    .write_xgif_4( write_xgif_4 ),
181
    .write_xgif_3( write_xgif_3 ),
182
    .write_xgif_2( write_xgif_2 ),
183
    .write_xgif_1( write_xgif_1 ),
184
    .write_xgif_0( write_xgif_0 ),
185
    .write_xgswt( write_xgswt ),
186
    .write_xgsem( write_xgsem ),
187
    .write_xgccr( write_xgccr ),
188
    .write_xgpc( write_xgpc ),
189
    .write_xgr7( write_xgr7 ),
190
    .write_xgr6( write_xgr6 ),
191
    .write_xgr5( write_xgr5 ),
192
    .write_xgr4( write_xgr4 ),
193
    .write_xgr3( write_xgr3 ),
194
    .write_xgr2( write_xgr2 ),
195
    .write_xgr1( write_xgr1 ),
196
    // inputs    
197
    .async_rst_b  ( async_rst_b ),
198
    .read_regs    (               // in  -- read register bits
199
                   { xgr7,             // XGR7
200
                     xgr6,             // XGR6
201
                     xgr5,             // XGR5
202
                     xgr4,             // XGR4
203
                     xgr3,             // XGR3
204
                     xgr2,             // XGR2
205
                     xgr1,             // XGR1
206
                     16'b0,            // Reserved (XGR0)
207
                     xgate_address,    // XGPC
208
                     {12'h000,  negative_flag, zero_flag, overflow_flag, carry_flag},  // XGCCR
209 17 rehayes
                     16'b0,                // Reserved
210 2 rehayes
                     {8'h00, host_semap},  // XGSEM
211 17 rehayes
                     {8'h00, xgswt},       // XGSWT
212 30 rehayes
                     xgif_status[ 15:  0], // XGIF_0
213
                     xgif_status[ 31: 16], // XGIF_1
214
                     xgif_status[ 47: 32], // XGIF_2
215
                     xgif_status[ 63: 48], // XGIF_3
216
                     xgif_status[ 79: 64], // XGIF_4
217
                     xgif_status[ 95: 80], // XGIF_5
218
                     xgif_status[111: 96], // XGIF_6
219
                     xgif_status[127:112], // XGIF_7
220 2 rehayes
                     {xgvbr[15:1], 1'b0},  // XGVBR
221 43 rehayes
                     16'b0,                // Reserved
222
                     16'b0,                // Reserved
223 17 rehayes
                     {8'b0, 1'b0, xgchid}, // XGCHID
224 41 rehayes
                     {8'b0, xge, xgfrz, debug_active, 1'b0, xgfact, brk_irq_ena, xg_sw_irq, xgie}  // XGMCTL
225 2 rehayes
                   }
226
                  )
227
  );
228
 
229
  // ---------------------------------------------------------------------------
230
  xgate_regs #(.ARST_LVL(ARST_LVL),
231
               .MAX_CHANNEL(MAX_CHANNEL))
232
    regs(
233
    // outputs
234
    .xge( xge ),
235
    .xgfrz( xgfrz ),
236 15 rehayes
    .xgdbg_set( xgdbg_set ),
237
    .xgdbg_clear( xgdbg_clear ),
238 41 rehayes
    .xgfact( xgfact ),
239 2 rehayes
    .xgss( xgss ),
240
    .xgsweif_c( xgsweif_c ),
241
    .xgie( xgie ),
242 12 rehayes
    .brk_irq_ena( brk_irq_ena ),
243 2 rehayes
    .xgvbr( xgvbr ),
244
    .xgswt( xgswt ),
245
    .clear_xgif_7( clear_xgif_7 ),
246
    .clear_xgif_6( clear_xgif_6 ),
247
    .clear_xgif_5( clear_xgif_5 ),
248
    .clear_xgif_4( clear_xgif_4 ),
249
    .clear_xgif_3( clear_xgif_3 ),
250
    .clear_xgif_2( clear_xgif_2 ),
251
    .clear_xgif_1( clear_xgif_1 ),
252
    .clear_xgif_0( clear_xgif_0 ),
253
    .clear_xgif_data( clear_xgif_data ),
254
 
255
    // inputs
256
    .async_rst_b( async_rst_b ),
257
    .sync_reset( sync_reset ),
258
    .bus_clk( wbs_clk_i ),
259
    .write_bus( wbs_dat_i ),
260
    .write_xgmctl( write_xgmctl ),
261
    .write_xgvbr( write_xgvbr ),
262
    .write_xgif_7( write_xgif_7 ),
263
    .write_xgif_6( write_xgif_6 ),
264
    .write_xgif_5( write_xgif_5 ),
265
    .write_xgif_4( write_xgif_4 ),
266
    .write_xgif_3( write_xgif_3 ),
267
    .write_xgif_2( write_xgif_2 ),
268
    .write_xgif_1( write_xgif_1 ),
269
    .write_xgif_0( write_xgif_0 ),
270 53 rehayes
    .write_xgswt( write_xgswt ),
271
    .debug_ack( debug_ack )
272 2 rehayes
  );
273
 
274
  // ---------------------------------------------------------------------------
275
  xgate_risc #(.MAX_CHANNEL(MAX_CHANNEL))
276
    risc(
277
    // outputs
278
    .xgate_address( xgate_address ),
279
    .write_mem_strb_l( write_mem_strb_l ),
280
    .write_mem_strb_h( write_mem_strb_h ),
281
    .write_mem_data( write_mem_data ),
282
    .zero_flag( zero_flag ),
283
    .negative_flag( negative_flag ),
284
    .carry_flag( carry_flag ),
285
    .overflow_flag( overflow_flag ),
286
    .xgchid( xgchid ),
287
    .host_semap( host_semap ),
288
    .xgr1( xgr1 ),
289
    .xgr2( xgr2 ),
290
    .xgr3( xgr3 ),
291
    .xgr4( xgr4 ),
292
    .xgr5( xgr5 ),
293
    .xgr6( xgr6 ),
294
    .xgr7( xgr7 ),
295 30 rehayes
    .xgif_status( xgif_status ),
296 12 rehayes
    .debug_active( debug_active ),
297 53 rehayes
    .debug_ack( debug_ack ),
298 12 rehayes
    .xg_sw_irq( xg_sw_irq ),
299 34 rehayes
    .mem_access( mem_access ),
300 53 rehayes
    .single_step( single_step ),
301 2 rehayes
 
302
    // inputs
303
    .risc_clk( risc_clk ),
304
    .perif_data( wbs_dat_i ),
305
    .async_rst_b( async_rst_b ),
306
    .read_mem_data( read_mem_data ),
307 5 rehayes
    .mem_req_ack( mem_req_ack ),
308 53 rehayes
    .ss_mem_ack( ss_mem_ack ),
309 2 rehayes
    .xge( xge ),
310 15 rehayes
    .xgdbg_set( xgdbg_set ),
311
    .xgdbg_clear( xgdbg_clear ),
312 30 rehayes
    .debug_mode_i(debug_mode_i),
313 2 rehayes
    .xgss( xgss ),
314
    .xgvbr( xgvbr ),
315 5 rehayes
    .int_req( int_req ),
316 12 rehayes
    .xgie( xgie ),
317
    .brk_irq_ena( brk_irq_ena ),
318 2 rehayes
    .write_xgsem( write_xgsem ),
319 17 rehayes
    .write_xgchid( write_xgchid ),
320 2 rehayes
    .write_xgccr( write_xgccr ),
321
    .write_xgpc( write_xgpc ),
322
    .write_xgr7( write_xgr7 ),
323
    .write_xgr6( write_xgr6 ),
324
    .write_xgr5( write_xgr5 ),
325
    .write_xgr4( write_xgr4 ),
326
    .write_xgr3( write_xgr3 ),
327
    .write_xgr2( write_xgr2 ),
328
    .write_xgr1( write_xgr1 ),
329
    .clear_xgif_7( clear_xgif_7 ),
330
    .clear_xgif_6( clear_xgif_6 ),
331
    .clear_xgif_5( clear_xgif_5 ),
332
    .clear_xgif_4( clear_xgif_4 ),
333
    .clear_xgif_3( clear_xgif_3 ),
334
    .clear_xgif_2( clear_xgif_2 ),
335
    .clear_xgif_1( clear_xgif_1 ),
336
    .clear_xgif_0( clear_xgif_0 ),
337 12 rehayes
    .xgsweif_c( xgsweif_c ),
338 2 rehayes
    .clear_xgif_data( clear_xgif_data )
339
  );
340
 
341
  xgate_irq_encode #(.MAX_CHANNEL(MAX_CHANNEL))
342
    irq_encode(
343
    // outputs
344
    .int_req( int_req ),
345
    // inputs
346
    .chan_req_i( chan_req_i )
347
  );
348
 
349 5 rehayes
  // ---------------------------------------------------------------------------
350
  // Wishbone Master Bus interface
351
  xgate_wbm_bus #(.ARST_LVL(ARST_LVL))
352
    wishbone_m(
353
  // Wishbone Master Signals
354
    .wbm_dat_o( wbm_dat_o ),
355
    .wbm_we_o( wbm_we_o ),
356
    .wbm_stb_o( wbm_stb_o ),
357
    .wbm_cyc_o( wbm_cyc_o ),
358
    .wbm_sel_o( wbm_sel_o ),
359
    .wbm_adr_o( wbm_adr_o ),
360
    .wbm_dat_i( wbm_dat_i ),
361
    .wbm_ack_i( wbm_ack_i ),
362
    .wbs_clk_i( wbs_clk_i ),
363
    .wbs_rst_i( wbs_rst_i ),
364
    .arst_i( arst_i ),
365
 // XGATE Control Signals
366 53 rehayes
    .risc_clk( risc_clk ),
367
    .async_rst_b( async_rst_b ),
368 34 rehayes
    .xge( xge ),
369
    .mem_access( mem_access ),
370 53 rehayes
    .single_step( single_step ),
371
    .ss_mem_ack( ss_mem_ack ),
372 5 rehayes
    .read_mem_data( read_mem_data ),
373
    .xgate_address( xgate_address ),
374
    .mem_req_ack( mem_req_ack ),
375
    .write_mem_strb_l( write_mem_strb_l ),
376
    .write_mem_strb_h( write_mem_strb_h ),
377
    .write_mem_data( write_mem_data )
378
  );
379 2 rehayes
 
380 5 rehayes
 
381 2 rehayes
endmodule  // xgate_top
382
 

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