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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_top.v] - Blame information for rev 89

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1 2 rehayes
////////////////////////////////////////////////////////////////////////////////
2
//
3
//  XGATE Coprocessor - XGATE Top Level Module
4
//
5
//  Author: Robert Hayes
6
//          rehayes@opencores.org
7
//
8
//  Downloaded from: http://www.opencores.org/projects/xgate.....
9
//
10
////////////////////////////////////////////////////////////////////////////////
11
// Copyright (c) 2009, Robert Hayes
12
//
13
// This source file is free software: you can redistribute it and/or modify
14
// it under the terms of the GNU Lesser General Public License as published
15
// by the Free Software Foundation, either version 3 of the License, or
16
// (at your option) any later version.
17
//
18
// Supplemental terms.
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//     * Redistributions of source code must retain the above copyright
20
//       notice, this list of conditions and the following disclaimer.
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//     * Neither the name of the <organization> nor the
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//       names of its contributors may be used to endorse or promote products
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//       derived from this software without specific prior written permission.
24
//
25
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28
// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
29
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
31
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35
//
36
// You should have received a copy of the GNU General Public License
37
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
38
////////////////////////////////////////////////////////////////////////////////
39
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
40
 
41
module xgate_top #(parameter ARST_LVL = 1'b0,      // asynchronous reset level
42 89 rehayes
                   parameter DWIDTH   = 16,        // define the wishbone bus data size
43
                   parameter SINGLE_CYCLE = 1'b0,  //
44
                   parameter MAX_CHANNEL  = 127,   // Max XGATE Interrupt Channel Number
45
                   parameter WB_RD_DEFAULT = 0)    // WISHBONE Read Bus default state
46 2 rehayes
  (
47 5 rehayes
  // Wishbone Slave Signals
48
  output    [DWIDTH-1:0] wbs_dat_o,     // databus output
49
  output                 wbs_ack_o,     // bus cycle acknowledge output
50 53 rehayes
  output                 wbs_err_o,     // bus error, lost module select durning wait state
51 5 rehayes
  input                  wbs_clk_i,     // master clock input
52
  input                  wbs_rst_i,     // synchronous active high reset
53
  input                  arst_i,        // asynchronous reset
54 67 rehayes
  input            [6:1] wbs_adr_i,     // lower address bits
55 5 rehayes
  input     [DWIDTH-1:0] wbs_dat_i,     // databus input
56
  input                  wbs_we_i,      // write enable input
57
  input                  wbs_stb_i,     // stobe/core select signal
58
  input                  wbs_cyc_i,     // valid bus cycle input
59
  input            [1:0] wbs_sel_i,     // Select byte in word bus transaction
60
  // Wishbone Master Signals
61
  output    [DWIDTH-1:0] wbm_dat_o,     // databus output
62
  output                 wbm_we_o,      // write enable output
63
  output                 wbm_stb_o,     // stobe/core select signal
64
  output                 wbm_cyc_o,     // valid bus cycle output
65
  output          [ 1:0] wbm_sel_o,     // Select byte in word bus transaction
66
  output          [15:0] wbm_adr_o,     // Address bits
67
  input     [DWIDTH-1:0] wbm_dat_i,     // databus input
68
  input                  wbm_ack_i,     // bus cycle acknowledge input
69 2 rehayes
  // XGATE IO Signals
70 5 rehayes
  output          [ 7:0] xgswt,         // XGATE Software Trigger Register
71 12 rehayes
  output                 xg_sw_irq,        // Xgate Software interrupt
72 72 rehayes
  output [MAX_CHANNEL:1] xgif,             // XGATE Interrupt Flag to Host
73
  input  [MAX_CHANNEL:1] chan_req_i,       // XGATE Interrupt request
74 2 rehayes
  input                  risc_clk,         // Clock for RISC core
75 30 rehayes
  input                  debug_mode_i,     // Force RISC core into debug mode
76
  input                  secure_mode_i,    // Limit host asscess to Xgate RISC registers
77 2 rehayes
  input                  scantestmode      // Chip in in scan test mode
78
  );
79
 
80 67 rehayes
 
81 2 rehayes
  wire        zero_flag;
82
  wire        negative_flag;
83
  wire        carry_flag;
84
  wire        overflow_flag;
85
  wire [15:0] xgr1;          // XGATE Register #1
86
  wire [15:0] xgr2;          // XGATE Register #2
87
  wire [15:0] xgr3;          // XGATE Register #3
88
  wire [15:0] xgr4;          // XGATE Register #4
89
  wire [15:0] xgr5;          // XGATE Register #5
90
  wire [15:0] xgr6;          // XGATE Register #6
91
  wire [15:0] xgr7;          // XGATE Register #7
92
 
93
  wire        write_xgmctl;  // Write Strobe for XGMCTL register
94 17 rehayes
  wire        write_xgchid;  // Write Strobe for XGCHID register
95 41 rehayes
  wire  [1:0] write_xgvbr;   // Write Strobe for XGVBR register
96
  wire  [1:0] write_xgif_7;  // Write Strobe for Interrupt Flag Register 7
97
  wire  [1:0] write_xgif_6;  // Write Strobe for Interrupt Flag Register 6
98
  wire  [1:0] write_xgif_5;  // Write Strobe for Interrupt Flag Register 5
99
  wire  [1:0] write_xgif_4;  // Write Strobe for Interrupt Flag Register 4
100
  wire  [1:0] write_xgif_3;  // Write Strobe for Interrupt Flag Register 3
101
  wire  [1:0] write_xgif_2;  // Write Strobe for Interrupt Flag Register 2
102
  wire  [1:0] write_xgif_1;  // Write Strobe for Interrupt Flag Register 1
103
  wire  [1:0] write_xgif_0;  // Write Strobe for Interrupt Flag Register 0
104 67 rehayes
  wire  [1:0] write_irw_en_7; // Write Strobe for Interrupt Bypass Control Register 7
105
  wire  [1:0] write_irw_en_6; // Write Strobe for Interrupt Bypass Control Register 6
106
  wire  [1:0] write_irw_en_5; // Write Strobe for Interrupt Bypass Control Register 5
107
  wire  [1:0] write_irw_en_4; // Write Strobe for Interrupt Bypass Control Register 4
108
  wire  [1:0] write_irw_en_3; // Write Strobe for Interrupt Bypass Control Register 3
109
  wire  [1:0] write_irw_en_2; // Write Strobe for Interrupt Bypass Control Register 2
110
  wire  [1:0] write_irw_en_1; // Write Strobe for Interrupt Bypass Control Register 1
111
  wire  [1:0] write_irw_en_0; // Write Strobe for Interrupt Bypass Control Register 0
112 2 rehayes
  wire        write_xgswt;   // Write Strobe for XGSWT register
113
  wire        write_xgsem;   // Write Strobe for XGSEM register
114
  wire        write_xgccr;   // Write Strobe for XGATE Condition Code Register
115 41 rehayes
  wire  [1:0] write_xgpc;    // Write Strobe for XGATE Program Counter
116
  wire  [1:0] write_xgr7;    // Write Strobe for XGATE Data Register R7
117
  wire  [1:0] write_xgr6;    // Write Strobe for XGATE Data Register R6
118
  wire  [1:0] write_xgr5;    // Write Strobe for XGATE Data Register R5
119
  wire  [1:0] write_xgr4;    // Write Strobe for XGATE Data Register R4
120
  wire  [1:0] write_xgr3;    // Write Strobe for XGATE Data Register R3
121
  wire  [1:0] write_xgr2;    // Write Strobe for XGATE Data Register R2
122
  wire  [1:0] write_xgr1;    // Write Strobe for XGATE Data Register R1
123 2 rehayes
 
124
  wire        clear_xgif_7;    // Strobe for decode to clear interrupt flag bank 7
125
  wire        clear_xgif_6;    // Strobe for decode to clear interrupt flag bank 6
126
  wire        clear_xgif_5;    // Strobe for decode to clear interrupt flag bank 5
127
  wire        clear_xgif_4;    // Strobe for decode to clear interrupt flag bank 4
128
  wire        clear_xgif_3;    // Strobe for decode to clear interrupt flag bank 3
129
  wire        clear_xgif_2;    // Strobe for decode to clear interrupt flag bank 2
130
  wire        clear_xgif_1;    // Strobe for decode to clear interrupt flag bank 1
131
  wire        clear_xgif_0;    // Strobe for decode to clear interrupt flag bank 0
132
  wire [15:0] clear_xgif_data; // Data for decode to clear interrupt flag
133 72 rehayes
  wire [MAX_CHANNEL:1] chan_bypass; // XGATE Interrupt enable or bypass
134 2 rehayes
 
135
  wire        xge;           // XGATE Module Enable
136
  wire        xgfrz;         // Stop XGATE in Freeze Mode
137 15 rehayes
  wire        xgdbg_set;     // Enter XGATE Debug Mode
138
  wire        xgdbg_clear;   // Leave XGATE Debug Mode
139 41 rehayes
  wire        xgfact;        // Fake Activity
140 2 rehayes
  wire        xgss;          // XGATE Single Step
141
  wire        xgsweif_c;     // Clear XGATE Software Error Interrupt FLag
142
  wire        xgie;          // XGATE Interrupt Enable
143
  wire [ 6:0] int_req;       // Encoded interrupt request
144
  wire [ 6:0] xgchid;        // Channel actively being processed
145 72 rehayes
  wire [127:1] xgif_status;  // Status bits of interrupt output flags that have been set
146
  wire [127:1] irq_bypass;   // IRQ status bits WISHBONE Read bus
147 67 rehayes
 
148 2 rehayes
  wire [15:1] xgvbr;         // XGATE vector Base Address Register
149 12 rehayes
  wire        brk_irq_ena;   // Enable BRK instruction to generate interrupt
150 89 rehayes
 
151 5 rehayes
  wire [15:0] xgate_address;   //
152
  wire [15:0] write_mem_data;  //
153
  wire [15:0] read_mem_data;   //
154 34 rehayes
  wire        mem_access;      //
155 5 rehayes
  wire        mem_req_ack;     //
156 12 rehayes
 
157 89 rehayes
  wire        debug_active;    // RISC state machine in Debug mode
158 53 rehayes
  wire        debug_ack;       // Clear debug register
159
  wire        single_step;     // Pulse to trigger a single instruction execution in debug mode
160
  wire        ss_mem_ack;      // WISHBONE Bus has granted single step memory access
161 89 rehayes
 
162 63 rehayes
  wire [ 7:0] host_semap;       // Semaphore status for host
163
  wire        write_mem_strb_l; // Strobe for writing low data byte
164
  wire        write_mem_strb_h; // Strobe for writing high data bye
165 89 rehayes
 
166 2 rehayes
  // ---------------------------------------------------------------------------
167
  // Wishbone Slave Bus interface
168
  xgate_wbs_bus #(.ARST_LVL(ARST_LVL),
169 67 rehayes
                  .SINGLE_CYCLE(SINGLE_CYCLE),
170 89 rehayes
                  .WB_RD_DEFAULT(WB_RD_DEFAULT))
171 2 rehayes
    wishbone_s(
172
    .wbs_dat_o( wbs_dat_o ),
173
    .wbs_ack_o( wbs_ack_o ),
174 53 rehayes
    .wbs_err_o( wbs_err_o ),
175 2 rehayes
    .wbs_clk_i( wbs_clk_i ),
176
    .wbs_rst_i( wbs_rst_i ),
177
    .arst_i( arst_i ),
178
    .wbs_adr_i( wbs_adr_i ),
179
    .wbs_dat_i( wbs_dat_i ),
180
    .wbs_we_i( wbs_we_i ),
181
    .wbs_stb_i( wbs_stb_i ),
182
    .wbs_cyc_i( wbs_cyc_i ),
183
    .wbs_sel_i( wbs_sel_i ),
184 89 rehayes
 
185 2 rehayes
    // outputs
186
    .sync_reset( sync_reset ),
187
    .write_xgmctl( write_xgmctl ),
188 17 rehayes
    .write_xgchid( write_xgchid ),
189 2 rehayes
    .write_xgvbr( write_xgvbr ),
190
    .write_xgif_7( write_xgif_7 ),
191
    .write_xgif_6( write_xgif_6 ),
192
    .write_xgif_5( write_xgif_5 ),
193
    .write_xgif_4( write_xgif_4 ),
194
    .write_xgif_3( write_xgif_3 ),
195
    .write_xgif_2( write_xgif_2 ),
196
    .write_xgif_1( write_xgif_1 ),
197
    .write_xgif_0( write_xgif_0 ),
198
    .write_xgswt( write_xgswt ),
199
    .write_xgsem( write_xgsem ),
200
    .write_xgccr( write_xgccr ),
201
    .write_xgpc( write_xgpc ),
202
    .write_xgr7( write_xgr7 ),
203
    .write_xgr6( write_xgr6 ),
204
    .write_xgr5( write_xgr5 ),
205
    .write_xgr4( write_xgr4 ),
206
    .write_xgr3( write_xgr3 ),
207
    .write_xgr2( write_xgr2 ),
208
    .write_xgr1( write_xgr1 ),
209 67 rehayes
    .write_irw_en_7( write_irw_en_7 ),
210
    .write_irw_en_6( write_irw_en_6 ),
211
    .write_irw_en_5( write_irw_en_5 ),
212
    .write_irw_en_4( write_irw_en_4 ),
213
    .write_irw_en_3( write_irw_en_3 ),
214
    .write_irw_en_2( write_irw_en_2 ),
215
    .write_irw_en_1( write_irw_en_1 ),
216
    .write_irw_en_0( write_irw_en_0 ),
217 89 rehayes
    // inputs
218 67 rehayes
    .async_rst_b( async_rst_b ),
219
    .read_risc_regs(               // in  -- read register bits
220 89 rehayes
       { xgr7,             // XGR7
221
         xgr6,             // XGR6
222
         xgr5,             // XGR5
223
         xgr4,             // XGR4
224
         xgr3,             // XGR3
225
         xgr2,             // XGR2
226
         xgr1,             // XGR1
227
         16'b0,            // Reserved (XGR0)
228
         xgate_address,    // XGPC
229
         {12'h000,  negative_flag, zero_flag, overflow_flag, carry_flag},  // XGCCR
230
         16'b0,                // Reserved
231
         {8'h00, host_semap},  // XGSEM
232
         {8'h00, xgswt},       // XGSWT
233
         {xgif_status[ 15:  1], 1'b0}, // XGIF_0
234
         xgif_status[ 31: 16], // XGIF_1
235
         xgif_status[ 47: 32], // XGIF_2
236
         xgif_status[ 63: 48], // XGIF_3
237
         xgif_status[ 79: 64], // XGIF_4
238
         xgif_status[ 95: 80], // XGIF_5
239
         xgif_status[111: 96], // XGIF_6
240
         xgif_status[127:112], // XGIF_7
241
         {xgvbr[15:1], 1'b0},  // XGVBR
242
         16'b0,                // Reserved
243
         16'b0,                // Reserved
244
         {8'b0, 1'b0, xgchid}, // XGCHID
245
         {8'b0, xge, xgfrz, debug_active, 1'b0, xgfact, brk_irq_ena, xg_sw_irq, xgie}  // XGMCTL
246
       }
247
      ),
248 67 rehayes
    .irq_bypass( irq_bypass )
249
 
250 2 rehayes
  );
251
 
252
  // ---------------------------------------------------------------------------
253
  xgate_regs #(.ARST_LVL(ARST_LVL),
254
               .MAX_CHANNEL(MAX_CHANNEL))
255
    regs(
256
    // outputs
257
    .xge( xge ),
258
    .xgfrz( xgfrz ),
259 15 rehayes
    .xgdbg_set( xgdbg_set ),
260
    .xgdbg_clear( xgdbg_clear ),
261 41 rehayes
    .xgfact( xgfact ),
262 2 rehayes
    .xgss( xgss ),
263
    .xgsweif_c( xgsweif_c ),
264
    .xgie( xgie ),
265 12 rehayes
    .brk_irq_ena( brk_irq_ena ),
266 2 rehayes
    .xgvbr( xgvbr ),
267
    .xgswt( xgswt ),
268
    .clear_xgif_7( clear_xgif_7 ),
269
    .clear_xgif_6( clear_xgif_6 ),
270
    .clear_xgif_5( clear_xgif_5 ),
271
    .clear_xgif_4( clear_xgif_4 ),
272
    .clear_xgif_3( clear_xgif_3 ),
273
    .clear_xgif_2( clear_xgif_2 ),
274
    .clear_xgif_1( clear_xgif_1 ),
275
    .clear_xgif_0( clear_xgif_0 ),
276
    .clear_xgif_data( clear_xgif_data ),
277 67 rehayes
    .irq_bypass( irq_bypass ),
278
    .chan_bypass( chan_bypass ),
279 2 rehayes
 
280
    // inputs
281
    .async_rst_b( async_rst_b ),
282
    .sync_reset( sync_reset ),
283
    .bus_clk( wbs_clk_i ),
284
    .write_bus( wbs_dat_i ),
285
    .write_xgmctl( write_xgmctl ),
286
    .write_xgvbr( write_xgvbr ),
287
    .write_xgif_7( write_xgif_7 ),
288
    .write_xgif_6( write_xgif_6 ),
289
    .write_xgif_5( write_xgif_5 ),
290
    .write_xgif_4( write_xgif_4 ),
291
    .write_xgif_3( write_xgif_3 ),
292
    .write_xgif_2( write_xgif_2 ),
293
    .write_xgif_1( write_xgif_1 ),
294
    .write_xgif_0( write_xgif_0 ),
295 67 rehayes
    .write_irw_en_7( write_irw_en_7 ),
296
    .write_irw_en_6( write_irw_en_6 ),
297
    .write_irw_en_5( write_irw_en_5 ),
298
    .write_irw_en_4( write_irw_en_4 ),
299
    .write_irw_en_3( write_irw_en_3 ),
300
    .write_irw_en_2( write_irw_en_2 ),
301
    .write_irw_en_1( write_irw_en_1 ),
302
    .write_irw_en_0( write_irw_en_0 ),
303 53 rehayes
    .write_xgswt( write_xgswt ),
304
    .debug_ack( debug_ack )
305 2 rehayes
  );
306
 
307
  // ---------------------------------------------------------------------------
308
  xgate_risc #(.MAX_CHANNEL(MAX_CHANNEL))
309
    risc(
310
    // outputs
311
    .xgate_address( xgate_address ),
312
    .write_mem_strb_l( write_mem_strb_l ),
313
    .write_mem_strb_h( write_mem_strb_h ),
314
    .write_mem_data( write_mem_data ),
315
    .zero_flag( zero_flag ),
316
    .negative_flag( negative_flag ),
317
    .carry_flag( carry_flag ),
318
    .overflow_flag( overflow_flag ),
319
    .xgchid( xgchid ),
320
    .host_semap( host_semap ),
321
    .xgr1( xgr1 ),
322
    .xgr2( xgr2 ),
323
    .xgr3( xgr3 ),
324
    .xgr4( xgr4 ),
325
    .xgr5( xgr5 ),
326
    .xgr6( xgr6 ),
327
    .xgr7( xgr7 ),
328 30 rehayes
    .xgif_status( xgif_status ),
329 12 rehayes
    .debug_active( debug_active ),
330 53 rehayes
    .debug_ack( debug_ack ),
331 12 rehayes
    .xg_sw_irq( xg_sw_irq ),
332 34 rehayes
    .mem_access( mem_access ),
333 53 rehayes
    .single_step( single_step ),
334 89 rehayes
 
335 2 rehayes
    // inputs
336
    .risc_clk( risc_clk ),
337
    .perif_data( wbs_dat_i ),
338
    .async_rst_b( async_rst_b ),
339
    .read_mem_data( read_mem_data ),
340 5 rehayes
    .mem_req_ack( mem_req_ack ),
341 53 rehayes
    .ss_mem_ack( ss_mem_ack ),
342 2 rehayes
    .xge( xge ),
343 15 rehayes
    .xgdbg_set( xgdbg_set ),
344
    .xgdbg_clear( xgdbg_clear ),
345 30 rehayes
    .debug_mode_i(debug_mode_i),
346 2 rehayes
    .xgss( xgss ),
347
    .xgvbr( xgvbr ),
348 5 rehayes
    .int_req( int_req ),
349 12 rehayes
    .xgie( xgie ),
350
    .brk_irq_ena( brk_irq_ena ),
351 2 rehayes
    .write_xgsem( write_xgsem ),
352 17 rehayes
    .write_xgchid( write_xgchid ),
353 2 rehayes
    .write_xgccr( write_xgccr ),
354
    .write_xgpc( write_xgpc ),
355
    .write_xgr7( write_xgr7 ),
356
    .write_xgr6( write_xgr6 ),
357
    .write_xgr5( write_xgr5 ),
358
    .write_xgr4( write_xgr4 ),
359
    .write_xgr3( write_xgr3 ),
360
    .write_xgr2( write_xgr2 ),
361
    .write_xgr1( write_xgr1 ),
362
    .clear_xgif_7( clear_xgif_7 ),
363
    .clear_xgif_6( clear_xgif_6 ),
364
    .clear_xgif_5( clear_xgif_5 ),
365
    .clear_xgif_4( clear_xgif_4 ),
366
    .clear_xgif_3( clear_xgif_3 ),
367
    .clear_xgif_2( clear_xgif_2 ),
368
    .clear_xgif_1( clear_xgif_1 ),
369
    .clear_xgif_0( clear_xgif_0 ),
370 12 rehayes
    .xgsweif_c( xgsweif_c ),
371 2 rehayes
    .clear_xgif_data( clear_xgif_data )
372
  );
373
 
374 89 rehayes
  xgate_irq_encode #(.MAX_CHANNEL(MAX_CHANNEL))
375 2 rehayes
    irq_encode(
376
    // outputs
377 67 rehayes
    .xgif( xgif ),
378 2 rehayes
    .int_req( int_req ),
379
    // inputs
380 67 rehayes
    .chan_req_i( chan_req_i ),
381
    .chan_bypass( chan_bypass ),
382
    .xgif_status( xgif_status )
383 2 rehayes
  );
384
 
385 5 rehayes
  // ---------------------------------------------------------------------------
386
  // Wishbone Master Bus interface
387
  xgate_wbm_bus #(.ARST_LVL(ARST_LVL))
388
    wishbone_m(
389
  // Wishbone Master Signals
390
    .wbm_dat_o( wbm_dat_o ),
391
    .wbm_we_o( wbm_we_o ),
392
    .wbm_stb_o( wbm_stb_o ),
393
    .wbm_cyc_o( wbm_cyc_o ),
394
    .wbm_sel_o( wbm_sel_o ),
395
    .wbm_adr_o( wbm_adr_o ),
396
    .wbm_dat_i( wbm_dat_i ),
397
    .wbm_ack_i( wbm_ack_i ),
398
    .wbs_clk_i( wbs_clk_i ),
399
    .wbs_rst_i( wbs_rst_i ),
400
    .arst_i( arst_i ),
401
 // XGATE Control Signals
402 53 rehayes
    .risc_clk( risc_clk ),
403
    .async_rst_b( async_rst_b ),
404 34 rehayes
    .xge( xge ),
405
    .mem_access( mem_access ),
406 53 rehayes
    .single_step( single_step ),
407
    .ss_mem_ack( ss_mem_ack ),
408 5 rehayes
    .read_mem_data( read_mem_data ),
409
    .xgate_address( xgate_address ),
410
    .mem_req_ack( mem_req_ack ),
411
    .write_mem_strb_l( write_mem_strb_l ),
412
    .write_mem_strb_h( write_mem_strb_h ),
413
    .write_mem_data( write_mem_data )
414
  );
415 2 rehayes
 
416 5 rehayes
 
417 2 rehayes
endmodule  // xgate_top
418
 

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