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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_wbs_bus.v] - Blame information for rev 2

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1 2 rehayes
////////////////////////////////////////////////////////////////////////////////
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//
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//  WISHBONE revB.2 compliant Xgate Coprocessor - Slave Bus interface
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//
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//  Author: Bob Hayes
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//          rehayes@opencores.org
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//
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//  Downloaded from: http://www.opencores.org/projects/xgate.....
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//
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2009, Robert Hayes
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// Supplemental terms.
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//     * Redistributions of source code must retain the above copyright
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//       notice, this list of conditions and the following disclaimer.
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//     * Neither the name of the <organization> nor the
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//       names of its contributors may be used to endorse or promote products
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//       derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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module xgate_wbs_bus #(parameter ARST_LVL = 1'b0,    // asynchronous reset level
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                       parameter DWIDTH = 16,
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                       parameter SINGLE_CYCLE = 1'b0)
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  (
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  // Wishbone Signals
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  output      [DWIDTH-1:0] wbs_dat_o,     // databus output
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  output                   wbs_ack_o,     // bus cycle acknowledge output
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  input                    wbs_clk_i,     // master clock input
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  input                    wbs_rst_i,     // synchronous active high reset
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  input                    arst_i,        // asynchronous reset
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  input             [ 4:0] wbs_adr_i,     // lower address bits
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  input       [DWIDTH-1:0] wbs_dat_i,     // databus input
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  input                    wbs_we_i,      // write enable input
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  input                    wbs_stb_i,     // stobe/core select signal
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  input                    wbs_cyc_i,     // valid bus cycle input
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  input              [1:0] wbs_sel_i,     // Select byte in word bus transaction
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  // COP Control Signals
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  output reg               write_xgmctl, // Write Strobe for XGMCTL register
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  output reg               write_xgisp74,// Write Strobe for XGISP74 register
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  output reg               write_xgisp30,// Write Strobe for XGISP30 register
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  output reg               write_xgvbr,  // Write Strobe for XGVBR register
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  output reg               write_xgif_7, // Write Strobe for Interrupt Flag Register 7
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  output reg               write_xgif_6, // Write Strobe for Interrupt Flag Register 6
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  output reg               write_xgif_5, // Write Strobe for Interrupt Flag Register 5
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  output reg               write_xgif_4, // Write Strobe for Interrupt Flag Register 4
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  output reg               write_xgif_3, // Write Strobe for Interrupt Flag Register 3
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  output reg               write_xgif_2, // Write Strobe for Interrupt Flag Register 2
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  output reg               write_xgif_1, // Write Strobe for Interrupt Flag Register 1
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  output reg               write_xgif_0, // Write Strobe for Interrupt Flag Register 0
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  output reg               write_xgswt,  // Write Strobe for XGSWT register
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  output reg               write_xgsem,  // Write Strobe for XGSEM register
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  output reg               write_xgccr,  // Write Strobe for XGATE Condition Code Register
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  output reg               write_xgpc,   // Write Strobe for XGATE Program Counter
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  output reg               write_xgr7,   // Write Strobe for XGATE Data Register R7
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  output reg               write_xgr6,   // Write Strobe for XGATE Data Register R6
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  output reg               write_xgr5,   // Write Strobe for XGATE Data Register R5
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  output reg               write_xgr4,   // Write Strobe for XGATE Data Register R4
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  output reg               write_xgr3,   // Write Strobe for XGATE Data Register R3
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  output reg               write_xgr2,   // Write Strobe for XGATE Data Register R2
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  output reg               write_xgr1,   // Write Strobe for XGATE Data Register R1
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  output                   async_rst_b,  //
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  output                   sync_reset,   //
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  input            [415:0] read_regs     // status register bits
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  );
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  // registers
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  reg                bus_wait_state;  // Holdoff wbs_ack_o for one clock to add wait state
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  reg  [DWIDTH-1:0]  rd_data_mux;     // Pseudo Register, WISHBONE Read Data Mux
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  reg  [DWIDTH-1:0]  rd_data_reg;     // Latch for WISHBONE Read Data
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  reg                write_reserv;    // Dummy Reg decode for Reserved address
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  // Wires
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  wire   module_sel;       // This module is selected for bus transaction
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  wire   wbs_wacc;         // WISHBONE Write Strobe (Clock gating signal)
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  wire   wbs_racc;         // WISHBONE Read Access (Clock gating signal)
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  //
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  // module body
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  //
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  // generate internal resets
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  assign async_rst_b = arst_i ^ ARST_LVL;
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  assign sync_reset  = wbs_rst_i;
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  // generate wishbone signals
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  assign module_sel  = wbs_cyc_i && wbs_stb_i;
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  assign wbs_wacc    = module_sel && wbs_we_i && (wbs_ack_o || SINGLE_CYCLE);
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  assign wbs_racc    = module_sel && !wbs_we_i;
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  assign wbs_ack_o   = SINGLE_CYCLE ? module_sel : bus_wait_state;
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  assign wbs_dat_o   = SINGLE_CYCLE ? rd_data_mux : rd_data_reg;
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  // generate acknowledge output signal, By using register all accesses takes two cycles.
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  //  Accesses in back to back clock cycles are not possable.
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  always @(posedge wbs_clk_i or negedge async_rst_b)
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    if (!async_rst_b)
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      bus_wait_state <=  1'b0;
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    else if (sync_reset)
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      bus_wait_state <=  1'b0;
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    else
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      bus_wait_state <=  module_sel && !bus_wait_state;
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  // assign data read bus -- DAT_O
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  always @(posedge wbs_clk_i)
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    if ( wbs_racc )                     // Clock gate for power saving
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      rd_data_reg <= rd_data_mux;
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  // WISHBONE Read Data Mux
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  always @*
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      case (wbs_adr_i) // synopsys parallel_case
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        // 16 bit Bus, 16 bit Granularity
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        5'b0_0000: rd_data_mux = read_regs[ 15:  0];
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        5'b0_0001: rd_data_mux = read_regs[ 31: 16];
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        5'b0_0010: rd_data_mux = read_regs[ 47: 32];
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        5'b0_0011: rd_data_mux = read_regs[ 63: 48];
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        5'b0_0100: rd_data_mux = read_regs[ 79: 64];
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        5'b0_0101: rd_data_mux = read_regs[ 95: 80];
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        5'b0_0110: rd_data_mux = read_regs[111: 96];
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        5'b0_0111: rd_data_mux = read_regs[127:112];
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        5'b0_1000: rd_data_mux = read_regs[143:128];
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        5'b0_1001: rd_data_mux = read_regs[159:144];
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        5'b0_1010: rd_data_mux = read_regs[175:160];
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        5'b0_1011: rd_data_mux = read_regs[191:176];
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        5'b0_1100: rd_data_mux = read_regs[207:192];
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        5'b0_1101: rd_data_mux = read_regs[223:208];
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        5'b0_1110: rd_data_mux = read_regs[239:224];
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        5'b0_1111: rd_data_mux = read_regs[255:240];
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        5'b1_0000: rd_data_mux = read_regs[271:256];
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        5'b1_0001: rd_data_mux = read_regs[287:272];
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        5'b1_0010: rd_data_mux = read_regs[303:288];
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        5'b1_0011: rd_data_mux = read_regs[319:304];
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        5'b1_0100: rd_data_mux = read_regs[335:320];
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        5'b1_0101: rd_data_mux = read_regs[351:336];
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        5'b1_0110: rd_data_mux = read_regs[367:352];
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        5'b1_0111: rd_data_mux = read_regs[383:368];
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        5'b1_1000: rd_data_mux = read_regs[399:384];
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        5'b1_1001: rd_data_mux = read_regs[415:400];
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        default: rd_data_mux = 16'h0000;
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      endcase
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  // generate wishbone write register strobes
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  always @*
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    begin
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      write_reserv = 1'b0;
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      write_xgmctl = 1'b0;
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      write_xgisp74 = 1'b0;
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      write_xgisp30 = 1'b0;
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      write_xgvbr  = 1'b0;
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      write_xgif_7 = 1'b0;
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      write_xgif_6 = 1'b0;
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      write_xgif_5 = 1'b0;
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      write_xgif_4 = 1'b0;
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      write_xgif_3 = 1'b0;
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      write_xgif_2 = 1'b0;
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      write_xgif_1 = 1'b0;
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      write_xgif_0 = 1'b0;
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      write_xgif_7 = 1'b0;
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      write_xgswt  = 1'b0;
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      write_xgsem  = 1'b0;
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      write_xgccr  = 1'b0;
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      write_xgpc   = 1'b0;
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      write_xgr7   = 1'b0;
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      write_xgr6   = 1'b0;
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      write_xgr5   = 1'b0;
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      write_xgr4   = 1'b0;
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      write_xgr3   = 1'b0;
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      write_xgr2   = 1'b0;
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      write_xgr1   = 1'b0;
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      if (wbs_wacc)
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        case (wbs_adr_i) // synopsys parallel_case
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           // 16 bit Bus, 16 bit Granularity
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           5'b0_0000 : write_xgmctl  = 1'b1;
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//         5'b0_0001 : write_xgchid  = 1'b1;
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           5'b0_0010 : write_xgisp74 = 1'b1;
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           5'b0_0011 : write_xgisp30 = 1'b1;
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           5'b0_0100 : write_xgvbr   = 1'b1;
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           5'b0_0101 : write_xgif_7  = 1'b1;
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           5'b0_0110 : write_xgif_6  = 1'b1;
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           5'b0_0111 : write_xgif_5  = 1'b1;
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           5'b0_1000 : write_xgif_4  = 1'b1;
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           5'b0_1001 : write_xgif_3  = 1'b1;
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           5'b0_1010 : write_xgif_2  = 1'b1;
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           5'b0_1011 : write_xgif_1  = 1'b1;
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           5'b0_1100 : write_xgif_0  = 1'b1;
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           5'b0_1101 : write_xgswt   = 1'b1;
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           5'b0_1110 : write_xgsem   = 1'b1;
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           5'b0_1111 : write_reserv  = 1'b1;
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           5'b1_0000 : write_xgccr   = 1'b1;
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           5'b1_0001 : write_xgpc    = 1'b1;
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           5'b1_0010 : write_reserv  = 1'b1;
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           5'b1_0011 : write_xgr1    = 1'b1;
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           5'b1_0100 : write_xgr2    = 1'b1;
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           5'b1_0101 : write_xgr3    = 1'b1;
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           5'b1_0110 : write_xgr4    = 1'b1;
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           5'b1_0111 : write_xgr5    = 1'b1;
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           5'b1_1000 : write_xgr6    = 1'b1;
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           5'b1_1001 : write_xgr7    = 1'b1;
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           default: ;
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        endcase
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    end
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endmodule  // xgate_wbs_bus

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