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[/] [xgate/] [trunk/] [sim/] [verilog/] [run/] [run_iverilog] - Blame information for rev 2

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Line No. Rev Author Line
1 2 rehayes
#!/bin/csh
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set xgate    = ../../..
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set bench    = $xgate/bench
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set wave_dir = $xgate/sim/rtl_sim/xgate_verilog/waves
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iverilog                                \
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                                        \
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        -I $bench/verilog               \
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        -I $xgate/rtl/verilog           \
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                        \
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        -o xgate_compiled \
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        -D WAVES_V      \
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                                        \
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        $xgate/rtl/verilog/xgate_top.v  \
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        $xgate/rtl/verilog/xgate_wbs_bus.v      \
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        $xgate/rtl/verilog/xgate_regs.v \
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        $xgate/rtl/verilog/xgate_risc.v \
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        $xgate/rtl/verilog/xgate_irq_encode.v   \
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                                        \
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        $bench/verilog/wb_master_model.v        \
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        $bench/verilog/tst_bench_top.v
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@ good_compile = $status
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if ($good_compile == 0) then
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  echo "Compile was Good"
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  vvp xgate_compiled -lxt2
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else
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  echo "Compile Failed"
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endif
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