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[/] [xgate/] [trunk/] [sw/] [tools/] [misc/] [instructions.rtf] - Blame information for rev 31

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1 16 rehayes 
{\rtf1\ansi\ansicpg1252\cocoartf949\cocoasubrtf460
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{\fonttbl\f0\fswiss\fcharset0 Helvetica;}
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{\colortbl;\red255\green255\blue255;}
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\margl1440\margr1440\vieww19660\viewh14040\viewkind0
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\deftab720
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\pard\pardeftab720\ql\qnatural
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\f0\b\fs24 \cf0 Return to Scheduler and Others\
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\pard\pardeftab720\ql\qnatural
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\b0 \cf0 BRK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\
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NOP 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0\
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RTS 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0\
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SIF 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0\
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\pard\pardeftab720\ql\qnatural
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\b \cf0 Semaphore Instructions\
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\pard\pardeftab720\ql\qnatural
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\b0 \cf0 CSEM IMM3 0 0 0 0 0 IMM3 1 1 1 1 0 0 0 0\
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CSEM RS 0 0 0 0 0 RS 1 1 1 1 0 0 0 1\
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SSEM IMM3 0 0 0 0 0 IMM3 1 1 1 1 0 0 1 0\
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SSEM RS 0 0 0 0 0 RS 1 1 1 1 0 0 1 1\
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\pard\pardeftab720\ql\qnatural
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\b \cf0 Single Register Instructions\
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\pard\pardeftab720\ql\qnatural
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\b0 \cf0 SEX RD 0 0 0 0 0 RD 1 1 1 1 0 1 0 0\
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PAR RD 0 0 0 0 0 RD 1 1 1 1 0 1 0 1\
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JAL RD 0 0 0 0 0 RD 1 1 1 1 0 1 1 0\
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SIF RS 0 0 0 0 0 RS 1 1 1 1 0 1 1 1\
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\pard\pardeftab720\ql\qnatural
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\b \cf0 Special Move instructions\
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\pard\pardeftab720\ql\qnatural
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\b0 \cf0 TFR RD,CCR 0 0 0 0 0 RD 1 1 1 1 1 0 0 0\
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TFR CCR,RS 0 0 0 0 0 RS 1 1 1 1 1 0 0 1\
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TFR RD,PC 0 0 0 0 0 RD 1 1 1 1 1 0 1 0\
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\pard\pardeftab720\ql\qnatural
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\b \cf0 Shift instructions Dyadic\
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\pard\pardeftab720\ql\qnatural
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\b0 \cf0 BFFO RD, RS 0 0 0 0 1 RD RS 1 0 0 0 0\
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ASR RD, RS 0 0 0 0 1 RD RS 1 0 0 0 1\
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CSL RD, RS 0 0 0 0 1 RD RS 1 0 0 1 0\
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CSR RD, RS 0 0 0 0 1 RD RS 1 0 0 1 1\
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LSL RD, RS 0 0 0 0 1 RD RS 1 0 1 0 0\
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LSR RD, RS 0 0 0 0 1 RD RS 1 0 1 0 1\
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ROL RD, RS 0 0 0 0 1 RD RS 1 0 1 1 0\
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ROR RD, RS 0 0 0 0 1 RD RS 1 0 1 1 1\
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\pard\pardeftab720\ql\qnatural
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\b \cf0 Shift instructions immediate\
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\pard\pardeftab720\ql\qnatural
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\b0 \cf0 ASR RD, #IMM4 0 0 0 0 1 RD IMM4 1 0 0 1\
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CSL RD, #IMM4 0 0 0 0 1 RD IMM4 1 0 1 0\
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CSR RD, #IMM4 0 0 0 0 1 RD IMM4 1 0 1 1\
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LSL RD, #IMM4 0 0 0 0 1 RD IMM4 1 1 0 0\
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LSR RD, #IMM4 0 0 0 0 1 RD IMM4 1 1 0 1\
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ROL RD, #IMM4 0 0 0 0 1 RD IMM4 1 1 1 0\
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ROR RD, #IMM4 0 0 0 0 1 RD IMM4 1 1 1 1\
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\pard\pardeftab720\ql\qnatural
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\b \cf0 Logical Triadic\
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\pard\pardeftab720\ql\qnatural
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\b0 \cf0 AND RD, RS1, RS2 0 0 0 1 0 RD RS1 RS2 0 0\
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OR RD, RS1, RS2 0 0 0 1 0 RD RS1 RS2 1 0\
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XNOR RD, RS1, RS2 0 0 0 1 0 RD RS1 RS2 1 1\
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\pard\pardeftab720\ql\qnatural
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\b \cf0 Arithmetic Triadic
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\b0 For compare use SUB R0,Rs1,Rs2\
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SUB RD, RS1, RS2 0 0 0 1 1 RD RS1 RS2 0 0\
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SBC RD, RS1, RS2 0 0 0 1 1 RD RS1 RS2 0 1\
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ADD RD, RS1, RS2 0 0 0 1 1 RD RS1 RS2 1 0\
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ADC RD, RS1, RS2 0 0 0 1 1 RD RS1 RS2 1 1\
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\b Branches\
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\pard\pardeftab720\ql\qnatural
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\b0 \cf0 BCC REL9 0 0 1 0 0 0 0 REL9\
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BCS REL9 0 0 1 0 0 0 1 REL9\
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BNE REL9 0 0 1 0 0 1 0 REL9\
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BEQ REL9 0 0 1 0 0 1 1 REL9\
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BPL REL9 0 0 1 0 1 0 0 REL9\
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BMI REL9 0 0 1 0 1 0 1 REL9\
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BVC REL9 0 0 1 0 1 1 0 REL9\
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BVS REL9 0 0 1 0 1 1 1 REL9\
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BHI REL9 0 0 1 1 0 0 0 REL9\
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BLS REL9 0 0 1 1 0 0 1 REL9\
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BGE REL9 0 0 1 1 0 1 0 REL9\
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BLT REL9 0 0 1 1 0 1 1 REL9\
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BGT REL9 0 0 1 1 1 0 0 REL9\
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BLE REL9 0 0 1 1 1 0 1 REL9\
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BRA REL10 0 0 1 1 1 1 REL10\
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\pard\pardeftab720\ql\qnatural
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\b \cf0 Load and Store Instructions\
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\pard\pardeftab720\ql\qnatural
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\b0 \cf0 LDB RD, (RB, #OFFS5) 0 1 0 0 0 RD RB OFFS5\
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LDW RD, (RB, #OFFS5) 0 1 0 0 1 RD RB OFFS5\
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STB RS, (RB, #OFFS5) 0 1 0 1 0 RS RB OFFS5\
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STW RS, (RB, #OFFS5) 0 1 0 1 1 RS RB OFFS5\
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LDB RD, (RB, RI) 0 1 1 0 0 RD RB RI 0 0\
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LDW RD, (RB, RI) 0 1 1 0 1 RD RB RI 0 0\
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STB RS, (RB, RI) 0 1 1 1 0 RS RB RI 0 0\
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STW RS, (RB, RI) 0 1 1 1 1 RS RB RI 0 0\
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LDB RD, (RB, RI+) 0 1 1 0 0 RD RB RI 0 1\
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LDW RD, (RB, RI+) 0 1 1 0 1 RD RB RI 0 1\
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STB RS, (RB, RI+) 0 1 1 1 0 RS RB RI 0 1\
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STW RS, (RB, RI+) 0 1 1 1 1 RS RB RI 0 1\
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LDB RD, (RB, \'96RI) 0 1 1 0 0 RD RB RI 1 0\
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LDW RD, (RB, \'96RI) 0 1 1 0 1 RD RB RI 1 0\
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STB RS, (RB, \'96RI) 0 1 1 1 0 RS RB RI 1 0\
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STW RS, (RB, \'96RI) 0 1 1 1 1 RS RB RI 1 0\
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\pard\pardeftab720\ql\qnatural
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\b \cf0 Bit Field Instructions\
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\pard\pardeftab720\ql\qnatural
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\b0 \cf0 BFEXT RD, RS1, RS2 0 1 1 0 0 RD RS1 RS2 1 1\
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BFINS RD, RS1, RS2 0 1 1 0 1 RD RS1 RS2 1 1\
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BFINSI RD, RS1, RS2 0 1 1 1 0 RD RS1 RS2 1 1\
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BFINSX RD, RS1, RS2 0 1 1 1 1 RD RS1 RS2 1 1\
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\pard\pardeftab720\ql\qnatural
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\b \cf0 Logic Immediate Instructions\
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\pard\pardeftab720\ql\qnatural
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\b0 \cf0 ANDL RD, #IMM8 1 0 0 0 0 RD IMM8\
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ANDH RD, #IMM8 1 0 0 0 1 RD IMM8\
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BITL RD, #IMM8 1 0 0 1 0 RD IMM8\
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BITH RD, #IMM8 1 0 0 1 1 RD IMM8\
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ORL RD, #IMM8 1 0 1 0 0 RD IMM8\
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ORH RD, #IMM8 1 0 1 0 1 RD IMM8\
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XNORL RD, #IMM8 1 0 1 1 0 RD IMM8\
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XNORH RD, #IMM8 1 0 1 1 1 RD IMM8\
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\pard\pardeftab720\ql\qnatural
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\b \cf0 Arithmetic Immediate Instructions\
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\pard\pardeftab720\ql\qnatural
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\b0 \cf0 SUBL RD, #IMM8 1 1 0 0 0 RD IMM8\
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SUBH RD, #IMM8 1 1 0 0 1 RD IMM8\
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CMPL RS, #IMM8 1 1 0 1 0 RS IMM8\
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CPCH RS, #IMM8 1 1 0 1 1 RS IMM8\
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ADDL RD, #IMM8 1 1 1 0 0 RD IMM8\
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ADDH RD, #IMM8 1 1 1 0 1 RD IMM8\
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LDL RD, #IMM8 1 1 1 1 0 RD IMM8\
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LDH RD, #IMM8 1 1 1 1 1 RD IMM8}

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