OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [sw/] [tools/] [misc/] [xgate_assembler.pl] - Blame information for rev 92

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 16 rehayes
#!/usr/bin/perl -w
2
 
3
 
4
sub fill_field {
5
  my($prototype, $data) = $_;
6
  my($i, $j);
7
  $j =  0;
8
  $out_field = "";
9
  for ($i = 0, $i <= 15, $i++) {
10
    if ($_[0][$i] eq "?") {
11
      $out_field = $_[1][$j] . $out_field;
12
      $j++;
13
    } else {
14
      $out_field = $_[0][$i] . $out_field;
15
  }
16
}
17
 
18
 
19
sub month_to_number {
20
  if ($_[0] eq "0") {
21
      $_[0] = "0";
22
  } elsif ($_[0] eq "1") {
23
      $_[0] = "1";
24
  } elsif ($_[0] eq "IMM3") {
25
      $_[0] = "???";
26
  } elsif ($_[0] eq "RS") {
27
      $_[0] = "???";
28
  } elsif ($_[0] eq "RD") {
29
      $_[0] = "???";
30
  } elsif ($_[0] eq "IMM4") {
31
      $_[0] = "????";
32
  } elsif ($_[0] eq "RS1") {
33
      $_[0] = "???";
34
  } elsif ($_[0] eq "RS2") {
35
      $_[0] = "???";
36
  } elsif ($_[0] eq "REL9") {
37
      $_[0] = "?????????";
38
  } elsif ($_[0] eq "REL10") {
39
      $_[0] = "??????????";
40
  } elsif ($_[0] eq "RB") {
41
      $_[0] = "???";
42
  } elsif ($_[0] eq "OFFS5") {
43
      $_[0] = "?????";
44
  } elsif ($_[0] eq "RI") {
45
      $_[0] = "???";
46
  } elsif ($_[0] eq "IMM8") {
47
      $_[0] = "????????";
48
  } else {
49
      printf "Bad Instruction Parameter: %s\n", $_[0];
50
      $_[0] = "";
51
  }
52
}
53
 
54
 
55
 
56
if( @ARGV < 1 ) {
57
  $progname = `basename $0`;
58
  chomp($progname);
59
  print "Syntax: $progname <Infile> <Outfile>\n";
60
  die;
61
} elsif ( @ARGV < 2 ) {
62
  print "Using default output file \"temp.v\"\n";
63
  $Infile = shift @ARGV;
64
  $Outfile = 'temp.v';
65
} else {
66
  $Infile = shift @ARGV;
67
  $Outfile = shift @ARGV;
68
}
69
 
70
open( source_file,  "<$Infile" )  || die "Could not open Input file";
71
open( verilog_file, ">$Outfile" ) || die "Could not open Output file";
72
 
73
$i = 1;
74
@op_code_list = ();
75
while (<source_file>) {
76
  chomp;
77
  #s/\\$//;      # remove trailing \
78
  #s/}$//;       # remove trailing }
79
  #s/{.*//;      # get rid of all the lines starting with {
80
  #s/\\\w*//g;   # get rid of all words starting with \
81
  s/;.*$//g;    # get rid of everything after ;
82
  s/ *$//g;     # get rid of trailing blanks
83
  s/^ *//g;     # get rid of all leading blanks
84
  if ($_) {
85
    if (! / [01] [01] / ) {
86
      print "\n      // Instruction Group -- $_ \n";
87
    } else {
88
      /( [01] )/;
89
      $inst = index($_, $1);
90
      $instruction = substr($_, 0, $inst);
91
      $op_code = substr($_, $inst++);
92
      # print "Instruction Line = $_\n";
93
      @bit_fields = split / /, $op_code;
94
      shift @bit_fields;  # get rid of leading blank element
95
      $case_var = "";
96
      foreach $field (@bit_fields) {
97
        $case_var = $case_var . &month_to_number($field);
98
      }
99
      push @op_code_list, $case_var;
100
      print "\n      // Instruction = $instruction, Op Code = $op_code\n";
101
      print "      16'b$case_var :\n";
102
     $i++;
103
    }
104
  }
105
}
106
 
107
 
108
close( source_file );
109
close( verilog_file );
110
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.