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[/] [xgate/] [trunk/] [sw/] [xgate_test_code/] [debug_test/] [debug_test.s] - Blame information for rev 81

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; 345678901234567890123456789012345678901234567890123456789012345678901234567890
; Instruction set test for xgate RISC processor core
; Bob Hayes - Sept 23 2009
;  Version 0.1 Basic tests of Debug Mode
 
 
        CPU     XGATE
 
        ORG     $fe00
        DS.W    2       ; reserve two words at channel 0
        ; channel 1
        DC.W    _START  ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 2
        DC.W    _START2 ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 3
        DC.W    _START3 ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 4
        DC.W    _START4 ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 5
        DC.W    _START5 ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 6
        DC.W    _START6 ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 7
        DC.W    _ERROR  ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 8
        DC.W    _ERROR  ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 9
        DC.W    _ERROR  ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 10
        DC.W    _ERROR  ; point to start address
        DC.W    V_PTR           ; point to initial variables
 
        ORG     $2000 ; with comment
 
V_PTR   EQU     123
 
 
        DC.W    BACK_
        DS.W    8
        DC.B    $56
        DS.B    11
 
        ALIGN   1
 
;-------------------------------------------------------------------------------
;   Place where undefined interrupts go
;-------------------------------------------------------------------------------
_ERROR
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
        LDH     R2,#$80
        LDL     R3,#$ff
        STB     R3,(R2,#0)
 
        SIF
        RTS
 
 
;-------------------------------------------------------------------------------
;   Test Debug Mode and Single Step instructions
;
;    Note: The testbench checks the PC values so adding or removing instructions
;          from this test will also require a change to the testbench
;          expected values.
;-------------------------------------------------------------------------------
_START
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
        LDH     R2,#$80
        LDL     R3,#$01
        STB     R3,(R2,#0)
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
 
 
        ; Test
        LDL     R4,#$c3 ;
        STW     R4,(R0,#$08)    ;
        LDL     R7,#$01         ; R3 = $01; R7 = $01
 
        BRK                     ; Enter Debug mode and start doing Single Step Commands
                                ;  from the testbench. Verify PC and R3 values.
 
        ADDL    R3,#$01         ; R3 + $01 => R3 (R3 = $02)
        NOP
        BRA     _BRA_OK1        ; Do Foward Branch Single Step
        ADDL    R3,#$40         ; For error detection
        NOP
        ADDL    R3,#$60         ; For error detection
_BRA_OK2
        STW     R3,(R0,#$0c)    ; 
        ADDL    R3,#$01         ; R3 + $01 => R3 (R3 = $04)
 
                                ; Testbench Clears Debug mode
 
        CMP     R4,R7           ; Check Load and Store commands received correct data
        BNE     _FAIL
        LDW     R5,(R0,#$0c)    ;
        ADDL    R5,#$01         ; R5 + $01 => R5 (R5 = $04) Catch up to latest R3 value
        CMP     R3,R5           ;
        BNE     _FAIL
 
        LDL     R2,#$00         ; Sent Message to Testbench Check Point Register
        LDH     R2,#$80
        LDL     R3,#$02
        STB     R3,(R2,#0)
 
        SIF
        RTS
 
_BRA_OK1
        ADDL    R3,#$01         ; R3 + $01 => R3 (R3 = $03)
        LDW     R7,(R0,#$08)    ;
        BRA     _BRA_OK2        ; Do Backward Branch
 
_FAIL
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
        LDH     R2,#$80
        LDL     R3,#$01
        STB     R3,(R2,#0)
 
        SIF
        RTS
 
 
;-------------------------------------------------------------------------------
;   Test Debug Command
;-------------------------------------------------------------------------------
_START2
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
        LDH     R2,#$80
        LDL     R3,#$03
        STB     R3,(R2,#0)
        LDL     R3,#$02    ; Thread Value
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
 
 
        ; Test
        LDL     R3,#$01         ; R3 = $01
        LDL     R4,#$01         ; R4 = $01
        LDL     R7,#$03         ; R7 = $03
 
_T2_LOOP
        ADDL    R3,#$01         ; R3 + $01 => R3 (R3 = $02)
        COM     R6              ; Toggle R6
        BRA     _T2_LOOP        ; Create an infinate loop. The testbench will
                                ;  take control using the Debug bit and change
                                ;  the PC to exit the loop.
 
        NOP
        NOP
        ADDL    R4,#$60         ; For error detection
        ADDL    R4,#$01         ; Test bench will set the PC to here
        ADDL    R4,#$01         ; 
 
        CMP     R4,R7           ; Check Load and Store commands received correct data
        BNE     _FAIL2
 
_END_2  LDL     R2,#$00         ; Sent Message to Testbench Check Point Register
        LDH     R2,#$80
        LDL     R3,#$04
        STB     R3,(R2,#0)
 
        SIF
        RTS
 
 
_FAIL2
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
        LDH     R2,#$80
        LDL     R3,#$02
        STB     R3,(R2,#0)
 
        SIF
        RTS
 
;-------------------------------------------------------------------------------
;   Test Debug and Change Channel ID Command
;-------------------------------------------------------------------------------
_START3
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
        LDH     R2,#$80
        LDL     R3,#$05
        STB     R3,(R2,#0)
        LDL     R3,#$03    ; Thread Value
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
 
 
        ; Test
        LDL     R3,#$01         ; R3 = $01
        LDL     R4,#$01         ; R4 = $01
        LDL     R7,#$03         ; R7 = $03
 
        BRK                     ; Enter Debug mode
 
        ; The testbench will use writes to the XGCHID reg to move to another
        ;  channel to complete the test.
 
_FAIL3
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
        LDH     R2,#$80
        LDL     R3,#$03
        STB     R3,(R2,#0)
 
        SIF
        RTS
 
;-------------------------------------------------------------------------------
;   Target for debug mode change CHID Command
;-------------------------------------------------------------------------------
_START4
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
        LDH     R2,#$80
        LDL     R3,#$06
        STB     R3,(R2,#0)
 
 
        ; Test
        BRK
 
_END_4  LDL     R2,#$00         ; Sent Message to Testbench Check Point Register
        LDH     R2,#$80
        LDL     R3,#$07
        STB     R3,(R2,#0)
 
        SIF
        RTS
 
 
_FAIL4
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
        LDH     R2,#$80
        LDL     R3,#$04
        STB     R3,(R2,#0)
 
        SIF
        RTS
 
;-------------------------------------------------------------------------------
;   False Target for debug mode change CHID Command
;    Verify that when the CHID command is issued that a higher poririty interrup
;    dosn't slip in.
;-------------------------------------------------------------------------------
_START5
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
        LDH     R2,#$80
        LDL     R3,#$08
        STB     R3,(R2,#0)
        LDL     R3,#$05    ; Thread Value
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
 
 
        ; Test
        BRK
 
_END_5  LDL     R2,#$00         ; Sent Message to Testbench Check Point Register
        LDH     R2,#$80
        LDL     R3,#$09
        STB     R3,(R2,#0)
 
        SIF
        RTS
 
 
_FAIL5
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
        LDH     R2,#$80
        LDL     R3,#$05
        STB     R3,(R2,#0)
 
        SIF
        RTS
 
;-------------------------------------------------------------------------------
;   Test Debug and Change Channel ID Command
;-------------------------------------------------------------------------------
_START6
        BRK                ; Enter Debug mode
        BRA     _GO6
        BRA     _FAIL6
_GO6
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
        LDH     R2,#$80
        LDL     R3,#$0a
        STB     R3,(R2,#0)
        LDL     R3,#$06    ; Thread Value
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
 
 
        ; Test
 
_END_6  LDL     R2,#$00         ; Sent Message to Testbench Check Point Register
        LDH     R2,#$80
        LDL     R3,#$0b
        STB     R3,(R2,#0)
 
        SIF
        RTS
 
 
_FAIL6
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
        LDH     R2,#$80
        LDL     R3,#$06
        STB     R3,(R2,#0)
 
        SIF
        RTS
 
 
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
 
 
;empty line
 
BACK_
 
 
        SIF     R7
        BRK
 
        ORG     $8000 ; Special Testbench Addresses
_BENCH  DS.W    8
 
 
 
 

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Subversion Repositories xgate

[/] [xgate/] [trunk/] [sw/] [xgate_test_code/] [debug_test/] [debug_test.s] - Blame information for rev 81

Line No.	Rev	Author	Line
1	16	rehayes	`; 345678901234567890123456789012345678901234567890123456789012345678901234567890`
2			`; Instruction set test for xgate RISC processor core`
3			`; Bob Hayes - Sept 23 2009`
4			`; Version 0.1 Basic tests of Debug Mode`
5
6
7			`CPU XGATE`
8
9			`ORG $fe00`
10			`DS.W 2 ; reserve two words at channel 0`
11			`; channel 1`
12			`DC.W _START ; point to start address`
13			`DC.W V_PTR ; point to initial variables`
14			`; channel 2`
15			`DC.W _START2 ; point to start address`
16			`DC.W V_PTR ; point to initial variables`
17			`; channel 3`
18			`DC.W _START3 ; point to start address`
19			`DC.W V_PTR ; point to initial variables`
20			`; channel 4`
21			`DC.W _START4 ; point to start address`
22			`DC.W V_PTR ; point to initial variables`
23			`; channel 5`
24			`DC.W _START5 ; point to start address`
25			`DC.W V_PTR ; point to initial variables`
26			`; channel 6`
27			`DC.W _START6 ; point to start address`
28			`DC.W V_PTR ; point to initial variables`
29			`; channel 7`
30			`DC.W _ERROR ; point to start address`
31			`DC.W V_PTR ; point to initial variables`
32			`; channel 8`
33			`DC.W _ERROR ; point to start address`
34			`DC.W V_PTR ; point to initial variables`
35			`; channel 9`
36			`DC.W _ERROR ; point to start address`
37			`DC.W V_PTR ; point to initial variables`
38			`; channel 10`
39			`DC.W _ERROR ; point to start address`
40			`DC.W V_PTR ; point to initial variables`
41
42			`ORG $2000 ; with comment`
43
44			`V_PTR EQU 123`
45
46
47			`DC.W BACK_`
48			`DS.W 8`
49			`DC.B $56`
50			`DS.B 11`
51
52			`ALIGN 1`
53
54			`;-------------------------------------------------------------------------------`
55			`; Place where undefined interrupts go`
56			`;-------------------------------------------------------------------------------`
57			`_ERROR`
58			`LDL R2,#$04 ; Sent Message to Testbench Error Register`
59			`LDH R2,#$80`
60			`LDL R3,#$ff`
61			`STB R3,(R2,#0)`
62
63			`SIF`
64			`RTS`
65
66
67			`;-------------------------------------------------------------------------------`
68			`; Test Debug Mode and Single Step instructions`
69			`;`
70			`; Note: The testbench checks the PC values so adding or removing instructions`
71			`; from this test will also require a change to the testbench`
72			`; expected values.`
73			`;-------------------------------------------------------------------------------`
74			`_START`
75			`LDL R2,#$00 ; Sent Message to Testbench Check Point Register`
76			`LDH R2,#$80`
77			`LDL R3,#$01`
78			`STB R3,(R2,#0)`
79			`STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register`
80
81
82			`; Test`
83			`LDL R4,#$c3 ;`
84			`STW R4,(R0,#$08) ;`
85	52	rehayes	`LDL R7,#$01 ; R3 = $01; R7 = $01`
86	16	rehayes
87			`BRK ; Enter Debug mode and start doing Single Step Commands`
88			`; from the testbench. Verify PC and R3 values.`
89
90			`ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $02)`
91			`NOP`
92			`BRA _BRA_OK1 ; Do Foward Branch Single Step`
93			`ADDL R3,#$40 ; For error detection`
94			`NOP`
95			`ADDL R3,#$60 ; For error detection`
96			`_BRA_OK2`
97			`STW R3,(R0,#$0c) ;`
98			`ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $04)`
99
100			`; Testbench Clears Debug mode`
101
102			`CMP R4,R7 ; Check Load and Store commands received correct data`
103			`BNE _FAIL`
104			`LDW R5,(R0,#$0c) ;`
105			`ADDL R5,#$01 ; R5 + $01 => R5 (R5 = $04) Catch up to latest R3 value`
106			`CMP R3,R5 ;`
107			`BNE _FAIL`
108
109			`LDL R2,#$00 ; Sent Message to Testbench Check Point Register`
110			`LDH R2,#$80`
111			`LDL R3,#$02`
112			`STB R3,(R2,#0)`
113
114			`SIF`
115			`RTS`
116
117			`_BRA_OK1`
118			`ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $03)`
119			`LDW R7,(R0,#$08) ;`
120			`BRA _BRA_OK2 ; Do Backward Branch`
121
122			`_FAIL`
123			`LDL R2,#$04 ; Sent Message to Testbench Error Register`
124			`LDH R2,#$80`
125			`LDL R3,#$01`
126			`STB R3,(R2,#0)`
127
128			`SIF`
129			`RTS`
130
131
132			`;-------------------------------------------------------------------------------`
133			`; Test Debug Command`
134			`;-------------------------------------------------------------------------------`
135			`_START2`
136			`LDL R2,#$00 ; Sent Message to Testbench Check Point Register`
137			`LDH R2,#$80`
138			`LDL R3,#$03`
139			`STB R3,(R2,#0)`
140			`LDL R3,#$02 ; Thread Value`
141			`STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register`
142
143
144			`; Test`
145			`LDL R3,#$01 ; R3 = $01`
146			`LDL R4,#$01 ; R4 = $01`
147			`LDL R7,#$03 ; R7 = $03`
148
149			`_T2_LOOP`
150			`ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $02)`
151	52	rehayes	`COM R6 ; Toggle R6`
152	16	rehayes	`BRA _T2_LOOP ; Create an infinate loop. The testbench will`
153			`; take control using the Debug bit and change`
154			`; the PC to exit the loop.`
155
156			`NOP`
157			`NOP`
158			`ADDL R4,#$60 ; For error detection`
159			`ADDL R4,#$01 ; Test bench will set the PC to here`
160			`ADDL R4,#$01 ;`
161
162			`CMP R4,R7 ; Check Load and Store commands received correct data`
163			`BNE _FAIL2`
164
165			`_END_2 LDL R2,#$00 ; Sent Message to Testbench Check Point Register`
166			`LDH R2,#$80`
167			`LDL R3,#$04`
168			`STB R3,(R2,#0)`
169
170			`SIF`
171			`RTS`
172
173
174			`_FAIL2`
175			`LDL R2,#$04 ; Sent Message to Testbench Error Register`
176			`LDH R2,#$80`
177			`LDL R3,#$02`
178			`STB R3,(R2,#0)`
179
180			`SIF`
181			`RTS`
182
183			`;-------------------------------------------------------------------------------`
184			`; Test Debug and Change Channel ID Command`
185			`;-------------------------------------------------------------------------------`
186			`_START3`
187			`LDL R2,#$00 ; Sent Message to Testbench Check Point Register`
188			`LDH R2,#$80`
189			`LDL R3,#$05`
190			`STB R3,(R2,#0)`
191			`LDL R3,#$03 ; Thread Value`
192			`STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register`
193
194
195			`; Test`
196			`LDL R3,#$01 ; R3 = $01`
197			`LDL R4,#$01 ; R4 = $01`
198			`LDL R7,#$03 ; R7 = $03`
199
200			`BRK ; Enter Debug mode`
201
202			`; The testbench will use writes to the XGCHID reg to move to another`
203			`; channel to complete the test.`
204
205			`_FAIL3`
206			`LDL R2,#$04 ; Sent Message to Testbench Error Register`
207			`LDH R2,#$80`
208			`LDL R3,#$03`
209			`STB R3,(R2,#0)`
210
211			`SIF`
212			`RTS`
213
214			`;-------------------------------------------------------------------------------`
215			`; Target for debug mode change CHID Command`
216			`;-------------------------------------------------------------------------------`
217			`_START4`
218			`LDL R2,#$00 ; Sent Message to Testbench Check Point Register`
219			`LDH R2,#$80`
220			`LDL R3,#$06`
221			`STB R3,(R2,#0)`
222
223
224			`; Test`
225			`BRK`
226
227			`_END_4 LDL R2,#$00 ; Sent Message to Testbench Check Point Register`
228			`LDH R2,#$80`
229			`LDL R3,#$07`
230			`STB R3,(R2,#0)`
231
232			`SIF`
233			`RTS`
234
235
236			`_FAIL4`
237			`LDL R2,#$04 ; Sent Message to Testbench Error Register`
238			`LDH R2,#$80`
239			`LDL R3,#$04`
240			`STB R3,(R2,#0)`
241
242			`SIF`
243			`RTS`
244
245			`;-------------------------------------------------------------------------------`
246			`; False Target for debug mode change CHID Command`
247			`; Verify that when the CHID command is issued that a higher poririty interrup`
248			`; dosn't slip in.`
249			`;-------------------------------------------------------------------------------`
250			`_START5`
251			`LDL R2,#$00 ; Sent Message to Testbench Check Point Register`
252			`LDH R2,#$80`
253			`LDL R3,#$08`
254			`STB R3,(R2,#0)`
255			`LDL R3,#$05 ; Thread Value`
256			`STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register`
257
258
259			`; Test`
260			`BRK`
261
262			`_END_5 LDL R2,#$00 ; Sent Message to Testbench Check Point Register`
263			`LDH R2,#$80`
264			`LDL R3,#$09`
265			`STB R3,(R2,#0)`
266
267			`SIF`
268			`RTS`
269
270
271			`_FAIL5`
272			`LDL R2,#$04 ; Sent Message to Testbench Error Register`
273			`LDH R2,#$80`
274			`LDL R3,#$05`
275			`STB R3,(R2,#0)`
276
277			`SIF`
278			`RTS`
279
280			`;-------------------------------------------------------------------------------`
281			`; Test Debug and Change Channel ID Command`
282			`;-------------------------------------------------------------------------------`
283			`_START6`
284			`BRK ; Enter Debug mode`
285			`BRA _GO6`
286			`BRA _FAIL6`
287			`_GO6`
288			`LDL R2,#$00 ; Sent Message to Testbench Check Point Register`
289			`LDH R2,#$80`
290			`LDL R3,#$0a`
291			`STB R3,(R2,#0)`
292			`LDL R3,#$06 ; Thread Value`
293			`STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register`
294
295
296			`; Test`
297
298			`_END_6 LDL R2,#$00 ; Sent Message to Testbench Check Point Register`
299			`LDH R2,#$80`
300			`LDL R3,#$0b`
301			`STB R3,(R2,#0)`
302
303			`SIF`
304			`RTS`
305
306
307			`_FAIL6`
308			`LDL R2,#$04 ; Sent Message to Testbench Error Register`
309			`LDH R2,#$80`
310			`LDL R3,#$06`
311			`STB R3,(R2,#0)`
312
313			`SIF`
314			`RTS`
315
316
317			`;-------------------------------------------------------------------------------`
318			`;-------------------------------------------------------------------------------`
319
320
321			`;empty line`
322
323			`BACK_`
324
325
326			`SIF R7`
327			`BRK`
328
329			`ORG $8000 ; Special Testbench Addresses`
330			`_BENCH DS.W 8`
331
332
333
334