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[/] [xgate/] [trunk/] [sw/] [xgate_test_code/] [inst_test/] [inst_test.s] - Blame information for rev 101

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Line No. Rev Author Line
1 16 rehayes 
; 345678901234567890123456789012345678901234567890123456789012345678901234567890
2 
; Instruction set test for xgate RISC processor core
3 
; Bob Hayes - Sept 1 2009
4 
;  Version 0.1 Basic test of all instruction done. Need to improve Condition
5 
;               Code function testing.
6 
 
7 
 
8 89 rehayes 
        CPU     XGATE
9 16 rehayes 
 
10 89 rehayes 
        ORG     $fe00
11 
        DS.W    2       ; reserve two words at channel 0
12 
        ; channel 1
13 
        DC.W    _START  ; point to start address
14 
        DC.W    V_PTR   ; point to initial variables
15 
        ; channel 2
16 
        DC.W    _START2 ; point to start address
17 
        DC.W    V_PTR   ; point to initial variables
18 
        ; channel 3
19 
        DC.W    _START3 ; point to start address
20 
        DC.W    V_PTR   ; point to initial variables
21 
        ; channel 4
22 
        DC.W    _START4 ; point to start address
23 
        DC.W    V_PTR   ; point to initial variables
24 
        ; channel 5
25 
        DC.W    _START5 ; point to start address
26 
        DC.W    V_PTR   ; point to initial variables
27 
        ; channel 6
28 
        DC.W    _START6 ; point to start address
29 
        DC.W    V_PTR   ; point to initial variables
30 
        ; channel 7
31 
        DC.W    _START7 ; point to start address
32 
        DC.W    V_PTR   ; point to initial variables
33 
        ; channel 8
34 
        DC.W    _START8 ; point to start address
35 
        DC.W    V_PTR   ; point to initial variables
36 
        ; channel 9
37 
        DC.W    _START9 ; point to start address
38 
        DC.W    V_PTR   ; point to initial variables
39 
        ; channel 10
40 
        DC.W    _START10        ; point to start address
41 
        DC.W    V_PTR           ; point to initial variables
42 
        ; channel 11
43 
        DC.W    _ERROR          ; point to start address
44 
        DC.W    V_PTR           ; point to initial variables
45 
        ; channel 12
46 
        DC.W    _ERROR          ; point to start address
47 
        DC.W    V_PTR           ; point to initial variables
48 
        ; channel 13
49 
        DC.W    _ERROR          ; point to start address
50 
        DC.W    V_PTR           ; point to initial variables
51 
        ; channel 14
52 
        DC.W    _ERROR          ; point to start address
53 
        DC.W    V_PTR           ; point to initial variables
54 
        ; channel 15
55 
        DC.W    _ERROR          ; point to start address
56 
        DC.W    V_PTR           ; point to initial variables
57 
        ; channel 16
58 
        DC.W    _ERROR  ; point to start address
59 
        DC.W    V_PTR   ; point to initial variables
60 
        ; channel 17
61 
        DC.W    _ERROR  ; point to start address
62 
        DC.W    V_PTR   ; point to initial variables
63 
        ; channel 18
64 
        DC.W    _ERROR  ; point to start address
65 
        DC.W    V_PTR   ; point to initial variables
66 
        ; channel 19
67 
        DC.W    _ERROR  ; point to start address
68 
        DC.W    V_PTR   ; point to initial variables
69 
        ; channel 20
70 
        DC.W    _ERROR  ; point to start address
71 
        DC.W    V_PTR   ; point to initial variables
72 
        ; channel 21
73 
        DC.W    _ERROR  ; point to start address
74 
        DC.W    V_PTR   ; point to initial variables
75 
        ; channel 22
76 
        DC.W    _ERROR  ; point to start address
77 
        DC.W    V_PTR   ; point to initial variables
78 
        ; channel 23
79 
        DC.W    _ERROR  ; point to start address
80 
        DC.W    V_PTR   ; point to initial variables
81 
        ; channel 24
82 
        DC.W    _ERROR  ; point to start address
83 
        DC.W    V_PTR   ; point to initial variables
84 
        ; channel 25
85 
        DC.W    _ERROR  ; point to start address
86 
        DC.W    V_PTR   ; point to initial variables
87 
        ; channel 26
88 
        DC.W    _ERROR  ; point to start address
89 
        DC.W    V_PTR   ; point to initial variables
90 
        ; channel 27
91 
        DC.W    _ERROR  ; point to start address
92 
        DC.W    V_PTR   ; point to initial variables
93 
        ; channel 28
94 
        DC.W    _ERROR  ; point to start address
95 
        DC.W    V_PTR   ; point to initial variables
96 
        ; channel 29
97 
        DC.W    _ERROR  ; point to start address
98 
        DC.W    V_PTR   ; point to initial variables
99 
        ; channel 30
100 
        DC.W    _ERROR  ; point to start address
101 
        DC.W    V_PTR   ; point to initial variables
102 
        ; channel 31
103 
        DC.W    _ERROR  ; point to start address
104 
        DC.W    V_PTR   ; point to initial variables
105 
        ; channel 32
106 
        DC.W    _ERROR  ; point to start address
107 
        DC.W    V_PTR   ; point to initial variables
108 
        ; channel 33
109 
        DC.W    _ERROR  ; point to start address
110 
        DC.W    V_PTR   ; point to initial variables
111 
        ; channel 34
112 
        DC.W    _ERROR  ; point to start address
113 
        DC.W    V_PTR   ; point to initial variables
114 
        ; channel 35
115 
        DC.W    _ERROR  ; point to start address
116 
        DC.W    V_PTR   ; point to initial variables
117 
        ; channel 36
118 
        DC.W    _ERROR  ; point to start address
119 
        DC.W    V_PTR   ; point to initial variables
120 
        ; channel 37
121 
        DC.W    _ERROR  ; point to start address
122 
        DC.W    V_PTR   ; point to initial variables
123 
        ; channel 38
124 
        DC.W    _ERROR  ; point to start address
125 
        DC.W    V_PTR   ; point to initial variables
126 
        ; channel 39
127 
        DC.W    _ERROR  ; point to start address
128 
        DC.W    V_PTR   ; point to initial variables
129 
        ; channel 40
130 
        DC.W    _ERROR  ; point to start address
131 
        DC.W    V_PTR   ; point to initial variables
132 
        ; channel 41
133 
        DC.W    _ERROR  ; point to start address
134 
        DC.W    V_PTR   ; point to initial variables
135 
        ; channel 42
136 
        DC.W    _ERROR  ; point to start address
137 
        DC.W    V_PTR   ; point to initial variables
138 
        ; channel 43
139 
        DC.W    _ERROR  ; point to start address
140 
        DC.W    V_PTR   ; point to initial variables
141 
        ; channel 44
142 
        DC.W    _ERROR  ; point to start address
143 
        DC.W    V_PTR   ; point to initial variables
144 
        ; channel 45
145 
        DC.W    _ERROR  ; point to start address
146 
        DC.W    V_PTR   ; point to initial variables
147 
        ; channel 46
148 
        DC.W    _ERROR  ; point to start address
149 
        DC.W    V_PTR   ; point to initial variables
150 
        ; channel 47
151 
        DC.W    _ERROR  ; point to start address
152 
        DC.W    V_PTR   ; point to initial variables
153 
        ; channel 48
154 
        DC.W    _ERROR  ; point to start address
155 
        DC.W    V_PTR   ; point to initial variables
156 
        ; channel 49
157 
        DC.W    _ERROR  ; point to start address
158 
        DC.W    V_PTR   ; point to initial variables
159 
        ; channel 50
160 
        DC.W    _ERROR  ; point to start address
161 
        DC.W    V_PTR   ; point to initial variables
162 16 rehayes 
 
163 89 rehayes 
        ORG     $2000 ; with comment
164 16 rehayes 
 
165 89 rehayes 
V_PTR   EQU     123
166 16 rehayes 
 
167 89 rehayes 
        DC.W    BACK_
168 
        DS.W    8
169 
        DC.B    $56
170 
        DS.B    11
171 16 rehayes 
 
172 89 rehayes 
        ALIGN   1
173 
 
174 16 rehayes 
;-------------------------------------------------------------------------------
175 
;   Place where undefined interrupts go
176 
;-------------------------------------------------------------------------------
177 
_ERROR
178 89 rehayes 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
179 
        LDH     R2,#$80
180 
        LDL     R3,#$ff
181 
        STB     R3,(R2,#0)
182 
 
183 16 rehayes 
        SIF
184 89 rehayes 
        RTS
185 16 rehayes 
 
186 
 
187 
;-------------------------------------------------------------------------------
188 
;   Test Shift instructions
189 
;-------------------------------------------------------------------------------
190 
_START
191 89 rehayes 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
192 
        LDH     R2,#$80
193 
        LDL     R3,#$01
194 
        STB     R3,(R2,#0)
195 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
196 16 rehayes 
 
197 
 
198 89 rehayes 
        ; Test Bit Field Find First One
199 
        LDL     R5,#$01  ; R5=$0001
200 
        LDH     R5,#$4f  ; R5=$4f01
201 90 rehayes 
        BFFO    R4,R5    ; Result in R4
202 89 rehayes 
        BVS     _FAIL    ; Negative Flag should be clear
203 
        LDL     R6,#$0e  ; First one should have been in bit position 14
204 
        SUB     R0,R6,R4
205 
        BNE     _FAIL
206 
        BFFO    R4,R0    ; Zero Value should set Carry Bit
207 
        BCC     _FAIL
208 
        LDH     R5,#$00  ; R5=$0001
209 
        BFFO    R4,R5
210 
        BCS     _FAIL    ; Carry should be clear
211 
        BVS     _FAIL    ; Overflow Flag should be clear
212 90 rehayes 
        SUB     R0,R0,R4 ; R4 Should be zero - ie. zero bit set
213 89 rehayes 
        BNE     _FAIL
214 16 rehayes 
 
215 89 rehayes 
       ; Test ASR instruction **************************************************
216 
        LDL     R5,#$04  ; R5=$0008
217 
        LDH     R5,#$81  ; R5=$8108
218 
        LDL     R3,#$03
219 
        ASR     R5,R3    ; R5=$f000, Carry flag set
220 
        BCC     _FAIL
221 
        BVS     _FAIL    ; Negative Flag should be clear
222 
        LDL     R4,#$20  ; R4=$0020
223 
        LDH     R4,#$f0  ; R4=$f020
224 
        SUB     R0,R5,R4 ; Compare R5 to R4
225 
        BNE     _FAIL
226 16 rehayes 
 
227 89 rehayes 
       ; Test CSL instruction **************************************************
228 
        LDL     R5,#$10  ; R5=$0010
229 
        LDH     R5,#$88  ; R5=$8810
230 
        LDL     R3,#$05
231 
        CSL     R5,R3    ; R5=$081f, Carry flag set
232 
        BCC     _FAIL
233 
        LDL     R4,#$00  ; R4=$0000
234 
        LDH     R4,#$02  ; R4=$0200
235 
        SUB     R0,R5,R4 ; Compare R5 to R4
236 
        BNE     _FAIL
237 
 
238 
       ;Test CSR instruction ***************************************************
239 
        LDL     R5,#$88  ; R5=$0088
240 
        LDH     R5,#$10  ; R5=$1088
241 
        LDL     R3,#$04
242 
        CSR     R5,R3    ; R5=$0108, Carry flag set
243 
        BCC     _FAIL
244 
        LDL     R4,#$08  ; R4=$0008
245 
        LDH     R4,#$01  ; R4=$0108
246 
        SUB     R0,R5,R4 ; Compare R5 to R4
247 
        BNE     _FAIL
248 
 
249 
       ;Test LSL instruction ***************************************************
250 
        LDL     R2,#$ff  ; R2=$00ff
251 
        LDH     R2,#$07  ; R2=$07ff
252 
        LDL     R1,#$06
253 
        LSL     R2,R1    ; R2=$ffc0, Carry flag set
254 
        BCC     _FAIL
255 
        LDL     R4,#$c0  ; R4=$0008
256 
        LDH     R4,#$ff  ; R4=$0108
257 
        SUB     R0,R2,R4 ; Compare R2 to R4
258 
        BNE     _FAIL
259 
 
260 
       ;Test LSR instruction ***************************************************
261 
        LDL     R7,#$02  ; R7=$0002
262 
        LDH     R7,#$c3  ; R7=$c302
263 
        LDL     R6,#$02
264 
        LSR     R7,R6    ; R7=$30c0, Carry flag set
265 
        BCC     _FAIL
266 
        LDL     R4,#$c0  ; R4=$00c0
267 
        LDH     R4,#$30  ; R4=$30c0
268 
        SUB     R0,R7,R4 ; Compare R7 to R4
269 
        BNE     _FAIL
270 
 
271 
       ;Test ROL instruction ***************************************************
272 
        LDL     R7,#$62  ; R7=$0062
273 
        LDH     R7,#$c3  ; R7=$c362
274 
        LDL     R6,#$04
275 
        ROL     R7,R6    ; R7=$362c
276 
        BVS     _FAIL    ; Overflow Flag should be clear
277 
        LDL     R4,#$2c  ; R4=$002c
278 
        LDH     R4,#$36  ; R4=$362c
279 
        SUB     R0,R7,R4 ; Compare R7 to R4
280 
        BNE     _FAIL
281 
 
282 
       ;Test ROR instruction ***************************************************
283 
        LDL     R7,#$62  ; R7=$0062
284 
        LDH     R7,#$c3  ; R7=$c362
285 
        LDL     R6,#$08
286 
        ROR     R7,R6    ; R7=$62c3
287 
        BVS     _FAIL    ; Overflow Flag should be clear
288 
        LDL     R4,#$c3  ; R4=$00c3
289 
        LDH     R4,#$62  ; R4=$62c3
290 
        SUB     R0,R7,R4 ; Compare R7 to R4
291 
        BNE     _FAIL
292 
 
293 
       ; Test ASR instruction **************************************************
294 
        LDL     R5,#$00  ; R5=$0000
295 
        LDH     R5,#$80  ; R5=$8000
296 
        ASR     R5,#0    ; R5=$ffff, Carry flag set
297 
        BCC     _FAIL
298 
        BVS     _FAIL    ; Overflow Flag should be clear
299 
        LDL     R4,#$ff  ; R4=$00ff
300 
        LDH     R4,#$ff  ; R4=$ffff
301 
        SUB     R0,R5,R4 ; Compare R5 to R4
302 
        BNE     _FAIL
303 
 
304 
       ; Test CSL insrtruction
305 
        LDL     R5,#$01  ; R5=$0001
306 
        LDH     R5,#$0f  ; R5=$0f01
307 
        CSL     R5,#0    ; R5=$0000, Carry flag set
308 
        BCC     _FAIL
309 
        LDL     R4,#$00  ; R4=$0000
310 
        LDH     R4,#$00  ; R4=$0000
311 
        SUB     R0,R5,R4 ; Compare R5 to R4
312 
        BNE     _FAIL
313 
 
314 
       ;Test CSR instruction ***************************************************
315 
        LDL     R5,#$ff  ; R5=$00ff
316 
        LDH     R5,#$80  ; R5=$80ff
317 
        CSR     R5,#15   ; R5=$0001, Carry flag clear
318 
        BCS     _FAIL
319 
        LDL     R4,#$01  ; R4=$0001
320 
        LDH     R4,#$00  ; R4=$0001
321 
        SUB     R0,R5,R4 ; Compare R5 to R4
322 
        BNE     _FAIL
323 
 
324 
       ;Test LSL instruction ***************************************************
325 
        LDL     R2,#$1a  ; R2=$001a
326 
        LDH     R2,#$ff  ; R2=$ff1a
327 
        LSL     R2,#12   ; R2=$a000, Carry flag set
328 
        BCC     _FAIL
329 
        LDL     R4,#$00  ; R4=$0000
330 
        LDH     R4,#$a0  ; R4=$a000
331 
        SUB     R0,R2,R4 ; Compare R2 to R4
332 
        BNE     _FAIL
333 
 
334 
       ;Test LSR instruction ***************************************************
335 
        LDL     R7,#$8f  ; R7=$008f
336 
        LDH     R7,#$b2  ; R7=$b18f
337 
        LSR     R7,#8    ; R7=$00b0, Carry flag set
338 
        BCC     _FAIL
339 
        LDL     R4,#$b2  ; R4=$00b0
340 
        LDH     R4,#$00  ; R4=$00b0
341 
        SUB     R0,R7,R4 ; Compare R7 to R4
342 
        BNE     _FAIL
343 
 
344 
       ;Test ROL instruction ***************************************************
345 
        LDL     R7,#$62  ; R7=$0062
346 
        LDH     R7,#$c3  ; R7=$c362
347 
        ROL     R7,#8    ; R7=$62c3
348 
        BVS     _FAIL    ; Overflow Flag should be clear
349 
        LDL     R4,#$c3  ; R4=$00c3
350 
        LDH     R4,#$62  ; R4=$62c3
351 
        SUB     R0,R7,R4 ; Compare R7 to R4
352 
        BNE     _FAIL
353 
 
354 
       ;Test ROR instruction ***************************************************
355 
        LDL     R7,#$62  ; R7=$0062
356 
        LDH     R7,#$c3  ; R7=$c362
357 
        ROR     R7,#12   ; R7=$362c
358 
        BVS     _FAIL    ; Overflow Flag should be clear
359 
        LDL     R4,#$2c  ; R4=$002c
360 
        LDH     R4,#$36  ; R4=$362c
361 
        SUB     R0,R7,R4 ; Compare R7 to R4
362 
        BNE     _FAIL
363 
 
364 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
365 
        LDH     R2,#$80
366 
        LDL     R3,#$02
367 
        STB     R3,(R2,#0)
368 
 
369 
        NOP
370 
        NOP
371 
        SIF
372 
        RTS
373 
 
374 16 rehayes 
_FAIL
375 89 rehayes 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
376 
        LDH     R2,#$80
377 
        LDL     R3,#$02
378 
        STB     R3,(R2,#0)
379 16 rehayes 
 
380 
        SIF
381 89 rehayes 
        RTS
382 16 rehayes 
 
383 
;-------------------------------------------------------------------------------
384 
;   Test Logical Byte wide instructions
385 
;-------------------------------------------------------------------------------
386 
_START2
387 89 rehayes 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
388 
        LDH     R2,#$80
389 
        LDL     R3,#$03    ; Checkpoint Value
390 
        STB     R3,(R2,#0)
391 
        LDL     R3,#$02    ; Thread Value
392 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
393 16 rehayes 
 
394 89 rehayes 
       ;Test ANDL instruction **************************************************
395 
        LDL     R7,#$55  ; R7=$0055
396 
        LDH     R7,#$a5  ; R7=$a555
397 
        ANDL    R7,#$00  ; R7=&a500
398 
        BNE     _FAIL2   ; Zero Flag should be set
399 
        BVS     _FAIL2   ; Overflow Flag should be clear
400 
        BMI     _FAIL2   ; Negative Flag should be clear
401 
        LDL     R3,#$00  ; R3=$0000
402 
        LDH     R3,#$a5  ; R3=$a500
403 
        SUB     R0,R7,R3 ; Compare R7 to R3
404 
        BNE     _FAIL2
405 
        LDL     R7,#$c5  ; R7=$00c5
406 
        LDH     R7,#$a5  ; R7=$a5c5
407 
        ANDL    R7,#$80  ; R7=$a580
408 
        BPL     _FAIL2   ; Negative Flag should be set
409 
        BEQ     _FAIL2   ; Zero Flag should be clear
410 
        BVS     _FAIL2   ; Overflow Flag should be clear
411 
        LDL     R3,#$80  ; R3=$0080
412 
        LDH     R3,#$a5  ; R3=$a580
413 
        SUB     R0,R7,R3 ; Compare R7 to R3
414 
        BNE     _FAIL2
415 16 rehayes 
 
416 89 rehayes 
       ;Test ANDH instruction **************************************************
417 
        LDL     R7,#$55  ; R7=$0055
418 
        LDH     R7,#$a5  ; R7=$a555
419 
        ANDH    R7,#$00  ; R7=&0055
420 
        BNE     _FAIL2   ; Zero Flag should be set
421 
        BVS     _FAIL2   ; Overflow Flag should be clear
422 
        BMI     _FAIL2   ; Negative Flag should be clear
423 
        LDL     R3,#$55  ; R3=$0000
424 
        LDH     R3,#$00  ; R3=$a500
425 
        SUB     R0,R7,R3 ; Compare R7 to R3
426 
        BNE     _FAIL2
427 
        LDL     R7,#$c5  ; R7=$00c5
428 
        LDH     R7,#$a5  ; R7=$a5c5
429 
        ANDH    R7,#$80  ; R7=$80c5
430 
        BPL     _FAIL2   ; Negative Flag should be set
431 
        BEQ     _FAIL2   ; Zero Flag should be clear
432 
        BVS     _FAIL2   ; Overflow Flag should be clear
433 
        LDL     R3,#$c5  ; R3=$00c5
434 
        LDH     R3,#$80  ; R3=$80c5
435 
        SUB     R0,R7,R3 ; Compare R7 to R3
436 
        BNE     _FAIL2
437 16 rehayes 
 
438 89 rehayes 
       ;Test BITL instruction **************************************************
439 
        LDL     R7,#$55  ; R7=$0055
440 
        LDH     R7,#$a5  ; R7=$a555
441 
        BITL    R7,#$00  ; R7=&a500
442 
        BNE     _FAIL2   ; Zero Flag should be set
443 
        BVS     _FAIL2   ; Overflow Flag should be clear
444 
        BMI     _FAIL2   ; Negative Flag should be clear
445 
        LDL     R7,#$c5  ; R7=$00c5
446 
        LDH     R7,#$a5  ; R7=$a5c5
447 
        BITL    R7,#$80  ; R7=$a580
448 
        BPL     _FAIL2   ; Negative Flag should be set
449 
        BEQ     _FAIL2   ; Zero Flag should be clear
450 
        BVS     _FAIL2   ; Overflow Flag should be clear
451 16 rehayes 
 
452 89 rehayes 
       ;Test BITH instruction **************************************************
453 
        LDL     R7,#$55  ; R7=$0055
454 
        LDH     R7,#$a5  ; R7=$a555
455 
        BITH    R7,#$00  ; R7=&0055
456 
        BNE     _FAIL2   ; Zero Flag should be set
457 
        BVS     _FAIL2   ; Overflow Flag should be clear
458 
        BMI     _FAIL2   ; Negative Flag should be clear
459 
        LDL     R7,#$c5  ; R7=$00c5
460 
        LDH     R7,#$a5  ; R7=$a5c5
461 
        BITH    R7,#$80  ; R7=$80c5
462 
        BPL     _FAIL2   ; Negative Flag should be set
463 
        BEQ     _FAIL2   ; Zero Flag should be clear
464 
        BVS     _FAIL2   ; Overflow Flag should be clear
465 
 
466 
       ;Test ORL instruction ***************************************************
467 16 rehayes 
        LDL     R2,#$0b
468 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=1
469 
        LDL     R7,#$00  ; R7=$0000
470 
        LDH     R7,#$a5  ; R7=$a500
471 
        ORL     R7,#$00  ; R7=&a500
472 
        BMI     _FAIL2   ; Negative Flag should be clear
473 
        BNE     _FAIL2   ; Zero Flag should be set
474 
        BVS     _FAIL2   ; Overflow Flag should be clear
475 
        BCC     _FAIL2   ; Carry Flag should be set
476 
        LDL     R3,#$00  ; R3=$0000
477 
        LDH     R3,#$a5  ; R3=$a500
478 
        SUB     R0,R7,R3 ; Compare R7 to R3
479 
        BNE     _FAIL2
480 16 rehayes 
        LDL     R2,#$06
481 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=1, Carry=0
482 
        LDL     R7,#$9f  ; R7=$009f
483 
        LDH     R7,#$a5  ; R7=$a59f
484 
        ORL     R7,#$60  ; R7=$a5ff
485 
        BPL     _FAIL2   ; Negative Flag should be set
486 
        BEQ     _FAIL2   ; Zero Flag should be clear
487 
        BVS     _FAIL2   ; Overflow Flag should be clear
488 
        BCS     _FAIL2   ; Carry Flag should be clear
489 
        LDL     R3,#$ff  ; R3=$00ff
490 
        LDH     R3,#$a5  ; R3=$a5ff
491 
        SUB     R0,R7,R3 ; Compare R7 to R3
492 
        BNE     _FAIL2
493 16 rehayes 
 
494 89 rehayes 
       ;Test ORH instruction ***************************************************
495 16 rehayes 
        LDL     R2,#$0b
496 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=1
497 
        LDL     R7,#$88  ; R7=$0088
498 
        LDH     R7,#$00  ; R7=$0088
499 
        ORH     R7,#$00  ; R7=&0088
500 
        BMI     _FAIL2   ; Negative Flag should be clear
501 
        BNE     _FAIL2   ; Zero Flag should be set
502 
        BVS     _FAIL2   ; Overflow Flag should be clear
503 
        BCC     _FAIL2   ; Carry Flag should be set
504 
        LDL     R3,#$88  ; R3=$0088
505 
        LDH     R3,#$00  ; R3=$0088
506 
        SUB     R0,R7,R3 ; Compare R7 to R3
507 
        BNE     _FAIL2
508 16 rehayes 
        LDL     R2,#$06
509 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=1, Carry=0
510 
        LDL     R7,#$36  ; R7=$0036
511 
        LDH     R7,#$a1  ; R7=$a136
512 
        ORH     R7,#$50  ; R7=$f136
513 
        BPL     _FAIL2   ; Negative Flag should be set
514 
        BEQ     _FAIL2   ; Zero Flag should be clear
515 
        BVS     _FAIL2   ; Overflow Flag should be clear
516 
        BCS     _FAIL2   ; Carry Flag should be clear
517 
        LDL     R3,#$36  ; R3=$0036
518 
        LDH     R3,#$f1  ; R3=$f136
519 
        SUB     R0,R7,R3 ; Compare R7 to R3
520 
        BNE     _FAIL2
521 16 rehayes 
 
522 89 rehayes 
       ;Test XNORL instruction *************************************************
523 16 rehayes 
        LDL     R2,#$0b
524 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=1
525 
        LDL     R7,#$c3  ; R7=$00c3
526 
        LDH     R7,#$96  ; R7=$96c3
527 
        XNORL   R7,#$3c  ; R7=$9600
528 
        BMI     _FAIL2   ; Negative Flag should be clear
529 
        BNE     _FAIL2   ; Zero Flag should be set
530 
        BVS     _FAIL2   ; Overflow Flag should be clear
531 
        BCC     _FAIL2   ; Carry Flag should be set
532 
        LDL     R3,#$00  ; R3=$0000
533 
        LDH     R3,#$96  ; R3=$9600
534 
        SUB     R0,R7,R3 ; Compare R7 to R3
535 
        BNE     _FAIL2
536 16 rehayes 
        LDL     R2,#$06
537 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=1, Carry=0
538 
        LDL     R6,#$00  ; R6=$0000
539 
        LDH     R6,#$a5  ; R6=$a500
540 
        XNORL   R6,#$73  ; R6=$a58c
541 
        BPL     _FAIL2   ; Negative Flag should be set
542 
        BEQ     _FAIL2   ; Zero Flag should be clear
543 
        BVS     _FAIL2   ; Overflow Flag should be clear
544 
        BCS     _FAIL2   ; Carry Flag should be clear
545 
        LDL     R3,#$8c  ; R3=$008c
546 
        LDH     R3,#$a5  ; R3=$a58c
547 
        SUB     R0,R6,R3 ; Compare R6 to R3
548 
        BNE     _FAIL2
549 16 rehayes 
 
550 89 rehayes 
       ;Test XNORH instruction *************************************************
551 16 rehayes 
        LDL     R2,#$0b
552 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=1
553 
        LDL     R7,#$c3  ; R7=$00c3
554 
        LDH     R7,#$96  ; R7=$96c3
555 
        XNORH   R7,#$69  ; R7=$00c3
556 
        BMI     _FAIL2   ; Negative Flag should be clear
557 
        BNE     _FAIL2   ; Zero Flag should be set
558 
        BVS     _FAIL2   ; Overflow Flag should be clear
559 
        BCC     _FAIL2   ; Carry Flag should be set
560 
        LDL     R3,#$c3  ; R3=$00c3
561 
        LDH     R3,#$00  ; R3=$00c3
562 
        SUB     R0,R7,R3 ; Compare R7 to R3
563 
        BNE     _FAIL2
564 16 rehayes 
        LDL     R2,#$06
565 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=1, Carry=0
566 
        LDL     R6,#$66  ; R6=$0066
567 
        LDH     R6,#$66  ; R6=$6666
568 
        XNORH   R6,#$66  ; R6=$ff66
569 
        BPL     _FAIL2   ; Negative Flag should be set
570 
        BEQ     _FAIL2   ; Zero Flag should be clear
571 
        BVS     _FAIL2   ; Overflow Flag should be clear
572 
        BCS     _FAIL2   ; Carry Flag should be clear
573 
        LDL     R3,#$66  ; R3=$0066
574 
        LDH     R3,#$ff  ; R3=$ff66
575 
        SUB     R0,R6,R3 ; Compare R6 to R3
576 
        BNE     _FAIL2
577 16 rehayes 
 
578 
 
579 89 rehayes 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
580 
        LDH     R2,#$80
581 
        LDL     R3,#$04
582 
        STB     R3,(R2,#0)
583 16 rehayes 
 
584 89 rehayes 
        SIF
585 
        RTS
586 
 
587 16 rehayes 
_FAIL2
588 89 rehayes 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
589 
        LDH     R2,#$80
590 
        LDL     R3,#$04
591 
        STB     R3,(R2,#0)
592 16 rehayes 
 
593 
        SIF
594 89 rehayes 
        RTS
595 16 rehayes 
 
596 
;-------------------------------------------------------------------------------
597 
;   Test Logical Word Wide instructions
598 
;-------------------------------------------------------------------------------
599 
_START3
600 89 rehayes 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
601 
        LDH     R2,#$80
602 
        LDL     R3,#$05    ; Checkpoint Value
603 
        STB     R3,(R2,#0)
604 
        LDL     R3,#$03    ; Thread Value
605 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
606 16 rehayes 
 
607 89 rehayes 
       ;Test SEX instruction ***************************************************
608 16 rehayes 
        LDL     R2,#$0b
609 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=1
610 16 rehayes 
        LDL     R3,#$00  ; R3=$0000
611 89 rehayes 
        LDH     R3,#$ff  ; R3=$ff00
612 
        SEX     R3       ; R3=$0000
613 
        BMI     _FAIL3   ; Negative Flag should be clear
614 
        BNE     _FAIL3   ; Zero Flag should be set
615 
        BVS     _FAIL3   ; Overflow Flag should be clear
616 
        BCC     _FAIL3   ; Carry Flag should be set
617 
        LDL     R6,#$00  ; R6=$0000
618 
        LDH     R6,#$00  ; R6=$0000
619 
        SUB     R0,R6,R3 ; Compare R6 to R3
620 
        BNE     _FAIL3
621 16 rehayes 
        LDL     R2,#$06
622 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=1, Carry=0
623 
        LDL     R6,#$83  ; R6=$0083
624 
        LDH     R6,#$00  ; R6=$0083
625 
        SEX     R6       ; R6=$ff83
626 
        BPL     _FAIL3   ; Negative Flag should be set
627 
        BEQ     _FAIL3   ; Zero Flag should be clear
628 
        BVS     _FAIL3   ; Overflow Flag should be clear
629 
        BCS     _FAIL3   ; Carry Flag should be clear
630 
        LDL     R3,#$83  ; R3=$0083
631 
        LDH     R3,#$ff  ; R3=$ff83
632 
        SUB     R0,R6,R3 ; Compare R6 to R3
633 
        BNE     _FAIL3
634 16 rehayes 
 
635 89 rehayes 
       ;Test PAR instruction ***************************************************
636 16 rehayes 
        LDL     R2,#$0a
637 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=0
638 16 rehayes 
        LDL     R4,#$00  ; R4=$0000
639 89 rehayes 
        LDH     R4,#$00  ; R4=$0000
640 
        PAR     R4       ; R4=$0000
641 
        BMI     _FAIL3   ; Negative Flag should be clear
642 
        BNE     _FAIL3   ; Zero Flag should be set
643 
        BVS     _FAIL3   ; Overflow Flag should be clear
644 
        BCS     _FAIL3   ; Carry Flag should be clear
645 
        LDL     R6,#$00  ; R6=$0000
646 
        LDH     R6,#$00  ; R6=$0000
647 
        SUB     R0,R6,R4 ; Compare R6 to R4
648 
        BNE     _FAIL3
649 16 rehayes 
        LDL     R2,#$0e
650 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=1, Overflow=1, Carry=0
651 
        LDL     R6,#$01  ; R6=$0001
652 
        LDH     R6,#$03  ; R6=$0301
653 
        PAR     R6       ; R6=$0301
654 
        BMI     _FAIL3   ; Negative Flag should be clear
655 
        BEQ     _FAIL3   ; Zero Flag should be clear
656 
        BVS     _FAIL3   ; Overflow Flag should be clear
657 
        BCC     _FAIL3   ; Carry Flag should be set
658 
        LDL     R3,#$01  ; R3=$0001
659 
        LDH     R3,#$03  ; R3=$0301
660 
        SUB     R0,R6,R3 ; Compare R6 to R3
661 
        BNE     _FAIL3
662 16 rehayes 
 
663 89 rehayes 
       ;Test AND instruction ***************************************************
664 16 rehayes 
        LDL     R2,#$0a
665 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=0
666 
        LDL     R6,#$55  ; R6=$0055
667 
        LDH     R6,#$aa  ; R6=$aa55
668 
        LDL     R5,#$aa  ; R5=$00aa
669 
        LDH     R5,#$55  ; R5=$55aa
670 
        AND     R3,R5,R6 ; R3=$0000
671 
        BMI     _FAIL3   ; Negative Flag should be clear
672 
        BNE     _FAIL3   ; Zero Flag should be set
673 
        BVS     _FAIL3   ; Overflow Flag should be clear
674 
        BCS     _FAIL3   ; Carry Flag should be clear
675 
        SUB     R0,R0,R3 ; Compare R0 to R3
676 
        BNE     _FAIL3
677 
        LDL     R7,#$55  ; R7=$00c5
678 
        LDH     R7,#$aa  ; R7=$aa55
679 16 rehayes 
        LDL     R2,#$07
680 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=1, Carry=1
681 
        AND     R4,R6,R7 ; R4=$aa55
682 
        BPL     _FAIL3   ; Negative Flag should be set
683 
        BEQ     _FAIL3   ; Zero Flag should be clear
684 
        BVS     _FAIL3   ; Overflow Flag should be clear
685 
        BCC     _FAIL3   ; Carry Flag should be set
686 
        SUB     R0,R4,R7 ; Compare R4 to R7
687 
        BNE     _FAIL2
688 16 rehayes 
 
689 89 rehayes 
       ;Test OR instruction ****************************************************
690 16 rehayes 
        LDL     R2,#$0a
691 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=0
692 
        LDL     R6,#$00  ; R6=$0000
693 
        LDL     R5,#$00  ; R5=$0000
694 
        OR      R3,R5,R6 ; R3=$0000
695 
        BMI     _FAIL3   ; Negative Flag should be clear
696 
        BNE     _FAIL3   ; Zero Flag should be set
697 
        BVS     _FAIL3   ; Overflow Flag should be clear
698 
        BCS     _FAIL3   ; Carry Flag should be clear
699 
        SUB     R0,R0,R3 ; Compare R0 to R3
700 
        BNE     _FAIL3
701 
        LDL     R7,#$55  ; R7=$00c5
702 
        LDH     R7,#$aa  ; R7=$aa55
703 16 rehayes 
        LDL     R6,#$8a  ; R6=$008a
704 89 rehayes 
        LDH     R6,#$10  ; R7=$108a
705 16 rehayes 
        LDL     R2,#$07
706 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=1, Carry=1
707 
        OR      R4,R6,R7 ; R4=$badf
708 
        BPL     _FAIL3   ; Negative Flag should be set
709 
        BEQ     _FAIL3   ; Zero Flag should be clear
710 
        BVS     _FAIL3   ; Overflow Flag should be clear
711 
        BCC     _FAIL3   ; Carry Flag should be set
712 
        LDL     R3,#$df  ; R3=$00df
713 
        LDH     R3,#$ba  ; R3=$badf
714 
        SUB     R0,R4,R3 ; Compare R6 to R3
715 
        BNE     _FAIL3
716 16 rehayes 
 
717 89 rehayes 
       ;Test XNOR instruction **************************************************
718 16 rehayes 
        LDL     R2,#$0a
719 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=0
720 
        LDL     R1,#$55  ; R1=$0055
721 
        LDH     R1,#$aa  ; R1=$aa55
722 
        LDL     R5,#$aa  ; R5=$00aa
723 
        LDH     R5,#$55  ; R5=$55aa
724 
        XNOR    R3,R5,R1 ; R3=$0000
725 
        BMI     _FAIL3   ; Negative Flag should be clear
726 
        BNE     _FAIL3   ; Zero Flag should be set
727 
        BVS     _FAIL3   ; Overflow Flag should be clear
728 
        BCS     _FAIL3   ; Carry Flag should be clear
729 
        SUB     R0,R0,R3 ; Compare R0 to R3
730 
        BNE     _FAIL3
731 
        LDL     R7,#$cc  ; R7=$00cc
732 
        LDH     R7,#$33  ; R7=$33cc
733 16 rehayes 
        LDL     R2,#$01  ; R2=$0001
734 89 rehayes 
        LDH     R2,#$40  ; R2=$4001
735 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=1, Carry=1
736 
        XNOR    R4,R7,R2 ; R4=$8c32
737 
        BPL     _FAIL3   ; Negative Flag should be set
738 
        BEQ     _FAIL3   ; Zero Flag should be clear
739 
        BVS     _FAIL3   ; Overflow Flag should be clear
740 
        BCC     _FAIL3   ; Carry Flag should be set
741 
        LDL     R3,#$32  ; R3=$0032
742 
        LDH     R3,#$8c  ; R3=$8c32
743 
        SUB     R0,R4,R3 ; Compare R4 to R3
744 
        BNE     _FAIL3
745 16 rehayes 
 
746 89 rehayes 
 
747 
       ;Test TFR instruction ***************************************************
748 
        MOV     R1,R0
749 
        COM     R1
750 
        TFR     CCR,R1   ; Negative=1, Zero=1, Overflow=1, Carry=1
751 
        TFR     R5,CCR   ; R5=$000f
752 
        LDL     R6,#$0f  ; R6=$xx0f
753 
        LDH     R6,#$00  ; R5=$000f
754 
        CMP     R5,R6
755 
        BNE     _FAIL3
756 
 
757 
 
758 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
759 
        LDH     R2,#$80
760 
        LDL     R3,#$06
761 
        STB     R3,(R2,#0)
762 
 
763 
        NOP
764 
        SIF
765 
        RTS
766 
 
767 16 rehayes 
_FAIL3
768 89 rehayes 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
769 
        LDH     R2,#$80
770 
        LDL     R3,#$06
771 
        STB     R3,(R2,#0)
772 16 rehayes 
 
773 
        SIF
774 89 rehayes 
        RTS
775 16 rehayes 
 
776 
 
777 
;-------------------------------------------------------------------------------
778 
;   Test Bit Field instructions
779 
;-------------------------------------------------------------------------------
780 
_START4
781 89 rehayes 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
782 
        LDH     R2,#$80
783 
        LDL     R3,#$07    ; Checkpoint Value
784 
        STB     R3,(R2,#0)
785 
        LDL     R3,#$04    ; Thread Value
786 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
787 16 rehayes 
 
788 89 rehayes 
       ;Test BFEXT instruction *************************************************
789 16 rehayes 
        LDL     R2,#$0e
790 89 rehayes 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=1, Carry=0
791 
        LDL     R6,#$34    ; Set offset to 4 and width to 3(4 bits)
792 
        LDL     R5,#$a6    ; Set R5=$00a6
793 
        LDH     R5,#$c3    ; Set R5=$c3a6
794 
        LDL     R4,#$ff    ; Set R4=$00ff
795 
        SEX     R4         ; Set R4=$ffff
796 
        BFEXT   R4,R5,R6   ; R4=$000a
797 
        BMI     _FAIL4     ; Negative Flag should be clear
798 
        BEQ     _FAIL4     ; Zero Flag should be clear
799 
        BVS     _FAIL4     ; Overflow Flag should be clear
800 
        BCS     _FAIL4     ; Carry Flag should be clear
801 
        LDL     R7,#$0a    ; R7=$00cc
802 
        SUB     R0,R7,R4 ; Compare R7 to R4
803 
        BNE     _FAIL4
804 16 rehayes 
 
805 89 rehayes 
        LDL     R6,#$b8    ; Set offset to 8 and width to 11(12 bits)
806 
        BFEXT   R4,R5,R6   ; R4=$00c3
807 
        LDL     R7,#$c3    ; R7=$00c3
808 
        SUB     R0,R7,R4 ; Compare R7 to R4
809 
        BNE     _FAIL4
810 16 rehayes 
 
811 89 rehayes 
       ;Test BFINS instruction *************************************************
812 16 rehayes 
        LDL     R2,#$06
813 89 rehayes 
        TFR     CCR,R2     ; Negative=0, Zero=1, Overflow=1, Carry=0
814 
        LDL     R6,#$34    ; Set offset to 4 and width to 3(4 bits)
815 
        LDL     R5,#$a6    ; Set R5=$00a6
816 
        LDH     R5,#$c3    ; Set R5=$c3a6
817 
        LDL     R4,#$ff    ; Set R4=$00ff
818 
        SEX     R4         ; Set R4=$ffff
819 
        BFINS   R4,R5,R6   ; R4=$ffaf
820 
        BPL     _FAIL4     ; Negative Flag should be set
821 
        BEQ     _FAIL4     ; Zero Flag should be clear
822 
        BVS     _FAIL4     ; Overflow Flag should be clear
823 
        BCS     _FAIL4     ; Carry Flag should be clear
824 
        LDL     R7,#$6f    ; R7=$006f
825 
        LDH     R7,#$ff    ; R7=$ff6f
826 
        SUB     R0,R7,R4 ; Compare R7 to R4
827 
        BNE     _FAIL4
828 16 rehayes 
 
829 89 rehayes 
        LDL     R6,#$b0    ; Set offset to 0 and width to 11(12 bits)
830 
        BFINS   R4,R5,R6   ; R4=$f3a6
831 
        LDL     R7,#$a6    ; R7=$00a6
832 
        LDH     R7,#$f3    ; R7=$f3a6
833 
        SUB     R0,R7,R4 ; Compare R7 to R4
834 
        BNE     _FAIL4
835 16 rehayes 
 
836 89 rehayes 
       ;Test BFINSI instruction ************************************************
837 16 rehayes 
        LDL     R2,#$06
838 89 rehayes 
        TFR     CCR,R2     ; Negative=0, Zero=1, Overflow=1, Carry=0
839 
        LDL     R6,#$3c    ; Set offset to 12 and width to 3(4 bits)
840 
        LDL     R5,#$a6    ; Set R5=$00a6
841 
        LDH     R5,#$c3    ; Set R5=$c3a6
842 
        LDL     R4,#$ff    ; Set R4=$00ff
843 
        SEX     R4         ; Set R4=$ffff
844 
        BFINSI  R4,R5,R6   ; R4=$9fff
845 
        BPL     _FAIL4     ; Negative Flag should be set
846 
        BEQ     _FAIL4     ; Zero Flag should be clear
847 
        BVS     _FAIL4     ; Overflow Flag should be clear
848 
        BCS     _FAIL4     ; Carry Flag should be clear
849 
        LDL     R7,#$ff    ; R7=$00ff
850 
        LDH     R7,#$9f    ; R7=$ff6f
851 
        SUB     R0,R7,R4 ; Compare R7 to R4
852 
        BNE     _FAIL4
853 16 rehayes 
 
854 89 rehayes 
        LDL     R6,#$78    ; Set offset to 8 and width to 7(8 bits)
855 
        BFINSI  R4,R5,R6   ; R4=$59ff
856 
        LDL     R7,#$ff    ; R7=$00ff
857 
        LDH     R7,#$59    ; R7=$59ff
858 
        SUB     R0,R7,R4 ; Compare R7 to R4
859 
        BNE     _FAIL4
860 16 rehayes 
 
861 89 rehayes 
       ;Test BFINSX instruction ************************************************
862 16 rehayes 
        LDL     R2,#$06
863 89 rehayes 
        TFR     CCR,R2     ; Negative=0, Zero=1, Overflow=1, Carry=0
864 
        LDL     R6,#$38    ; Set offset to 8 and width to 3(4 bits)
865 
        LDL     R5,#$a6    ; Set R5=$00a6
866 
        LDH     R5,#$c3    ; Set R5=$c3a6
867 
        LDL     R4,#$ff    ; Set R4=$00ff
868 
        LDH     R4,#$fa    ; Set R4=$faff
869 
        BFINSX  R4,R5,R6   ; R4=$f3ff
870 
        BPL     _FAIL4     ; Negative Flag should be set
871 
        BEQ     _FAIL4     ; Zero Flag should be clear
872 
        BVS     _FAIL4     ; Overflow Flag should be clear
873 
        BCS     _FAIL4     ; Carry Flag should be clear
874 
        LDL     R7,#$ff    ; R7=$00ff
875 
        LDH     R7,#$f3    ; R7=$f3ff
876 
        SUB     R0,R7,R4   ; Compare R7 to R4
877 
        BNE     _FAIL4
878 16 rehayes 
 
879 89 rehayes 
        LDL     R6,#$70    ; Set offset to 0 and width to 7(8 bits)
880 
        BFINSX  R4,R5,R6   ; R4=$f3a6
881 
        LDL     R7,#$a6    ; R7=$00a6
882 
        LDH     R7,#$f3    ; R7=$f3a6
883 
        SUB     R0,R7,R4 ; Compare R7 to R4
884 
        BNE     _FAIL4
885 16 rehayes 
 
886 
 
887 89 rehayes 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
888 
        LDH     R2,#$80
889 
        LDL     R3,#$08
890 
        STB     R3,(R2,#0)
891 
 
892 
        NOP
893 
        SIF
894 
        RTS
895 
 
896 16 rehayes 
_FAIL4
897 89 rehayes 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
898 
        LDH     R2,#$80
899 
        LDL     R3,#$08
900 
        STB     R3,(R2,#0)
901 16 rehayes 
 
902 
        SIF
903 89 rehayes 
        RTS
904 16 rehayes 
 
905 
 
906 
;-------------------------------------------------------------------------------
907 
;   Test Branch instructions
908 
;-------------------------------------------------------------------------------
909 
_START5
910 89 rehayes 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
911 
        LDH     R2,#$80
912 
        LDL     R3,#$09    ; Checkpoint Value
913 
        STB     R3,(R2,#0)
914 
        LDL     R3,#$05    ; Thread Value
915 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
916 16 rehayes 
 
917 89 rehayes 
       ;Test BCC instruction  C = 0   ******************************************
918 16 rehayes 
        LDL     R2,#$00
919 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
920 
        BCC     _BCC_OK1 ; Take Branch
921 
        BRA     _BR_ERR
922 16 rehayes 
_BCC_OK1
923 
        LDL     R2,#$01
924 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=1
925 
        BCC     _BR_ERR  ; Don't take branch
926 16 rehayes 
 
927 
 
928 89 rehayes 
       ;Test BCS instruction  C = 1   ******************************************
929 16 rehayes 
        LDL     R2,#$01
930 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=1
931 
        BCS     _BCS_OK1 ; Take Branch
932 
        BRA     _BR_ERR
933 16 rehayes 
_BCS_OK1
934 
        LDL     R2,#$00
935 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
936 
        BCS     _BR_ERR  ; Don't take branch
937 16 rehayes 
 
938 
 
939 89 rehayes 
       ;Test BEQ instruction  Z = 1   ******************************************
940 16 rehayes 
        LDL     R2,#$04
941 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=0, Carry=0
942 
        BEQ     _BEQ_OK1 ; Take Branch
943 
        BRA     _BR_ERR
944 16 rehayes 
_BEQ_OK1
945 
        LDL     R2,#$00
946 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
947 
        BEQ     _BR_ERR  ; Don't take branch
948 16 rehayes 
 
949 
 
950 89 rehayes 
       ;Test BNE instruction  Z = 0   ******************************************
951 16 rehayes 
        LDL     R2,#$00
952 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
953 
        BNE     _BNE_OK1 ; Take Branch
954 
        BRA     _BR_ERR
955 16 rehayes 
_BNE_OK1
956 
        LDL     R2,#$04
957 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=0, Carry=0
958 
        BNE     _BR_ERR  ; Don't take branch
959 16 rehayes 
 
960 
 
961 89 rehayes 
       ;Test BPL instruction  N = 0   ******************************************
962 16 rehayes 
        LDL     R2,#$00
963 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
964 
        BPL     _BPL_OK1 ; Take Branch
965 
        BRA     _BR_ERR
966 16 rehayes 
_BPL_OK1
967 
        LDL     R2,#$08
968 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=0, Carry=0
969 
        BPL     _BR_ERR  ; Don't take branch
970 16 rehayes 
 
971 
 
972 89 rehayes 
       ;Test BMI instruction  N = 1   ******************************************
973 16 rehayes 
        LDL     R2,#$08
974 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=0, Carry=0
975 
        BMI     _BMI_OK1 ; Take Branch
976 
        BRA     _BR_ERR
977 16 rehayes 
_BMI_OK1
978 
        LDL     R2,#$00
979 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
980 
        BMI     _BR_ERR  ; Don't take branch
981 16 rehayes 
 
982 
 
983 89 rehayes 
       ;Test BVC instruction  V = 0   ******************************************
984 16 rehayes 
        LDL     R2,#$00
985 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
986 
        BVC     _BVC_OK1 ; Take Branch
987 
        BRA     _BR_ERR
988 16 rehayes 
_BVC_OK1
989 
        LDL     R2,#$02
990 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=1, Carry=0
991 
        BVC     _BR_ERR  ; Don't take branch
992 16 rehayes 
 
993 
 
994 89 rehayes 
       ;Test BVS instruction  V = 1   ******************************************
995 16 rehayes 
        LDL     R2,#$02
996 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=1, Carry=0
997 
        BVS     _BVS_OK1 ; Take Branch
998 
        BRA     _BR_ERR
999 16 rehayes 
_BVS_OK1
1000 
        LDL     R2,#$00
1001 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
1002 
        BVS     _BR_ERR  ; Don't take branch
1003 16 rehayes 
 
1004 
 
1005 89 rehayes 
       ;Test BLS instruction  C | Z = 1   **************************************
1006 16 rehayes 
        LDL     R2,#$01
1007 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=1
1008 
        BLS     _BLS_OK1 ; Take Branch
1009 
        BRA     _BR_ERR
1010 16 rehayes 
_BLS_OK1
1011 
        LDL     R2,#$04
1012 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=0, Carry=0
1013 
        BLS     _BLS_OK2 ; Take Branch
1014 
        BRA     _BR_ERR
1015 16 rehayes 
_BLS_OK2
1016 
        LDL     R2,#$00
1017 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
1018 
        BLS     _BR_ERR  ; Don't take branch
1019 16 rehayes 
 
1020 
 
1021 89 rehayes 
       ;Test BGE instruction  N ^ V = 0   **************************************
1022 16 rehayes 
        LDL     R2,#$0a
1023 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=0
1024 
        BGE     _BGE_OK1 ; Take Branch
1025 
        BRA     _BR_ERR
1026 16 rehayes 
_BGE_OK1
1027 
        LDL     R2,#$05
1028 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=0, Carry=1
1029 
        BGE     _BGE_OK2 ; Take Branch
1030 
        BRA     _BR_ERR
1031 16 rehayes 
_BGE_OK2
1032 
        LDL     R2,#$08
1033 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=0, Carry=0
1034 
        BGE     _BR_ERR  ; Don't take branch
1035 16 rehayes 
 
1036 
 
1037 89 rehayes 
       ;Test BLT instruction  N ^ V = 1   **************************************
1038 
        LDL     R2,#$08
1039 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=0
1040 
        BLT     _BLT_OK1 ; Take Branch
1041 
        BRA     _BR_ERR
1042 
_BLT_OK1
1043 
        LDL     R2,#$02
1044 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=0, Carry=1
1045 
        BLT     _BLT_OK2 ; Take Branch
1046 
        BRA     _BR_ERR
1047 
_BLT_OK2
1048 16 rehayes 
        LDL     R2,#$0a
1049 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=0
1050 
        BLT     _BR_ERR  ; Don't take branch
1051 
 
1052 
        LDL     R2,#$00
1053 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
1054 
        BLT     _BR_ERR  ; Don't take branch
1055 
 
1056 
 
1057 
       ;Test BHI instruction  Z | C = 0   **************************************
1058 
        LDL     R2,#$0a
1059 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=0
1060 
        BHI     _BHI_OK1 ; Take Branch
1061 
        BRA     _BR_ERR
1062 16 rehayes 
_BHI_OK1
1063 
        LDL     R2,#$0b
1064 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=1
1065 
        BHI     _BR_ERR  ; Don't take branch
1066 16 rehayes 
 
1067 
        LDL     R2,#$0e
1068 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=1, Overflow=1, Carry=0
1069 
        BHI     _BR_ERR  ; Don't take branch
1070 16 rehayes 
 
1071 
 
1072 89 rehayes 
       ;Test BGT instruction  Z | (N ^ V) = 0   ********************************
1073 16 rehayes 
        LDL     R2,#$0a
1074 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=0
1075 
        BGT     _BGT_OK1 ; Take Branch
1076 
        BRA     _BR_ERR
1077 16 rehayes 
_BGT_OK1
1078 
        LDL     R2,#$01
1079 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=1
1080 
        BGT     _BGT_OK2 ; Take Branch
1081 
        BRA     _BR_ERR
1082 16 rehayes 
_BGT_OK2
1083 
        LDL     R2,#$0e
1084 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=1, Overflow=1, Carry=0
1085 
        BGT     _BR_ERR  ; Don't take branch
1086 16 rehayes 
 
1087 
        LDL     R2,#$02
1088 89 rehayes 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=1, Carry=0
1089 
        BGT     _BR_ERR  ; Don't take branch
1090 16 rehayes 
 
1091 
        LDL     R2,#$08
1092 89 rehayes 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=0, Carry=0
1093 
        BGT     _BR_ERR  ; Don't take branch
1094 16 rehayes 
 
1095 
 
1096 89 rehayes 
       ;Test BLE instruction  Z | (N ^ V) = 1   ********************************
1097 
        LDL     R2,#$04
1098 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=0, Carry=0
1099 
        BLE     _BLE_OK1 ; Take Branch
1100 
        BRA     _BR_ERR
1101 
_BLE_OK1
1102 
        LDL     R2,#$02
1103 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=1, Carry=0
1104 
        BLE     _BLE_OK2 ; Take Branch
1105 
        BRA     _BR_ERR
1106 
_BLE_OK2
1107 
        LDL     R2,#$08
1108 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=0, Carry=0
1109 
        BLE     _BLE_OK3 ; Take Branch
1110 
        BRA     _BR_ERR
1111 
_BLE_OK3
1112 
        LDL     R2,#$0a
1113 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=0
1114 
        BLE     _BR_ERR  ; Don't take branch
1115 16 rehayes 
 
1116 89 rehayes 
        LDL     R2,#$00
1117 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
1118 
        BLE     _BR_ERR  ; Don't take branch
1119 16 rehayes 
 
1120 89 rehayes 
 
1121 
       ;Test BRA instruction  **************************************************
1122 
        BRA     BRA_FWARD
1123 
 
1124 
 
1125 16 rehayes 
_BR_ERR
1126 89 rehayes 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
1127 
        LDH     R2,#$80
1128 
        LDL     R3,#$0a
1129 
        STB     R3,(R2,#0)
1130 16 rehayes 
 
1131 
        SIF
1132 89 rehayes 
        RTS
1133 16 rehayes 
 
1134 89 rehayes 
_BRA_OK
1135 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1136 
        LDH     R2,#$80
1137 
        LDL     R3,#$0a
1138 
        STB     R3,(R2,#0)
1139 16 rehayes 
 
1140 89 rehayes 
        SIF
1141 
        RTS
1142 
 
1143 16 rehayes 
BRA_FWARD
1144 89 rehayes 
        BRA     _BRA_OK    ; Test backward branch caculation
1145 16 rehayes 
 
1146 89 rehayes 
 
1147 16 rehayes 
;-------------------------------------------------------------------------------
1148 
;   Test Subroutine Call and return instructions
1149 
;-------------------------------------------------------------------------------
1150 
_START6
1151 89 rehayes 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1152 
        LDH     R2,#$80
1153 
        LDL     R3,#$0b    ; Checkpoint Value
1154 
        STB     R3,(R2,#0)
1155 
        LDL     R3,#$06    ; Thread Value
1156 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
1157 16 rehayes 
 
1158 89 rehayes 
        LDL     R4,#$00
1159 
        TFR     R5,PC      ; Subroutine Call
1160 
        BRA     SUB_TST
1161 16 rehayes 
 
1162 
RET_SUB
1163 89 rehayes 
 
1164 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1165 
        LDH     R2,#$80
1166 
        LDL     R3,#$0c
1167 
        STB     R3,(R2,#0)
1168 
 
1169 
        SIF
1170 
        RTS
1171 
 
1172 16 rehayes 
_FAIL6
1173 89 rehayes 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
1174 
        LDH     R2,#$80
1175 
        LDL     R3,#$0c
1176 
        STB     R3,(R2,#0)
1177 
 
1178 16 rehayes 
        SIF
1179 89 rehayes 
        RTS
1180 
 
1181 16 rehayes 
SUB_TST
1182 89 rehayes 
        LDL     R4,#$88    ; If we branch to far then the wrong data will get loaded
1183 
        LDH     R4,#$99    ;  and we'll make a bad compare to cause test to fail
1184 
        LDL     R7,#$88    ; R7=$0088
1185 
        LDH     R7,#$99    ; R7=$9988
1186 
        SUB     R0,R7,R4   ; Compare R7 to R4
1187 
        BNE     _FAIL6
1188 
        JAL     R5         ; Jump to return address
1189 16 rehayes 
 
1190 
;-------------------------------------------------------------------------------
1191 
;   Test 16 bit Addition and Substract instructions
1192 
;-------------------------------------------------------------------------------
1193 
_START7
1194 89 rehayes 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1195 
        LDH     R2,#$80
1196 
        LDL     R3,#$0d    ; Checkpoint Value
1197 
        STB     R3,(R2,#0)
1198 
        LDL     R3,#$07    ; Thread Value
1199 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
1200 16 rehayes 
 
1201 89 rehayes 
       ;Test SUB instruction ***************************************************
1202 
        LDL     R4,#$0f    ; R4=$000f
1203 
        LDH     R4,#$01    ; R4=$010f
1204 
        LDL     R7,#$0e    ; R7=$000e
1205 
        LDH     R7,#$01    ; R7=$010e
1206 16 rehayes 
        LDL     R2,#$0f
1207 89 rehayes 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=1, Carry=1
1208 
        SUB     R1,R4,R7   ; R4 - R7 => R1
1209 
        BMI     _FAIL7     ; Negative Flag should be clear
1210 
        BEQ     _FAIL7     ; Zero Flag should be clear
1211 
        BVS     _FAIL7     ; Overflow Flag should be clear
1212 
        BCS     _FAIL7     ; Carry Flag should be clear
1213 
        LDL     R3,#$01    ; R3=$0001
1214 
        SUB     R0,R1,R3   ; Compare R1 to R3
1215 
        BNE     _FAIL7
1216 16 rehayes 
 
1217 89 rehayes 
        LDL     R7,#$0f    ; R7=$000f
1218 
        LDH     R7,#$01    ; R7=$010f
1219 16 rehayes 
        LDL     R2,#$0b
1220 89 rehayes 
        TFR     CCR,R2     ; Negative=1, Zero=0, Overflow=1, Carry=1
1221 
        SUB     R1,R4,R7   ; R4 - R7 => R1
1222 
        BMI     _FAIL7     ; Negative Flag should be clear
1223 
        BNE     _FAIL7     ; Zero Flag should be set
1224 
        BVS     _FAIL7     ; Overflow Flag should be clear
1225 
        BCS     _FAIL7     ; Carry Flag should be clear
1226 16 rehayes 
 
1227 
 
1228 89 rehayes 
       ;Test SBC instruction ***************************************************
1229 
        LDL     R4,#$11    ; R4=$0011
1230 
        LDH     R4,#$01    ; R4=$0111
1231 
        LDL     R7,#$0e    ; R7=$000e
1232 
        LDH     R7,#$01    ; R7=$010e
1233 16 rehayes 
        LDL     R2,#$0f
1234 89 rehayes 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=1, Carry=1
1235 
        SBC     R1,R4,R7   ; R4 - R7 => R1
1236 
        BMI     _FAIL7     ; Negative Flag should be clear
1237 
        BEQ     _FAIL7     ; Zero Flag should be clear
1238 
        BVS     _FAIL7     ; Overflow Flag should be clear
1239 
        BCS     _FAIL7     ; Carry Flag should be clear
1240 
        LDL     R3,#$02    ; R3=$0002
1241 
        SUB     R0,R1,R3   ; Compare R1 to R3
1242 
        BNE     _FAIL7
1243 16 rehayes 
 
1244 89 rehayes 
        LDL     R4,#$0f    ; R4=$000f
1245 
        LDH     R4,#$01    ; R4=$010f
1246 
        LDL     R7,#$0f    ; R7=$000f
1247 
        LDH     R7,#$01    ; R7=$010f
1248 16 rehayes 
        LDL     R2,#$0a
1249 89 rehayes 
        TFR     CCR,R2     ; Negative=1, Zero=0, Overflow=1, Carry=0
1250 
        SBC     R1,R4,R7   ; R4 - R7 => R1
1251 
        BMI     _FAIL7     ; Negative Flag should be clear
1252 
        BEQ     _FAIL7     ; Zero Flag should be clear
1253 
        BVS     _FAIL7     ; Overflow Flag should be clear
1254 
        BCS     _FAIL7     ; Carry Flag should be clear
1255 16 rehayes 
 
1256 
 
1257 89 rehayes 
       ;Test ADD instruction ***************************************************
1258 
        LDL     R4,#$0f    ; R4=$000f
1259 
        LDH     R4,#$70    ; R4=$700f
1260 
        LDL     R7,#$01    ; R7=$0001
1261 
        LDH     R7,#$10    ; R7=$1001
1262 16 rehayes 
        LDL     R2,#$05
1263 89 rehayes 
        TFR     CCR,R2     ; Negative=0, Zero=1, Overflow=0, Carry=1
1264 
        ADD     R1,R4,R7   ; R4 + R7 => R1
1265 
        BPL     _FAIL7     ; Negative Flag should be set
1266 
        BEQ     _FAIL7     ; Zero Flag should be clear
1267 
        BVC     _FAIL7     ; Overflow Flag should be set
1268 
        BCS     _FAIL7     ; Carry Flag should be clear
1269 
        LDL     R3,#$10    ; R3=$0010
1270 
        LDH     R3,#$80    ; R3=$8010
1271 
        SUB     R0,R1,R3   ; Compare R1 to R3
1272 
        BNE     _FAIL7
1273 16 rehayes 
 
1274 89 rehayes 
        LDL     R4,#$00    ; R4=$0000
1275 
        LDH     R4,#$80    ; R4=$8000
1276 
        LDL     R7,#$00    ; R7=$0000
1277 
        LDH     R7,#$80    ; R7=$8000
1278 16 rehayes 
        LDL     R2,#$0f
1279 89 rehayes 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=0, Carry=0
1280 
        ADD     R1,R4,R7   ; R4 + R7 => R1
1281 
        BMI     _FAIL7     ; Negative Flag should be clear
1282 
        BNE     _FAIL7     ; Zero Flag should be set
1283 
        BVC     _FAIL7     ; Overflow Flag should be set
1284 
        BCC     _FAIL7     ; Carry Flag should be set
1285 
        SUB     R0,R1,R0   ; Compare R1 to R0(Zero)
1286 
        BNE     _FAIL7
1287 16 rehayes 
 
1288 
 
1289 89 rehayes 
       ;Test ADC instruction ***************************************************
1290 
        LDL     R4,#$0f    ; R4=$000f
1291 
        LDH     R4,#$70    ; R4=$700f
1292 
        LDL     R7,#$01    ; R7=$0001
1293 
        LDH     R7,#$10    ; R7=$1001
1294 16 rehayes 
        LDL     R2,#$05
1295 89 rehayes 
        TFR     CCR,R2     ; Negative=0, Zero=1, Overflow=0, Carry=1
1296 
        ADC     R1,R4,R7   ; R4 + R7 => R1
1297 
        BPL     _FAIL7     ; Negative Flag should be set
1298 
        BEQ     _FAIL7     ; Zero Flag should be clear
1299 
        BVC     _FAIL7     ; Overflow Flag should be set
1300 
        BCS     _FAIL7     ; Carry Flag should be clear
1301 
        LDL     R3,#$11    ; R3=$0011
1302 
        LDH     R3,#$80    ; R3=$8011
1303 
        SUB     R0,R1,R3   ; Compare R1 to R3
1304 
        BNE     _FAIL7
1305 16 rehayes 
 
1306 89 rehayes 
        LDL     R4,#$00    ; R4=$0000
1307 
        LDH     R4,#$80    ; R4=$8000
1308 
        LDL     R7,#$00    ; R7=$0000
1309 
        LDH     R7,#$80    ; R7=$8000
1310 16 rehayes 
        LDL     R2,#$0c
1311 89 rehayes 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=0, Carry=0
1312 
        ADC     R1,R4,R7   ; R4 + R7 => R1
1313 
        BMI     _FAIL7     ; Negative Flag should be clear
1314 
        BNE     _FAIL7     ; Zero Flag should be set
1315 
        BVC     _FAIL7     ; Overflow Flag should be set
1316 
        BCC     _FAIL7     ; Carry Flag should be set
1317 
        SUB     R0,R1,R0   ; Compare R1 to R0(Zero)
1318 
        BNE     _FAIL7
1319 16 rehayes 
 
1320 
 
1321 89 rehayes 
_END_7
1322 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1323 
        LDH     R2,#$80
1324 
        LDL     R3,#$0e
1325 
        STB     R3,(R2,#0)
1326 
 
1327 
        SIF
1328 
        RTS
1329 
 
1330 16 rehayes 
_FAIL7
1331 89 rehayes 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
1332 
        LDH     R2,#$80
1333 
        LDL     R3,#$0e
1334 
        STB     R3,(R2,#0)
1335 16 rehayes 
 
1336 
        SIF
1337 89 rehayes 
        RTS
1338 
 
1339 16 rehayes 
;-------------------------------------------------------------------------------
1340 
;   Test 8 bit Addition and Substract instructions
1341 
;-------------------------------------------------------------------------------
1342 
_START8
1343 89 rehayes 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1344 
        LDH     R2,#$80
1345 
        LDL     R3,#$0f    ; Checkpoint Value
1346 
        STB     R3,(R2,#0)
1347 
        LDL     R3,#$08    ; Thread Value
1348 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
1349 16 rehayes 
 
1350 89 rehayes 
       ;Test SUBL instruction **************************************************
1351 
        LDL     R5,#$0f    ; R5=$000f
1352 16 rehayes 
        LDL     R2,#$0f
1353 89 rehayes 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=1, Carry=1
1354 
        SUBL    R5,#$0e    ; R5 - $0e => R5
1355 
        BMI     _FAIL8     ; Negative Flag should be clear
1356 
        BEQ     _FAIL8     ; Zero Flag should be clear
1357 
        BVS     _FAIL8     ; Overflow Flag should be clear
1358 
        BCS     _FAIL8     ; Carry Flag should be clear
1359 
        LDL     R3,#$01    ; R3=$0001
1360 
        SUB     R0,R5,R3   ; Compare R5 to R3
1361 
        BNE     _FAIL8
1362 16 rehayes 
 
1363 89 rehayes 
        LDL     R7,#$0f    ; R7=$000f
1364 16 rehayes 
        LDL     R2,#$0d
1365 89 rehayes 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=1, Carry=0
1366 
        SUBL    R7,#$10    ; R7 - $10 => R7
1367 
        BPL     _FAIL8     ; Negative Flag should be set
1368 
        BEQ     _FAIL8     ; Zero Flag should be clear
1369 
        BVS     _FAIL8     ; Overflow Flag should be clear
1370 
        BCC     _FAIL8     ; Carry Flag should be set
1371 
        CMPL    R7,#$FF    ; Result should be -1 or $FFFF
1372 
        CPCH    R7,#$FF
1373 
        BNE     _FAIL8
1374 16 rehayes 
 
1375 89 rehayes 
       ;Test SUBH instruction **************************************************
1376 
        LDL     R6,#$11    ; R4=$0011
1377 
        LDH     R6,#$81    ; R4=$8111
1378 16 rehayes 
        LDL     R2,#$0d
1379 89 rehayes 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=0, Carry=1
1380 
        SUBH    R6,#$70    ; R6 - $70 => R6
1381 
        BMI     _FAIL8     ; Negative Flag should be clear
1382 
        BEQ     _FAIL8     ; Zero Flag should be clear
1383 
        BVC     _FAIL8     ; Overflow Flag should be set
1384 
        BCS     _FAIL8     ; Carry Flag should be clear
1385 
        LDL     R3,#$11    ; R3=$0011
1386 
        LDH     R3,#$11    ; R3=$1111
1387 
        SUB     R0,R6,R3   ; Compare R6 to R3
1388 
        BNE     _FAIL8
1389 16 rehayes 
 
1390 89 rehayes 
        LDL     R6,#$00    ; R6=$0000
1391 
        LDH     R6,#$01    ; R6=$0100
1392 16 rehayes 
        LDL     R2,#$06
1393 89 rehayes 
        TFR     CCR,R2     ; Negative=0, Zero=1, Overflow=1, Carry=0
1394 
        SUBH    R6,#$02    ; R6 - $70 => R6
1395 
        BPL     _FAIL8     ; Negative Flag should be set
1396 
        BEQ     _FAIL8     ; Zero Flag should be clear
1397 
        BVS     _FAIL8     ; Overflow Flag should be clear
1398 
        BCC     _FAIL8     ; Carry Flag should be set
1399 16 rehayes 
 
1400 
 
1401 89 rehayes 
       ;Test CMPL instruction **************************************************
1402 
        LDL     R5,#$0f    ; R5=$000f
1403 16 rehayes 
        LDL     R2,#$0b
1404 89 rehayes 
        TFR     CCR,R2     ; Negative=1, Zero=0, Overflow=1, Carry=1
1405 
        CMPL    R5,#$0f    ; R5 - $0f => R5
1406 
        BMI     _FAIL8     ; Negative Flag should be clear
1407 
        BNE     _FAIL8     ; Zero Flag should be set
1408 
        BVS     _FAIL8     ; Overflow Flag should be clear
1409 
        BCS     _FAIL8     ; Carry Flag should be clear
1410 16 rehayes 
 
1411 89 rehayes 
        LDL     R7,#$0f    ; R7=$000f
1412 16 rehayes 
        LDL     R2,#$07
1413 89 rehayes 
        TFR     CCR,R2     ; Negative=0, Zero=1, Overflow=1, Carry=1
1414 
        CMPL    R7,#$10    ; R7 - $10 => R7
1415 
        BPL     _FAIL8     ; Negative Flag should be set
1416 
        BEQ     _FAIL8     ; Zero Flag should be clear
1417 
        BVS     _FAIL8     ; Overflow Flag should be clear
1418 
        BCC     _FAIL8     ; Carry Flag should be set
1419 16 rehayes 
 
1420 
 
1421 89 rehayes 
       ;Test CPCH instruction **************************************************
1422 
        LDL     R5,#$00    ; R5=$0000
1423 
        LDH     R5,#$01    ; R5=$0001
1424 16 rehayes 
        LDL     R2,#$0f
1425 89 rehayes 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=1, Carry=1
1426 
        CPCH    R5,#$00    ; R5 - $00 - carryflag => nowhere
1427 
        BMI     _FAIL8     ; Negative Flag should be clear
1428 
        BNE     _FAIL8     ; Zero Flag should be set
1429 
        BVS     _FAIL8     ; Overflow Flag should be clear
1430 
        BCS     _FAIL8     ; Carry Flag should be clear
1431 16 rehayes 
        LDL     R2,#$06
1432 89 rehayes 
        TFR     CCR,R2     ; Negative=0, Zero=1, Overflow=1, Carry=0
1433 
        CPCH    R5,#$02    ; R5 - $00 - carryflag => nowhere
1434 
        BPL     _FAIL8     ; Negative Flag should be set
1435 
        BEQ     _FAIL8     ; Zero Flag should be clear
1436 
        BVS     _FAIL8     ; Overflow Flag should be clear
1437 
        BCC     _FAIL8     ; Carry Flag should be set
1438 16 rehayes 
 
1439 
 
1440 89 rehayes 
       ;Test ADDH instruction **************************************************
1441 
        LDL     R5,#$0f    ; R5=$000f
1442 
        LDH     R5,#$70    ; R5=$700f
1443 16 rehayes 
        LDL     R2,#$0e
1444 89 rehayes 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=1, Carry=0
1445 
        ADDH    R5,#$a0    ; R5 + $a0 => R5
1446 
        BMI     _FAIL8     ; Negative Flag should be clear
1447 
        BEQ     _FAIL8     ; Zero Flag should be clear
1448 
        BVS     _FAIL8     ; Overflow Flag should be clear
1449 
        BCC     _FAIL8     ; Carry Flag should be set
1450 
        LDL     R3,#$0f    ; R3=$000f
1451 
        LDH     R3,#$10    ; R3=$100f
1452 
        SUB     R0,R5,R3   ; Compare R5 to R3
1453 
        BNE     _FAIL8
1454 16 rehayes 
 
1455 
        LDL     R2,#$07
1456 89 rehayes 
        TFR     CCR,R2     ; Negative=0, Zero=1, Overflow=1, Carry=1
1457 
        ADDH    R5,#$70    ; R5 + $70 => R5
1458 
        BPL     _FAIL8     ; Negative Flag should be set
1459 
        BEQ     _FAIL8     ; Zero Flag should be clear
1460 
        BVC     _FAIL8     ; Overflow Flag should be set
1461 
        BCS     _FAIL8     ; Carry Flag should be clear
1462 
        LDL     R3,#$0f    ; R3=$000f
1463 
        LDH     R3,#$80    ; R3=$800f
1464 
        SUB     R0,R5,R3   ; Compare R5 to R3
1465 
        BNE     _FAIL8
1466 16 rehayes 
 
1467 
 
1468 89 rehayes 
       ;Test ADDL instruction **************************************************
1469 
        LDL     R4,#$ff    ; R4=$00ff
1470 
        LDH     R4,#$70    ; R4=$70ff
1471 16 rehayes 
        LDL     R2,#$0e
1472 89 rehayes 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=1, Carry=0
1473 
        ADDL    R4,#$01    ; R4 + $01 => R4
1474 
        BMI     _FAIL8     ; Negative Flag should be clear
1475 
        BEQ     _FAIL8     ; Zero Flag should be clear
1476 
        BVS     _FAIL8     ; Overflow Flag should be clear
1477 
        BCC     _FAIL8     ; Carry Flag should be set
1478 
        LDL     R5,#$00    ; R5=$0000
1479 
        LDH     R5,#$71    ; R5=$7100
1480 
        SUB     R0,R4,R5   ; Compare R4 to R5
1481 
        BNE     _FAIL8
1482 16 rehayes 
 
1483 89 rehayes 
        LDL     R4,#$8e    ; R4=$008e
1484 
        LDH     R4,#$7f    ; R4=$7f8e
1485 16 rehayes 
        LDL     R2,#$0c
1486 89 rehayes 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=0, Carry=0
1487 
        ADDL    R4,#$81    ; R4 + $81 => R4
1488 
        BPL     _FAIL8     ; Negative Flag should be set
1489 
        BEQ     _FAIL8     ; Zero Flag should be clear
1490 
        BVC     _FAIL8     ; Overflow Flag should be set
1491 
        BCC     _FAIL8     ; Carry Flag should be set
1492 
        LDL     R6,#$0f    ; R6=$000f
1493 
        LDH     R6,#$80    ; R6=$800f
1494 
        SUB     R0,R4,R6   ; Compare R4 to R6
1495 
        BNE     _FAIL8
1496 16 rehayes 
 
1497 
 
1498 89 rehayes 
_END_8
1499 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1500 
        LDH     R2,#$80
1501 
        LDL     R3,#$10
1502 
        STB     R3,(R2,#0)
1503 
 
1504 
        SIF
1505 
        RTS
1506 
 
1507 16 rehayes 
_FAIL8
1508 89 rehayes 
        LDL     R2,#$00    ; Sent Message to Testbench Error Register
1509 
        LDH     R2,#$80
1510 
        LDL     R3,#$10
1511 
        STB     R3,(R2,#4)
1512 
 
1513 16 rehayes 
        SIF
1514 89 rehayes 
        RTS
1515 16 rehayes 
 
1516 89 rehayes 
 
1517 16 rehayes 
;-------------------------------------------------------------------------------
1518 
;   Test Load and Store instructions
1519 
;-------------------------------------------------------------------------------
1520 
_START9
1521 89 rehayes 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1522 
        LDH     R2,#$80
1523 
        LDL     R3,#$11    ; Checkpoint Value
1524 
        STB     R3,(R2,#0)
1525 
        LDL     R3,#$09    ; Thread Value
1526 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
1527 16 rehayes 
 
1528 89 rehayes 
        LDL     R1,#$aa    ; R1=$00aa
1529 
        LDH     R1,#$7f    ; R1=$7faa
1530 
        LDL     R2,#$55    ; R2=$0055
1531 
        LDH     R2,#$6f    ; R2=$6f55
1532 
        LDL     R3,#$66    ; R3=$0066
1533 
        LDH     R3,#$5f    ; R3=$5f66
1534 
        LDL     R7,#$ff    ; R7=$00ff
1535 
        LDH     R7,#$ff    ; R7=$ffff
1536 16 rehayes 
 
1537 89 rehayes 
       ;Test STB/LDB instruction ***********************************************
1538 
        STB     R1,(R0,#$00)    ;
1539 
        STB     R2,(R0,#$01)    ;
1540 
        STB     R3,(R0,#$1f)    ;
1541 
        LDL     R4,#$00         ; R4=$0000
1542 
        LDB     R5,(R4,#$00)    ;
1543 
        LDB     R6,(R4,#$01)    ;
1544 
        LDB     R7,(R4,#$1f)    ;
1545 
        CMPL    R5,#$aa         ;
1546 
        BNE     _FAIL9
1547 
        CMPL    R6,#$55         ;
1548 
        BNE     _FAIL9
1549 
        CMPL    R7,#$66         ;
1550 
        BNE     _FAIL9
1551 
        LDL     R6,#$66         ; R6=$0066
1552 
        CMP     R6,R7           ; Make sure the high byte has been cleared
1553 
        BNE     _FAIL9
1554 16 rehayes 
 
1555 89 rehayes 
       ;Test STW/LDW instruction ***********************************************
1556 
        STW     R1,(R0,#$04)    ; Should be even offsets
1557 
        STW     R2,(R0,#$06)    ;
1558 
        STW     R3,(R0,#$0a)    ;
1559 
        LDL     R4,#$00         ; R4=$0000
1560 
        LDL     R5,#$00         ; R5=$0000
1561 
        LDL     R6,#$00         ; R6=$0000
1562 
        LDL     R7,#$00         ; R7=$0000
1563 
        LDW     R5,(R4,#$04)    ;
1564 
        LDW     R6,(R4,#$06)    ;
1565 
        LDW     R7,(R4,#$0a)    ;
1566 
        CMP     R1,R5           ;
1567 
        BNE     _FAIL9
1568 
        CMP     R2,R6           ;
1569 
        BNE     _FAIL9
1570 
        CMP     R3,R7           ;
1571 
        BNE     _FAIL9
1572 16 rehayes 
 
1573 89 rehayes 
       ;Test STB/LDB instruction ***********************************************
1574 
        LDL     R1,#$cc    ; R1=$00cc
1575 
        LDH     R1,#$1f    ; R1=$1f66
1576 
        LDL     R2,#$99    ; R2=$0099
1577 
        LDH     R2,#$2f    ; R2=$2f99
1578 16 rehayes 
 
1579 89 rehayes 
        LDL     R4,#$20         ; R4=$0020 - Base Address
1580 
        LDL     R5,#$02         ; R5=$0002 - even offset
1581 
        LDL     R6,#$07         ; R6=$0007 - odd offset
1582 
        STB     R1,(R4,R5)      ;
1583 
        STB     R2,(R4,R6)      ;
1584 
        LDB     R5,(R4,R5)      ;
1585 
        LDB     R6,(R4,R6)      ;
1586 
        CMPL    R5,#$cc         ;
1587 
        BNE     _FAIL9
1588 
        LDL     R3,#$99         ; R3=$0099
1589 
        CMP     R3,R6           ; Make sure the high byte has been cleared
1590 
        BNE     _FAIL9
1591 16 rehayes 
 
1592 89 rehayes 
       ;Test STW/LDW instruction ***********************************************
1593 
        LDL     R1,#$cc    ; R1=$00cc
1594 
        LDH     R1,#$1f    ; R1=$1f66
1595 
        LDL     R2,#$99    ; R2=$0099
1596 
        LDH     R2,#$2f    ; R2=$2f99
1597 16 rehayes 
 
1598 89 rehayes 
        LDL     R4,#$30         ; R3=$0030 - Base Address
1599 
        LDL     R5,#$02         ; R5=$0002
1600 
        LDL     R6,#$08         ; R6=$0008
1601 
        STW     R1,(R4,R5)      ;
1602 
        STW     R2,(R4,R6)      ;
1603 
        LDW     R5,(R4,R5)      ;
1604 
        LDW     R6,(R4,R6)      ;
1605 
        CMP     R5,R1           ;
1606 
        BNE     _FAIL9
1607 
        CMP     R6,R2           ;
1608 
        BNE     _FAIL9
1609 16 rehayes 
 
1610 89 rehayes 
       ;Test STB/LDB instruction ***********************************************
1611 
        LDL     R1,#$33    ; R1=$0033
1612 
        LDH     R1,#$1f    ; R1=$1f33
1613 
        LDL     R2,#$55    ; R2=$0055
1614 
        LDH     R2,#$2f    ; R2=$2f55
1615 16 rehayes 
 
1616 89 rehayes 
        LDL     R4,#$40         ; R4=$0040 - Base Address
1617 
        LDL     R5,#$02         ; R5=$0002 - even offset
1618 
        LDL     R6,#$07         ; R6=$0007 - odd offset
1619 
        STB     R1,(R4,R5+)     ;
1620 
        STB     R2,(R4,R6+)     ;
1621 
        CMPL    R5,#$03         ; Test for 1 byte increment
1622 
        BNE     _FAIL9
1623 
        CMPL    R6,#$08         ; Test for 1 byte increment
1624 
        BNE     _FAIL9
1625 
        LDB     R3,(R4,-R5)     ;
1626 
        LDB     R7,(R4,-R6)     ;
1627 
        CMPL    R5,#$02         ; Test for 1 byte decrement
1628 
        BNE     _FAIL9
1629 
        CMPL    R6,#$07         ; Test for 1 byte decrement
1630 
        BNE     _FAIL9
1631 
        CMPL    R3,#$33         ;
1632 
        BNE     _FAIL9
1633 
        LDL     R3,#$55         ; R3=$0055
1634 
        CMP     R3,R7           ; Make sure the high byte has been cleared
1635 
        BNE     _FAIL9
1636 16 rehayes 
 
1637 89 rehayes 
       ;Test STB/LDB instruction ***********************************************
1638 
        LDL     R1,#$66    ; R1=$0066
1639 
        LDH     R1,#$1f    ; R1=$1f66
1640 
        LDL     R2,#$99    ; R2=$0099
1641 
        LDH     R2,#$2f    ; R2=$2f99
1642 16 rehayes 
 
1643 89 rehayes 
        LDL     R4,#$50         ; R4=$0050 - Base Address
1644 
        LDL     R5,#$04         ; R5=$0004 - even offset
1645 
        LDL     R6,#$09         ; R6=$0009 - odd offset
1646 
        STB     R1,(R4,-R5)     ;
1647 
        STB     R2,(R4,-R6)     ;
1648 
        CMPL    R5,#$03         ; Test for 1 byte decrement
1649 
        BNE     _FAIL9
1650 
        CMPL    R6,#$08         ; Test for 1 byte decrement
1651 
        BNE     _FAIL9
1652 
        LDB     R3,(R4,R5+)     ;
1653 
        LDB     R7,(R4,R6+)     ;
1654 
        CMPL    R5,#$04         ; Test for 1 byte increment
1655 
        BNE     _FAIL9
1656 
        CMPL    R6,#$09         ; Test for 1 byte increment
1657 
        BNE     _FAIL9
1658 
        CMPL    R3,#$66         ;
1659 
        BNE     _FAIL9
1660 
        LDL     R3,#$99         ; R3=$0099
1661 
        CMP     R3,R7           ; Make sure the high byte has been cleared
1662 
        BNE     _FAIL9
1663 16 rehayes 
 
1664 89 rehayes 
       ;Test STW/LDW instruction ***********************************************
1665 
        LDL     R1,#$aa         ; R1=$00aa
1666 
        LDH     R1,#$1f         ; R1=$1faa
1667 
        LDL     R2,#$cc         ; R2=$00cc
1668 
        LDH     R2,#$2f         ; R2=$2fcc
1669 16 rehayes 
 
1670 89 rehayes 
        LDL     R4,#$60         ; R4=$0060 - Base Address
1671 
        LDL     R5,#$02         ; R5=$0002 - even offset
1672 
        LDL     R6,#$08         ; R6=$0008
1673 
        STW     R1,(R4,R5+)     ;
1674 
        STW     R2,(R4,R6+)     ;
1675 
        CMPL    R5,#$04         ; Test for 2 byte increment
1676 
        BNE     _FAIL9
1677 
        CMPL    R6,#$0a         ; Test for 2 byte increment
1678 
        BNE     _FAIL9
1679 
        LDW     R3,(R4,-R5)     ;
1680 
        LDW     R7,(R4,-R6)     ;
1681 
        CMPL    R5,#$02         ; Test for 2 byte decrement
1682 
        BNE     _FAIL9
1683 
        CMPL    R6,#$08         ; Test for 2 byte decrement
1684 
        BNE     _FAIL9
1685 
        CMP     R1,R3           ;
1686 
        BNE     _FAIL9
1687 
        CMP     R2,R7           ;
1688 
        BNE     _FAIL9
1689 16 rehayes 
 
1690 89 rehayes 
       ;Test STW/LDW instruction ***********************************************
1691 
        LDL     R1,#$66         ; R1=$0066
1692 
        LDH     R1,#$99         ; R1=$9966
1693 
        LDL     R2,#$33         ; R2=$0033
1694 
        LDH     R2,#$75         ; R2=$7533
1695 
 
1696 
        LDL     R4,#$80         ; R4=$0080 - Base Address
1697 
        LDL     R5,#$02         ; R5=$0002 - even offset
1698 
        LDL     R6,#$08         ; R6=$0008
1699 
        STW     R1,(R4,-R5)     ;
1700 
        STW     R2,(R4,-R6)     ;
1701 
        CMPL    R5,#$00         ; Test for 2 byte increment
1702 
        BNE     _FAIL9
1703 
        CMPL    R6,#$06         ; Test for 2 byte increment
1704 
        BNE     _FAIL9
1705 
        LDW     R3,(R4,R5+)     ;
1706 
        LDW     R7,(R4,R6+)     ;
1707 
        CMPL    R5,#$02         ; Test for 2 byte decrement
1708 
        BNE     _FAIL9
1709 
        CMPL    R6,#$08         ; Test for 2 byte decrement
1710 
        BNE     _FAIL9
1711 
        CMP     R1,R3           ;
1712 
        BNE     _FAIL9
1713 
        CMP     R2,R7           ;
1714 
        BNE     _FAIL9
1715 
 
1716 
_END_9
1717 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1718 
        LDH     R2,#$80
1719 
        LDL     R3,#$12
1720 
        STB     R3,(R2,#0)
1721 
 
1722 
        SIF
1723 
        RTS
1724 
 
1725 16 rehayes 
_FAIL9
1726 89 rehayes 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
1727 
        LDH     R2,#$80
1728 
        LDL     R3,#$12
1729 
        STB     R3,(R2,#0)
1730 
 
1731 16 rehayes 
        SIF
1732 89 rehayes 
        RTS
1733 16 rehayes 
 
1734 89 rehayes 
 
1735 16 rehayes 
;-------------------------------------------------------------------------------
1736 
;   Test Semaphore instructions
1737 
;-------------------------------------------------------------------------------
1738 
_START10
1739 89 rehayes 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1740 
        LDH     R2,#$80
1741 
        LDL     R3,#$13    ; Checkpoint Value
1742 
        STB     R3,(R2,#0)
1743 
        LDL     R3,#$0a    ; Thread Value
1744 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
1745 16 rehayes 
 
1746 89 rehayes 
        LDL     R1,#$5     ; R1=$0005
1747 16 rehayes 
 
1748 89 rehayes 
       ;Test SSEM instruction **************************************************
1749 
        SSEM    #7      ; semaphores
1750 
        BCC     _FAIL10 ; Should be set
1751 
        SSEM    R1      ; semaphores
1752 
        BCC     _FAIL10 ; Should be set
1753 16 rehayes 
 
1754 89 rehayes 
        SSEM    #6      ; semaphore has been set by host
1755 
        BCS     _FAIL10 ; Should be clear
1756 16 rehayes 
 
1757 89 rehayes 
        CSEM    #7      ; semaphore
1758 
        CSEM    R1      ; semaphore #5
1759 
                        ; Host will test that these semaphores are clear
1760 16 rehayes 
 
1761 89 rehayes 
        SSEM    #3      ; set this semaphore for the host to test
1762 
 
1763 
 
1764 
_END_10
1765 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1766 
        LDH     R2,#$80
1767 
        LDL     R3,#$14
1768 
        STB     R3,(R2,#0)
1769 
 
1770 
        SIF
1771 
        RTS
1772 
 
1773 16 rehayes 
_FAIL10
1774 89 rehayes 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
1775 
        LDH     R2,#$80
1776 
        LDL     R3,#$14
1777 
        STB     R3,(R2,#0)
1778 
 
1779 16 rehayes 
        SIF
1780 89 rehayes 
        RTS
1781 16 rehayes 
 
1782 89 rehayes 
 
1783 16 rehayes 
;-------------------------------------------------------------------------------
1784 
;-------------------------------------------------------------------------------
1785 
 
1786 89 rehayes 
 
1787 16 rehayes 
;empty line
1788 
 
1789 
BACK_
1790 
 
1791 
 
1792 89 rehayes 
        SIF     R7
1793 
        BRK
1794 16 rehayes 
 
1795 89 rehayes 
        ORG     $8000 ; Special Testbench Addresses
1796 
_BENCH  DS.W    8
1797 16 rehayes 
 
1798 
 
1799 
 
1800 
 

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