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[/] [xgate/] [trunk/] [sw/] [xgate_test_code/] [inst_test/] [inst_test.s] - Blame information for rev 31

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1 16 rehayes 
; 345678901234567890123456789012345678901234567890123456789012345678901234567890
2 
; Instruction set test for xgate RISC processor core
3 
; Bob Hayes - Sept 1 2009
4 
;  Version 0.1 Basic test of all instruction done. Need to improve Condition
5 
;               Code function testing.
6 
 
7 
 
8 
        CPU     XGATE
9 
 
10 
        ORG     $fe00
11 
        DS.W    2       ; reserve two words at channel 0
12 
        ; channel 1
13 
        DC.W    _START  ; point to start address
14 
        DC.W    V_PTR   ; point to initial variables
15 
        ; channel 2
16 
        DC.W    _START2 ; point to start address
17 
        DC.W    V_PTR   ; point to initial variables
18 
        ; channel 3
19 
        DC.W    _START3 ; point to start address
20 
        DC.W    V_PTR   ; point to initial variables
21 
        ; channel 4
22 
        DC.W    _START4 ; point to start address
23 
        DC.W    V_PTR   ; point to initial variables
24 
        ; channel 5
25 
        DC.W    _START5 ; point to start address
26 
        DC.W    V_PTR   ; point to initial variables
27 
        ; channel 6
28 
        DC.W    _START6 ; point to start address
29 
        DC.W    V_PTR   ; point to initial variables
30 
        ; channel 7
31 
        DC.W    _START7 ; point to start address
32 
        DC.W    V_PTR   ; point to initial variables
33 
        ; channel 8
34 
        DC.W    _START8 ; point to start address
35 
        DC.W    V_PTR   ; point to initial variables
36 
        ; channel 9
37 
        DC.W    _START9 ; point to start address
38 
        DC.W    V_PTR   ; point to initial variables
39 
        ; channel 10
40 
        DC.W    _START10        ; point to start address
41 
        DC.W    V_PTR           ; point to initial variables
42 
        ; channel 11
43 
        DC.W    _ERROR          ; point to start address
44 
        DC.W    V_PTR           ; point to initial variables
45 
        ; channel 12
46 
        DC.W    _ERROR          ; point to start address
47 
        DC.W    V_PTR           ; point to initial variables
48 
        ; channel 13
49 
        DC.W    _ERROR          ; point to start address
50 
        DC.W    V_PTR           ; point to initial variables
51 
        ; channel 14
52 
        DC.W    _ERROR          ; point to start address
53 
        DC.W    V_PTR           ; point to initial variables
54 
        ; channel 15
55 
        DC.W    _ERROR          ; point to start address
56 
        DC.W    V_PTR           ; point to initial variables
57 
        ; channel 16
58 
        DC.W    _ERROR  ; point to start address
59 
        DC.W    V_PTR   ; point to initial variables
60 
        ; channel 17
61 
        DC.W    _ERROR  ; point to start address
62 
        DC.W    V_PTR   ; point to initial variables
63 
        ; channel 18
64 
        DC.W    _ERROR  ; point to start address
65 
        DC.W    V_PTR   ; point to initial variables
66 
        ; channel 19
67 
        DC.W    _ERROR  ; point to start address
68 
        DC.W    V_PTR   ; point to initial variables
69 
        ; channel 20
70 
        DC.W    _ERROR  ; point to start address
71 
        DC.W    V_PTR   ; point to initial variables
72 
        ; channel 21
73 
        DC.W    _ERROR  ; point to start address
74 
        DC.W    V_PTR   ; point to initial variables
75 
        ; channel 22
76 
        DC.W    _ERROR  ; point to start address
77 
        DC.W    V_PTR   ; point to initial variables
78 
        ; channel 23
79 
        DC.W    _ERROR  ; point to start address
80 
        DC.W    V_PTR   ; point to initial variables
81 
        ; channel 24
82 
        DC.W    _ERROR  ; point to start address
83 
        DC.W    V_PTR   ; point to initial variables
84 
        ; channel 25
85 
        DC.W    _ERROR  ; point to start address
86 
        DC.W    V_PTR   ; point to initial variables
87 
        ; channel 26
88 
        DC.W    _ERROR  ; point to start address
89 
        DC.W    V_PTR   ; point to initial variables
90 
        ; channel 27
91 
        DC.W    _ERROR  ; point to start address
92 
        DC.W    V_PTR   ; point to initial variables
93 
        ; channel 28
94 
        DC.W    _ERROR  ; point to start address
95 
        DC.W    V_PTR   ; point to initial variables
96 
        ; channel 29
97 
        DC.W    _ERROR  ; point to start address
98 
        DC.W    V_PTR   ; point to initial variables
99 
        ; channel 30
100 
        DC.W    _ERROR  ; point to start address
101 
        DC.W    V_PTR   ; point to initial variables
102 
        ; channel 31
103 
        DC.W    _ERROR  ; point to start address
104 
        DC.W    V_PTR   ; point to initial variables
105 
        ; channel 32
106 
        DC.W    _ERROR  ; point to start address
107 
        DC.W    V_PTR   ; point to initial variables
108 
        ; channel 33
109 
        DC.W    _ERROR  ; point to start address
110 
        DC.W    V_PTR   ; point to initial variables
111 
        ; channel 34
112 
        DC.W    _ERROR  ; point to start address
113 
        DC.W    V_PTR   ; point to initial variables
114 
        ; channel 35
115 
        DC.W    _ERROR  ; point to start address
116 
        DC.W    V_PTR   ; point to initial variables
117 
        ; channel 36
118 
        DC.W    _ERROR  ; point to start address
119 
        DC.W    V_PTR   ; point to initial variables
120 
        ; channel 37
121 
        DC.W    _ERROR  ; point to start address
122 
        DC.W    V_PTR   ; point to initial variables
123 
        ; channel 38
124 
        DC.W    _ERROR  ; point to start address
125 
        DC.W    V_PTR   ; point to initial variables
126 
        ; channel 39
127 
        DC.W    _ERROR  ; point to start address
128 
        DC.W    V_PTR   ; point to initial variables
129 
        ; channel 40
130 
        DC.W    _ERROR  ; point to start address
131 
        DC.W    V_PTR   ; point to initial variables
132 
        ; channel 41
133 
        DC.W    _ERROR  ; point to start address
134 
        DC.W    V_PTR   ; point to initial variables
135 
        ; channel 42
136 
        DC.W    _ERROR  ; point to start address
137 
        DC.W    V_PTR   ; point to initial variables
138 
        ; channel 43
139 
        DC.W    _ERROR  ; point to start address
140 
        DC.W    V_PTR   ; point to initial variables
141 
        ; channel 44
142 
        DC.W    _ERROR  ; point to start address
143 
        DC.W    V_PTR   ; point to initial variables
144 
        ; channel 45
145 
        DC.W    _ERROR  ; point to start address
146 
        DC.W    V_PTR   ; point to initial variables
147 
        ; channel 46
148 
        DC.W    _ERROR  ; point to start address
149 
        DC.W    V_PTR   ; point to initial variables
150 
        ; channel 47
151 
        DC.W    _ERROR  ; point to start address
152 
        DC.W    V_PTR   ; point to initial variables
153 
        ; channel 48
154 
        DC.W    _ERROR  ; point to start address
155 
        DC.W    V_PTR   ; point to initial variables
156 
        ; channel 49
157 
        DC.W    _ERROR  ; point to start address
158 
        DC.W    V_PTR   ; point to initial variables
159 
        ; channel 50
160 
        DC.W    _ERROR  ; point to start address
161 
        DC.W    V_PTR   ; point to initial variables
162 
 
163 
        ORG     $2000 ; with comment
164 
 
165 
V_PTR   EQU     123
166 
 
167 
        DC.W    BACK_
168 
        DS.W    8
169 
        DC.B    $56
170 
        DS.B    11
171 
 
172 
        ALIGN   1
173 
 
174 
;-------------------------------------------------------------------------------
175 
;   Place where undefined interrupts go
176 
;-------------------------------------------------------------------------------
177 
_ERROR
178 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
179 
        LDH     R2,#$80
180 
        LDL     R3,#$ff
181 
        STB     R3,(R2,#0)
182 
 
183 
        SIF
184 
        RTS
185 
 
186 
 
187 
;-------------------------------------------------------------------------------
188 
;   Test Shift instructions
189 
;-------------------------------------------------------------------------------
190 
_START
191 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
192 
        LDH     R2,#$80
193 
        LDL     R3,#$01
194 
        STB     R3,(R2,#0)
195 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
196 
 
197 
 
198 
        ; Test Bit Field Find First One
199 
        LDL     R5,#$01  ; R5=$0001
200 
        LDH     R5,#$4f  ; R5=$4f01
201 
        BFFO    R4,R5
202 
        BVS     _FAIL    ; Negative Flag should be clear
203 
        LDL     R6,#$0e  ; First one should have been in bit position 14
204 
        SUB     R0,R6,R4
205 
        BNE     _FAIL
206 
        BFFO    R4,R0    ; Zero Value should set Carry Bit
207 
        BCC     _FAIL
208 
        LDH     R5,#$00  ; R5=$0001
209 
        BFFO    R4,R5
210 
        BCS     _FAIL    ; Carry should be clear
211 
        BVS     _FAIL    ; Overflow Flag should be clear
212 
        SUB     R0,R0,R4 ; R4 Should be zero
213 
        BNE     _FAIL
214 
 
215 
       ; Test ASR instruction
216 
        LDL     R5,#$04  ; R5=$0008
217 
        LDH     R5,#$81  ; R5=$8108
218 
        LDL     R3,#$03
219 
        ASR     R5,R3    ; R5=$f000, Carry flag set
220 
        BCC     _FAIL
221 
        BVS     _FAIL    ; Negative Flag should be clear
222 
        LDL     R4,#$20  ; R4=$0020
223 
        LDH     R4,#$f0  ; R4=$f020
224 
        SUB     R0,R5,R4 ; Compare R5 to R4
225 
        BNE     _FAIL
226 
 
227 
       ; Test CSL insrtruction
228 
        LDL     R5,#$10  ; R5=$0010
229 
        LDH     R5,#$88  ; R5=$8810
230 
        LDL     R3,#$05
231 
        CSL     R5,R3    ; R5=$081f, Carry flag set
232 
        BCC     _FAIL
233 
        LDL     R4,#$00  ; R4=$0000
234 
        LDH     R4,#$02  ; R4=$0200
235 
        SUB     R0,R5,R4 ; Compare R5 to R4
236 
        BNE     _FAIL
237 
 
238 
       ;Test CSR instruction
239 
        LDL     R5,#$88  ; R5=$0088
240 
        LDH     R5,#$10  ; R5=$1088
241 
        LDL     R3,#$04
242 
        CSR     R5,R3    ; R5=$0108, Carry flag set
243 
        BCC     _FAIL
244 
        LDL     R4,#$08  ; R4=$0008
245 
        LDH     R4,#$01  ; R4=$0108
246 
        SUB     R0,R5,R4 ; Compare R5 to R4
247 
        BNE     _FAIL
248 
 
249 
       ;Test LSL instruction
250 
        LDL     R2,#$ff  ; R2=$00ff
251 
        LDH     R2,#$07  ; R2=$07ff
252 
        LDL     R1,#$06
253 
        LSL     R2,R1    ; R2=$ffc0, Carry flag set
254 
        BCC     _FAIL
255 
        LDL     R4,#$c0  ; R4=$0008
256 
        LDH     R4,#$ff  ; R4=$0108
257 
        SUB     R0,R2,R4 ; Compare R2 to R4
258 
        BNE     _FAIL
259 
 
260 
       ;Test LSR instruction
261 
        LDL     R7,#$02  ; R7=$0002
262 
        LDH     R7,#$c3  ; R7=$c302
263 
        LDL     R6,#$02
264 
        LSR     R7,R6    ; R7=$30c0, Carry flag set
265 
        BCC     _FAIL
266 
        LDL     R4,#$c0  ; R4=$00c0
267 
        LDH     R4,#$30  ; R4=$30c0
268 
        SUB     R0,R7,R4 ; Compare R7 to R4
269 
        BNE     _FAIL
270 
 
271 
       ;Test ROL instruction
272 
        LDL     R7,#$62  ; R7=$0062
273 
        LDH     R7,#$c3  ; R7=$c362
274 
        LDL     R6,#$04
275 
        ROL     R7,R6    ; R7=$362c
276 
        BVS     _FAIL    ; Overflow Flag should be clear
277 
        LDL     R4,#$2c  ; R4=$002c
278 
        LDH     R4,#$36  ; R4=$362c
279 
        SUB     R0,R7,R4 ; Compare R7 to R4
280 
        BNE     _FAIL
281 
 
282 
       ;Test ROR instruction
283 
        LDL     R7,#$62  ; R7=$0062
284 
        LDH     R7,#$c3  ; R7=$c362
285 
        LDL     R6,#$08
286 
        ROL     R7,R6    ; R7=$62c3
287 
        BVS     _FAIL    ; Overflow Flag should be clear
288 
        LDL     R4,#$c3  ; R4=$00c3
289 
        LDH     R4,#$62  ; R4=$62c3
290 
        SUB     R0,R7,R4 ; Compare R7 to R4
291 
        BNE     _FAIL
292 
 
293 
       ; Test ASR instruction
294 
        LDL     R5,#$00  ; R5=$0000
295 
        LDH     R5,#$80  ; R5=$8000
296 
        ASR     R5,#0    ; R5=$ffff, Carry flag set
297 
        BCC     _FAIL
298 
        BVS     _FAIL    ; Overflow Flag should be clear
299 
        LDL     R4,#$ff  ; R4=$00ff
300 
        LDH     R4,#$ff  ; R4=$ffff
301 
        SUB     R0,R5,R4 ; Compare R5 to R4
302 
        BNE     _FAIL
303 
 
304 
       ; Test CSL insrtruction
305 
        LDL     R5,#$01  ; R5=$0001
306 
        LDH     R5,#$0f  ; R5=$0f01
307 
        CSL     R5,#0    ; R5=$0000, Carry flag set
308 
        BCC     _FAIL
309 
        LDL     R4,#$00  ; R4=$0000
310 
        LDH     R4,#$00  ; R4=$0000
311 
        SUB     R0,R5,R4 ; Compare R5 to R4
312 
        BNE     _FAIL
313 
 
314 
       ;Test CSR instruction
315 
        LDL     R5,#$ff  ; R5=$00ff
316 
        LDH     R5,#$80  ; R5=$80ff
317 
        CSR     R5,#15   ; R5=$0001, Carry flag clear
318 
        BCS     _FAIL
319 
        LDL     R4,#$01  ; R4=$0001
320 
        LDH     R4,#$00  ; R4=$0001
321 
        SUB     R0,R5,R4 ; Compare R5 to R4
322 
        BNE     _FAIL
323 
 
324 
       ;Test LSL instruction
325 
        LDL     R2,#$1a  ; R2=$001a
326 
        LDH     R2,#$ff  ; R2=$ff1a
327 
        LSL     R2,#12   ; R2=$a000, Carry flag set
328 
        BCC     _FAIL
329 
        LDL     R4,#$00  ; R4=$0000
330 
        LDH     R4,#$a0  ; R4=$a000
331 
        SUB     R0,R2,R4 ; Compare R2 to R4
332 
        BNE     _FAIL
333 
 
334 
       ;Test LSR instruction
335 
        LDL     R7,#$8f  ; R7=$008f
336 
        LDH     R7,#$b2  ; R7=$b18f
337 
        LSR     R7,#8    ; R7=$00b0, Carry flag set
338 
        BCC     _FAIL
339 
        LDL     R4,#$b2  ; R4=$00b0
340 
        LDH     R4,#$00  ; R4=$00b0
341 
        SUB     R0,R7,R4 ; Compare R7 to R4
342 
        BNE     _FAIL
343 
 
344 
       ;Test ROL instruction
345 
        LDL     R7,#$62  ; R7=$0062
346 
        LDH     R7,#$c3  ; R7=$c362
347 
        ROL     R7,#8    ; R7=$62c3
348 
        BVS     _FAIL    ; Overflow Flag should be clear
349 
        LDL     R4,#$c3  ; R4=$00c3
350 
        LDH     R4,#$62  ; R4=$62c3
351 
        SUB     R0,R7,R4 ; Compare R7 to R4
352 
        BNE     _FAIL
353 
 
354 
       ;Test ROR instruction
355 
        LDL     R7,#$62  ; R7=$0062
356 
        LDH     R7,#$c3  ; R7=$c362
357 
        ROL     R7,#12   ; R7=$2c36
358 
        BVS     _FAIL    ; Overflow Flag should be clear
359 
        LDL     R4,#$36  ; R4=$0036
360 
        LDH     R4,#$2c  ; R4=$2c36
361 
        SUB     R0,R7,R4 ; Compare R7 to R4
362 
        BNE     _FAIL
363 
 
364 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
365 
        LDH     R2,#$80
366 
        LDL     R3,#$02
367 
        STB     R3,(R2,#0)
368 
 
369 
        NOP
370 
        NOP
371 
        SIF
372 
        RTS
373 
 
374 
_FAIL
375 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
376 
        LDH     R2,#$80
377 
        LDL     R3,#$02
378 
        STB     R3,(R2,#0)
379 
 
380 
        SIF
381 
        RTS
382 
 
383 
;-------------------------------------------------------------------------------
384 
;   Test Logical Byte wide instructions
385 
;-------------------------------------------------------------------------------
386 
_START2
387 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
388 
        LDH     R2,#$80
389 
        LDL     R3,#$03    ; Checkpoint Value
390 
        STB     R3,(R2,#0)
391 
        LDL     R3,#$02    ; Thread Value
392 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
393 
 
394 
       ;Test ANDL instruction
395 
        LDL     R7,#$55  ; R7=$0055
396 
        LDH     R7,#$a5  ; R7=$a555
397 
        ANDL    R7,#$00  ; R7=&a500
398 
        BNE     _FAIL2   ; Zero Flag should be set
399 
        BVS     _FAIL2   ; Overflow Flag should be clear
400 
        BMI     _FAIL2   ; Negative Flag should be clear
401 
        LDL     R3,#$00  ; R3=$0000
402 
        LDH     R3,#$a5  ; R3=$a500
403 
        SUB     R0,R7,R3 ; Compare R7 to R3
404 
        BNE     _FAIL2
405 
        LDL     R7,#$c5  ; R7=$00c5
406 
        LDH     R7,#$a5  ; R7=$a5c5
407 
        ANDL    R7,#$80  ; R7=$a580
408 
        BPL     _FAIL2   ; Negative Flag should be set
409 
        BEQ     _FAIL2   ; Zero Flag should be clear
410 
        BVS     _FAIL2   ; Overflow Flag should be clear
411 
        LDL     R3,#$80  ; R3=$0080
412 
        LDH     R3,#$a5  ; R3=$a580
413 
        SUB     R0,R7,R3 ; Compare R7 to R3
414 
        BNE     _FAIL2
415 
 
416 
       ;Test ANDH instruction
417 
        LDL     R7,#$55  ; R7=$0055
418 
        LDH     R7,#$a5  ; R7=$a555
419 
        ANDH    R7,#$00  ; R7=&0055
420 
        BNE     _FAIL2   ; Zero Flag should be set
421 
        BVS     _FAIL2   ; Overflow Flag should be clear
422 
        BMI     _FAIL2   ; Negative Flag should be clear
423 
        LDL     R3,#$55  ; R3=$0000
424 
        LDH     R3,#$00  ; R3=$a500
425 
        SUB     R0,R7,R3 ; Compare R7 to R3
426 
        BNE     _FAIL2
427 
        LDL     R7,#$c5  ; R7=$00c5
428 
        LDH     R7,#$a5  ; R7=$a5c5
429 
        ANDH    R7,#$80  ; R7=$80c5
430 
        BPL     _FAIL2   ; Negative Flag should be set
431 
        BEQ     _FAIL2   ; Zero Flag should be clear
432 
        BVS     _FAIL2   ; Overflow Flag should be clear
433 
        LDL     R3,#$c5  ; R3=$00c5
434 
        LDH     R3,#$80  ; R3=$80c5
435 
        SUB     R0,R7,R3 ; Compare R7 to R3
436 
        BNE     _FAIL2
437 
 
438 
       ;Test BITL instruction
439 
        LDL     R7,#$55  ; R7=$0055
440 
        LDH     R7,#$a5  ; R7=$a555
441 
        BITL    R7,#$00  ; R7=&a500
442 
        BNE     _FAIL2   ; Zero Flag should be set
443 
        BVS     _FAIL2   ; Overflow Flag should be clear
444 
        BMI     _FAIL2   ; Negative Flag should be clear
445 
        LDL     R7,#$c5  ; R7=$00c5
446 
        LDH     R7,#$a5  ; R7=$a5c5
447 
        BITL    R7,#$80  ; R7=$a580
448 
        BPL     _FAIL2   ; Negative Flag should be set
449 
        BEQ     _FAIL2   ; Zero Flag should be clear
450 
        BVS     _FAIL2   ; Overflow Flag should be clear
451 
 
452 
       ;Test BITH instruction
453 
        LDL     R7,#$55  ; R7=$0055
454 
        LDH     R7,#$a5  ; R7=$a555
455 
        BITH    R7,#$00  ; R7=&0055
456 
        BNE     _FAIL2   ; Zero Flag should be set
457 
        BVS     _FAIL2   ; Overflow Flag should be clear
458 
        BMI     _FAIL2   ; Negative Flag should be clear
459 
        LDL     R7,#$c5  ; R7=$00c5
460 
        LDH     R7,#$a5  ; R7=$a5c5
461 
        BITH    R7,#$80  ; R7=$80c5
462 
        BPL     _FAIL2   ; Negative Flag should be set
463 
        BEQ     _FAIL2   ; Zero Flag should be clear
464 
        BVS     _FAIL2   ; Overflow Flag should be clear
465 
 
466 
       ;Test ORL instruction
467 
        LDL     R2,#$0b
468 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=1
469 
        LDL     R7,#$00  ; R7=$0000
470 
        LDH     R7,#$a5  ; R7=$a500
471 
        ORL     R7,#$00  ; R7=&a500
472 
        BMI     _FAIL2   ; Negative Flag should be clear
473 
        BNE     _FAIL2   ; Zero Flag should be set
474 
        BVS     _FAIL2   ; Overflow Flag should be clear
475 
        BCC     _FAIL2   ; Carry Flag should be set
476 
        LDL     R3,#$00  ; R3=$0000
477 
        LDH     R3,#$a5  ; R3=$a500
478 
        SUB     R0,R7,R3 ; Compare R7 to R3
479 
        BNE     _FAIL2
480 
        LDL     R2,#$06
481 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=1, Carry=0
482 
        LDL     R7,#$9f  ; R7=$009f
483 
        LDH     R7,#$a5  ; R7=$a59f
484 
        ORL     R7,#$60  ; R7=$a5ff
485 
        BPL     _FAIL2   ; Negative Flag should be set
486 
        BEQ     _FAIL2   ; Zero Flag should be clear
487 
        BVS     _FAIL2   ; Overflow Flag should be clear
488 
        BCS     _FAIL2   ; Carry Flag should be clear
489 
        LDL     R3,#$ff  ; R3=$00ff
490 
        LDH     R3,#$a5  ; R3=$a5ff
491 
        SUB     R0,R7,R3 ; Compare R7 to R3
492 
        BNE     _FAIL2
493 
 
494 
       ;Test ORH instruction
495 
        LDL     R2,#$0b
496 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=1
497 
        LDL     R7,#$88  ; R7=$0088
498 
        LDH     R7,#$00  ; R7=$0088
499 
        ORH     R7,#$00  ; R7=&0088
500 
        BMI     _FAIL2   ; Negative Flag should be clear
501 
        BNE     _FAIL2   ; Zero Flag should be set
502 
        BVS     _FAIL2   ; Overflow Flag should be clear
503 
        BCC     _FAIL2   ; Carry Flag should be set
504 
        LDL     R3,#$88  ; R3=$0088
505 
        LDH     R3,#$00  ; R3=$0088
506 
        SUB     R0,R7,R3 ; Compare R7 to R3
507 
        BNE     _FAIL2
508 
        LDL     R2,#$06
509 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=1, Carry=0
510 
        LDL     R7,#$36  ; R7=$0036
511 
        LDH     R7,#$a1  ; R7=$a136
512 
        ORH     R7,#$50  ; R7=$f136
513 
        BPL     _FAIL2   ; Negative Flag should be set
514 
        BEQ     _FAIL2   ; Zero Flag should be clear
515 
        BVS     _FAIL2   ; Overflow Flag should be clear
516 
        BCS     _FAIL2   ; Carry Flag should be clear
517 
        LDL     R3,#$36  ; R3=$0036
518 
        LDH     R3,#$f1  ; R3=$f136
519 
        SUB     R0,R7,R3 ; Compare R7 to R3
520 
        BNE     _FAIL2
521 
 
522 
       ;Test XNORL instruction
523 
        LDL     R2,#$0b
524 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=1
525 
        LDL     R7,#$c3  ; R7=$00c3
526 
        LDH     R7,#$96  ; R7=$96c3
527 
        XNORL   R7,#$3c  ; R7=$9600
528 
        BMI     _FAIL2   ; Negative Flag should be clear
529 
        BNE     _FAIL2   ; Zero Flag should be set
530 
        BVS     _FAIL2   ; Overflow Flag should be clear
531 
        BCC     _FAIL2   ; Carry Flag should be set
532 
        LDL     R3,#$00  ; R3=$0000
533 
        LDH     R3,#$96  ; R3=$9600
534 
        SUB     R0,R7,R3 ; Compare R7 to R3
535 
        BNE     _FAIL2
536 
        LDL     R2,#$06
537 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=1, Carry=0
538 
        LDL     R6,#$00  ; R6=$0000
539 
        LDH     R6,#$a5  ; R6=$a500
540 
        XNORL   R6,#$73  ; R6=$a58c
541 
        BPL     _FAIL2   ; Negative Flag should be set
542 
        BEQ     _FAIL2   ; Zero Flag should be clear
543 
        BVS     _FAIL2   ; Overflow Flag should be clear
544 
        BCS     _FAIL2   ; Carry Flag should be clear
545 
        LDL     R3,#$8c  ; R3=$008c
546 
        LDH     R3,#$a5  ; R3=$a58c
547 
        SUB     R0,R6,R3 ; Compare R6 to R3
548 
        BNE     _FAIL2
549 
 
550 
       ;Test XNORH instruction
551 
        LDL     R2,#$0b
552 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=1
553 
        LDL     R7,#$c3  ; R7=$00c3
554 
        LDH     R7,#$96  ; R7=$96c3
555 
        XNORH   R7,#$69  ; R7=$00c3
556 
        BMI     _FAIL2   ; Negative Flag should be clear
557 
        BNE     _FAIL2   ; Zero Flag should be set
558 
        BVS     _FAIL2   ; Overflow Flag should be clear
559 
        BCC     _FAIL2   ; Carry Flag should be set
560 
        LDL     R3,#$c3  ; R3=$00c3
561 
        LDH     R3,#$00  ; R3=$00c3
562 
        SUB     R0,R7,R3 ; Compare R7 to R3
563 
        BNE     _FAIL2
564 
        LDL     R2,#$06
565 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=1, Carry=0
566 
        LDL     R6,#$66  ; R6=$0066
567 
        LDH     R6,#$66  ; R6=$6666
568 
        XNORH   R6,#$66  ; R6=$ff66
569 
        BPL     _FAIL2   ; Negative Flag should be set
570 
        BEQ     _FAIL2   ; Zero Flag should be clear
571 
        BVS     _FAIL2   ; Overflow Flag should be clear
572 
        BCS     _FAIL2   ; Carry Flag should be clear
573 
        LDL     R3,#$66  ; R3=$0066
574 
        LDH     R3,#$ff  ; R3=$ff66
575 
        SUB     R0,R6,R3 ; Compare R6 to R3
576 
        BNE     _FAIL2
577 
 
578 
 
579 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
580 
        LDH     R2,#$80
581 
        LDL     R3,#$04
582 
        STB     R3,(R2,#0)
583 
 
584 
        SIF
585 
        RTS
586 
 
587 
_FAIL2
588 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
589 
        LDH     R2,#$80
590 
        LDL     R3,#$04
591 
        STB     R3,(R2,#0)
592 
 
593 
        SIF
594 
        RTS
595 
 
596 
;-------------------------------------------------------------------------------
597 
;   Test Logical Word Wide instructions
598 
;-------------------------------------------------------------------------------
599 
_START3
600 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
601 
        LDH     R2,#$80
602 
        LDL     R3,#$05    ; Checkpoint Value
603 
        STB     R3,(R2,#0)
604 
        LDL     R3,#$03    ; Thread Value
605 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
606 
 
607 
       ;Test SEX instruction
608 
        LDL     R2,#$0b
609 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=1
610 
        LDL     R3,#$00  ; R3=$0000
611 
        LDH     R3,#$ff  ; R3=$ff00
612 
        SEX     R3       ; R3=$0000
613 
        BMI     _FAIL3   ; Negative Flag should be clear
614 
        BNE     _FAIL3   ; Zero Flag should be set
615 
        BVS     _FAIL3   ; Overflow Flag should be clear
616 
        BCC     _FAIL3   ; Carry Flag should be set
617 
        LDL     R6,#$00  ; R6=$0000
618 
        LDH     R6,#$00  ; R6=$0000
619 
        SUB     R0,R6,R3 ; Compare R6 to R3
620 
        BNE     _FAIL3
621 
        LDL     R2,#$06
622 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=1, Carry=0
623 
        LDL     R6,#$83  ; R6=$0083
624 
        LDH     R6,#$00  ; R6=$0083
625 
        SEX     R6       ; R6=$ff83
626 
        BPL     _FAIL3   ; Negative Flag should be set
627 
        BEQ     _FAIL3   ; Zero Flag should be clear
628 
        BVS     _FAIL3   ; Overflow Flag should be clear
629 
        BCS     _FAIL3   ; Carry Flag should be clear
630 
        LDL     R3,#$83  ; R3=$0083
631 
        LDH     R3,#$ff  ; R3=$ff83
632 
        SUB     R0,R6,R3 ; Compare R6 to R3
633 
        BNE     _FAIL3
634 
 
635 
       ;Test PAR instruction
636 
        LDL     R2,#$0a
637 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=0
638 
        LDL     R4,#$00  ; R4=$0000
639 
        LDH     R4,#$00  ; R4=$0000
640 
        PAR     R4       ; R4=$0000
641 
        BMI     _FAIL3   ; Negative Flag should be clear
642 
        BNE     _FAIL3   ; Zero Flag should be set
643 
        BVS     _FAIL3   ; Overflow Flag should be clear
644 
        BCS     _FAIL3   ; Carry Flag should be clear
645 
        LDL     R6,#$00  ; R6=$0000
646 
        LDH     R6,#$00  ; R6=$0000
647 
        SUB     R0,R6,R4 ; Compare R6 to R4
648 
        BNE     _FAIL3
649 
        LDL     R2,#$0e
650 
        TFR     CCR,R2   ; Negative=1, Zero=1, Overflow=1, Carry=0
651 
        LDL     R6,#$01  ; R6=$0001
652 
        LDH     R6,#$03  ; R6=$0301
653 
        PAR     R6       ; R6=$0301
654 
        BMI     _FAIL3   ; Negative Flag should be clear
655 
        BEQ     _FAIL3   ; Zero Flag should be clear
656 
        BVS     _FAIL3   ; Overflow Flag should be clear
657 
        BCC     _FAIL3   ; Carry Flag should be set
658 
        LDL     R3,#$01  ; R3=$0001
659 
        LDH     R3,#$03  ; R3=$0301
660 
        SUB     R0,R6,R3 ; Compare R6 to R3
661 
        BNE     _FAIL3
662 
 
663 
       ;Test AND instruction
664 
        LDL     R2,#$0a
665 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=0
666 
        LDL     R6,#$55  ; R6=$0055
667 
        LDH     R6,#$aa  ; R6=$aa55
668 
        LDL     R5,#$aa  ; R5=$00aa
669 
        LDH     R5,#$55  ; R5=$55aa
670 
        AND     R3,R5,R6 ; R3=$0000
671 
        BMI     _FAIL3   ; Negative Flag should be clear
672 
        BNE     _FAIL3   ; Zero Flag should be set
673 
        BVS     _FAIL3   ; Overflow Flag should be clear
674 
        BCS     _FAIL3   ; Carry Flag should be clear
675 
        SUB     R0,R0,R3 ; Compare R0 to R3
676 
        BNE     _FAIL3
677 
        LDL     R7,#$55  ; R7=$00c5
678 
        LDH     R7,#$aa  ; R7=$aa55
679 
        LDL     R2,#$07
680 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=1, Carry=1
681 
        AND     R4,R6,R7 ; R4=$aa55
682 
        BPL     _FAIL3   ; Negative Flag should be set
683 
        BEQ     _FAIL3   ; Zero Flag should be clear
684 
        BVS     _FAIL3   ; Overflow Flag should be clear
685 
        BCC     _FAIL3   ; Carry Flag should be set
686 
        SUB     R0,R4,R7 ; Compare R4 to R7
687 
        BNE     _FAIL2
688 
 
689 
       ;Test OR instruction
690 
        LDL     R2,#$0a
691 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=0
692 
        LDL     R6,#$00  ; R6=$0000
693 
        LDL     R5,#$00  ; R5=$0000
694 
        OR      R3,R5,R6 ; R3=$0000
695 
        BMI     _FAIL3   ; Negative Flag should be clear
696 
        BNE     _FAIL3   ; Zero Flag should be set
697 
        BVS     _FAIL3   ; Overflow Flag should be clear
698 
        BCS     _FAIL3   ; Carry Flag should be clear
699 
        SUB     R0,R0,R3 ; Compare R0 to R3
700 
        BNE     _FAIL3
701 
        LDL     R7,#$55  ; R7=$00c5
702 
        LDH     R7,#$aa  ; R7=$aa55
703 
        LDL     R6,#$8a  ; R6=$008a
704 
        LDH     R6,#$10  ; R7=$108a
705 
        LDL     R2,#$07
706 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=1, Carry=1
707 
        OR      R4,R6,R7 ; R4=$badf
708 
        BPL     _FAIL3   ; Negative Flag should be set
709 
        BEQ     _FAIL3   ; Zero Flag should be clear
710 
        BVS     _FAIL3   ; Overflow Flag should be clear
711 
        BCC     _FAIL3   ; Carry Flag should be set
712 
        LDL     R3,#$df  ; R3=$00df
713 
        LDH     R3,#$ba  ; R3=$badf
714 
        SUB     R0,R4,R3 ; Compare R6 to R3
715 
        BNE     _FAIL3
716 
 
717 
       ;Test XNOR instruction
718 
        LDL     R2,#$0a
719 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=0
720 
        LDL     R1,#$55  ; R1=$0055
721 
        LDH     R1,#$aa  ; R1=$aa55
722 
        LDL     R5,#$aa  ; R5=$00aa
723 
        LDH     R5,#$55  ; R5=$55aa
724 
        XNOR    R3,R5,R1 ; R3=$0000
725 
        BMI     _FAIL3   ; Negative Flag should be clear
726 
        BNE     _FAIL3   ; Zero Flag should be set
727 
        BVS     _FAIL3   ; Overflow Flag should be clear
728 
        BCS     _FAIL3   ; Carry Flag should be clear
729 
        SUB     R0,R0,R3 ; Compare R0 to R3
730 
        BNE     _FAIL3
731 
        LDL     R7,#$cc  ; R7=$00cc
732 
        LDH     R7,#$33  ; R7=$33cc
733 
        LDL     R2,#$01  ; R2=$0001
734 
        LDH     R2,#$40  ; R2=$4001
735 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=1, Carry=1
736 
        XNOR    R4,R7,R2 ; R4=$8c32
737 
        BPL     _FAIL3   ; Negative Flag should be set
738 
        BEQ     _FAIL3   ; Zero Flag should be clear
739 
        BVS     _FAIL3   ; Overflow Flag should be clear
740 
        BCC     _FAIL3   ; Carry Flag should be set
741 
        LDL     R3,#$32  ; R3=$0032
742 
        LDH     R3,#$8c  ; R3=$8c32
743 
        SUB     R0,R4,R3 ; Compare R4 to R3
744 
        BNE     _FAIL3
745 
 
746 
 
747 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
748 
        LDH     R2,#$80
749 
        LDL     R3,#$06
750 
        STB     R3,(R2,#0)
751 
 
752 
        NOP
753 
        SIF
754 
        RTS
755 
 
756 
_FAIL3
757 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
758 
        LDH     R2,#$80
759 
        LDL     R3,#$06
760 
        STB     R3,(R2,#0)
761 
 
762 
        SIF
763 
        RTS
764 
 
765 
 
766 
;-------------------------------------------------------------------------------
767 
;   Test Bit Field instructions
768 
;-------------------------------------------------------------------------------
769 
_START4
770 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
771 
        LDH     R2,#$80
772 
        LDL     R3,#$07    ; Checkpoint Value
773 
        STB     R3,(R2,#0)
774 
        LDL     R3,#$04    ; Thread Value
775 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
776 
 
777 
       ;Test BFEXT instruction
778 
        LDL     R2,#$0e
779 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=1, Carry=0
780 
        LDL     R6,#$34    ; Set offset to 4 and width to 3(4 bits)
781 
        LDL     R5,#$a6    ; Set R5=$00a6
782 
        LDH     R5,#$c3    ; Set R5=$c3a6
783 
        LDL     R4,#$ff    ; Set R4=$00ff
784 
        SEX     R4         ; Set R4=$ffff
785 
        BFEXT   R4,R5,R6   ; R4=$000a
786 
        BMI     _FAIL4     ; Negative Flag should be clear
787 
        BEQ     _FAIL4     ; Zero Flag should be clear
788 
        BVS     _FAIL4     ; Overflow Flag should be clear
789 
        BCS     _FAIL4     ; Carry Flag should be clear
790 
        LDL     R7,#$0a    ; R7=$00cc
791 
        SUB     R0,R7,R4 ; Compare R7 to R4
792 
        BNE     _FAIL4
793 
 
794 
        LDL     R6,#$b8    ; Set offset to 8 and width to 11(12 bits)
795 
        BFEXT   R4,R5,R6   ; R4=$00c3
796 
        LDL     R7,#$c3    ; R7=$00c3
797 
        SUB     R0,R7,R4 ; Compare R7 to R4
798 
        BNE     _FAIL4
799 
 
800 
       ;Test BFINS instruction
801 
        LDL     R2,#$06
802 
        TFR     CCR,R2     ; Negative=0, Zero=1, Overflow=1, Carry=0
803 
        LDL     R6,#$34    ; Set offset to 4 and width to 3(4 bits)
804 
        LDL     R5,#$a6    ; Set R5=$00a6
805 
        LDH     R5,#$c3    ; Set R5=$c3a6
806 
        LDL     R4,#$ff    ; Set R4=$00ff
807 
        SEX     R4         ; Set R4=$ffff
808 
        BFINS   R4,R5,R6   ; R4=$ffaf
809 
        BPL     _FAIL4     ; Negative Flag should be set
810 
        BEQ     _FAIL4     ; Zero Flag should be clear
811 
        BVS     _FAIL4     ; Overflow Flag should be clear
812 
        BCS     _FAIL4     ; Carry Flag should be clear
813 
        LDL     R7,#$6f    ; R7=$006f
814 
        LDH     R7,#$ff    ; R7=$ff6f
815 
        SUB     R0,R7,R4 ; Compare R7 to R4
816 
        BNE     _FAIL4
817 
 
818 
        LDL     R6,#$b0    ; Set offset to 0 and width to 11(12 bits)
819 
        BFINS   R4,R5,R6   ; R4=$f3a6
820 
        LDL     R7,#$a6    ; R7=$00a6
821 
        LDH     R7,#$f3    ; R7=$f3a6
822 
        SUB     R0,R7,R4 ; Compare R7 to R4
823 
        BNE     _FAIL4
824 
 
825 
       ;Test BFINSI instruction
826 
        LDL     R2,#$06
827 
        TFR     CCR,R2     ; Negative=0, Zero=1, Overflow=1, Carry=0
828 
        LDL     R6,#$3c    ; Set offset to 12 and width to 3(4 bits)
829 
        LDL     R5,#$a6    ; Set R5=$00a6
830 
        LDH     R5,#$c3    ; Set R5=$c3a6
831 
        LDL     R4,#$ff    ; Set R4=$00ff
832 
        SEX     R4         ; Set R4=$ffff
833 
        BFINSI  R4,R5,R6   ; R4=$9fff
834 
        BPL     _FAIL4     ; Negative Flag should be set
835 
        BEQ     _FAIL4     ; Zero Flag should be clear
836 
        BVS     _FAIL4     ; Overflow Flag should be clear
837 
        BCS     _FAIL4     ; Carry Flag should be clear
838 
        LDL     R7,#$ff    ; R7=$00ff
839 
        LDH     R7,#$9f    ; R7=$ff6f
840 
        SUB     R0,R7,R4 ; Compare R7 to R4
841 
        BNE     _FAIL4
842 
 
843 
        LDL     R6,#$78    ; Set offset to 8 and width to 7(8 bits)
844 
        BFINSI  R4,R5,R6   ; R4=$59ff
845 
        LDL     R7,#$ff    ; R7=$00ff
846 
        LDH     R7,#$59    ; R7=$59ff
847 
        SUB     R0,R7,R4 ; Compare R7 to R4
848 
        BNE     _FAIL4
849 
 
850 
       ;Test BFINSX instruction
851 
        LDL     R2,#$06
852 
        TFR     CCR,R2     ; Negative=0, Zero=1, Overflow=1, Carry=0
853 
        LDL     R6,#$38    ; Set offset to 8 and width to 3(4 bits)
854 
        LDL     R5,#$a6    ; Set R5=$00a6
855 
        LDH     R5,#$c3    ; Set R5=$c3a6
856 
        LDL     R4,#$ff    ; Set R4=$00ff
857 
        LDH     R4,#$fa    ; Set R4=$faff
858 
        BFINSX  R4,R5,R6   ; R4=$f3ff
859 
        BPL     _FAIL4     ; Negative Flag should be set
860 
        BEQ     _FAIL4     ; Zero Flag should be clear
861 
        BVS     _FAIL4     ; Overflow Flag should be clear
862 
        BCS     _FAIL4     ; Carry Flag should be clear
863 
        LDL     R7,#$ff    ; R7=$00ff
864 
        LDH     R7,#$f3    ; R7=$f3ff
865 
        SUB     R0,R7,R4   ; Compare R7 to R4
866 
        BNE     _FAIL4
867 
 
868 
        LDL     R6,#$70    ; Set offset to 0 and width to 7(8 bits)
869 
        BFINSX  R4,R5,R6   ; R4=$f3a6
870 
        LDL     R7,#$a6    ; R7=$00a6
871 
        LDH     R7,#$f3    ; R7=$f3a6
872 
        SUB     R0,R7,R4 ; Compare R7 to R4
873 
        BNE     _FAIL4
874 
 
875 
 
876 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
877 
        LDH     R2,#$80
878 
        LDL     R3,#$08
879 
        STB     R3,(R2,#0)
880 
 
881 
        NOP
882 
        SIF
883 
        RTS
884 
 
885 
_FAIL4
886 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
887 
        LDH     R2,#$80
888 
        LDL     R3,#$08
889 
        STB     R3,(R2,#0)
890 
 
891 
        SIF
892 
        RTS
893 
 
894 
 
895 
;-------------------------------------------------------------------------------
896 
;   Test Branch instructions
897 
;-------------------------------------------------------------------------------
898 
_START5
899 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
900 
        LDH     R2,#$80
901 
        LDL     R3,#$09    ; Checkpoint Value
902 
        STB     R3,(R2,#0)
903 
        LDL     R3,#$05    ; Thread Value
904 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
905 
 
906 
       ;Test BCC instruction  C = 0
907 
        LDL     R2,#$00
908 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
909 
        BCC     _BCC_OK1 ; Take Branch
910 
        BRA     _BR_ERR
911 
_BCC_OK1
912 
        LDL     R2,#$01
913 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=1
914 
        BCC     _BR_ERR  ; Don't take branch
915 
 
916 
 
917 
       ;Test BCS instruction  C = 1
918 
        LDL     R2,#$01
919 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=1
920 
        BCS     _BCS_OK1 ; Take Branch
921 
        BRA     _BR_ERR
922 
_BCS_OK1
923 
        LDL     R2,#$00
924 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
925 
        BCS     _BR_ERR  ; Don't take branch
926 
 
927 
 
928 
       ;Test BEQ instruction  Z = 1
929 
        LDL     R2,#$04
930 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=0, Carry=0
931 
        BEQ     _BEQ_OK1 ; Take Branch
932 
        BRA     _BR_ERR
933 
_BEQ_OK1
934 
        LDL     R2,#$00
935 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
936 
        BEQ     _BR_ERR  ; Don't take branch
937 
 
938 
 
939 
       ;Test BNE instruction  Z = 0
940 
        LDL     R2,#$00
941 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
942 
        BNE     _BNE_OK1 ; Take Branch
943 
        BRA     _BR_ERR
944 
_BNE_OK1
945 
        LDL     R2,#$04
946 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=0, Carry=0
947 
        BNE     _BR_ERR  ; Don't take branch
948 
 
949 
 
950 
       ;Test BPL instruction  N = 0
951 
        LDL     R2,#$00
952 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
953 
        BPL     _BPL_OK1 ; Take Branch
954 
        BRA     _BR_ERR
955 
_BPL_OK1
956 
        LDL     R2,#$08
957 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=0, Carry=0
958 
        BPL     _BR_ERR  ; Don't take branch
959 
 
960 
 
961 
       ;Test BMI instruction  N = 1
962 
        LDL     R2,#$08
963 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=0, Carry=0
964 
        BMI     _BMI_OK1 ; Take Branch
965 
        BRA     _BR_ERR
966 
_BMI_OK1
967 
        LDL     R2,#$00
968 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
969 
        BMI     _BR_ERR  ; Don't take branch
970 
 
971 
 
972 
       ;Test BVC instruction  V = 0
973 
        LDL     R2,#$00
974 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
975 
        BVC     _BVC_OK1 ; Take Branch
976 
        BRA     _BR_ERR
977 
_BVC_OK1
978 
        LDL     R2,#$02
979 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=1, Carry=0
980 
        BVC     _BR_ERR  ; Don't take branch
981 
 
982 
 
983 
       ;Test BVS instruction  V = 1
984 
        LDL     R2,#$02
985 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=1, Carry=0
986 
        BVS     _BVS_OK1 ; Take Branch
987 
        BRA     _BR_ERR
988 
_BVS_OK1
989 
        LDL     R2,#$00
990 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
991 
        BVS     _BR_ERR  ; Don't take branch
992 
 
993 
 
994 
       ;Test BLS instruction  C | Z = 1
995 
        LDL     R2,#$01
996 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=1
997 
        BLS     _BLS_OK1 ; Take Branch
998 
        BRA     _BR_ERR
999 
_BLS_OK1
1000 
        LDL     R2,#$04
1001 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=0, Carry=0
1002 
        BLS     _BLS_OK2 ; Take Branch
1003 
        BRA     _BR_ERR
1004 
_BLS_OK2
1005 
        LDL     R2,#$00
1006 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=0
1007 
        BLS     _BR_ERR  ; Don't take branch
1008 
 
1009 
 
1010 
       ;Test BGE instruction  N ^ V = 0
1011 
        LDL     R2,#$0a
1012 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=0
1013 
        BGE     _BGE_OK1 ; Take Branch
1014 
        BRA     _BR_ERR
1015 
_BGE_OK1
1016 
        LDL     R2,#$05
1017 
        TFR     CCR,R2   ; Negative=0, Zero=1, Overflow=0, Carry=1
1018 
        BGE     _BGE_OK2 ; Take Branch
1019 
        BRA     _BR_ERR
1020 
_BGE_OK2
1021 
        LDL     R2,#$08
1022 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=0, Carry=0
1023 
        BGE     _BR_ERR  ; Don't take branch
1024 
 
1025 
 
1026 
        ;Test BHI instruction  Z | C = 0
1027 
        LDL     R2,#$0a
1028 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=0
1029 
        BHI     _BHI_OK1 ; Take Branch
1030 
        BRA     _BR_ERR
1031 
_BHI_OK1
1032 
        LDL     R2,#$0b
1033 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=1
1034 
        BHI     _BR_ERR  ; Don't take branch
1035 
 
1036 
        LDL     R2,#$0e
1037 
        TFR     CCR,R2   ; Negative=1, Zero=1, Overflow=1, Carry=0
1038 
        BHI     _BR_ERR  ; Don't take branch
1039 
 
1040 
 
1041 
       ;Test BGT instruction  Z | (N ^ V) = 0
1042 
        LDL     R2,#$0a
1043 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=1, Carry=0
1044 
        BGT     _BGT_OK1 ; Take Branch
1045 
        BRA     _BR_ERR
1046 
_BGT_OK1
1047 
        LDL     R2,#$01
1048 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=0, Carry=1
1049 
        BGT     _BGT_OK2 ; Take Branch
1050 
        BRA     _BR_ERR
1051 
_BGT_OK2
1052 
        LDL     R2,#$0e
1053 
        TFR     CCR,R2   ; Negative=1, Zero=1, Overflow=1, Carry=0
1054 
        BGT     _BR_ERR  ; Don't take branch
1055 
 
1056 
        LDL     R2,#$02
1057 
        TFR     CCR,R2   ; Negative=0, Zero=0, Overflow=1, Carry=0
1058 
        BGT     _BR_ERR  ; Don't take branch
1059 
 
1060 
        LDL     R2,#$08
1061 
        TFR     CCR,R2   ; Negative=1, Zero=0, Overflow=0, Carry=0
1062 
        BGT     _BR_ERR  ; Don't take branch
1063 
 
1064 
 
1065 
        BRA     BRA_FWARD
1066 
 
1067 
 
1068 
_BR_ERR
1069 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
1070 
        LDH     R2,#$80
1071 
        LDL     R3,#$0a
1072 
        STB     R3,(R2,#0)
1073 
 
1074 
        SIF
1075 
        RTS
1076 
 
1077 
_BRA_OK
1078 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1079 
        LDH     R2,#$80
1080 
        LDL     R3,#$0a
1081 
        STB     R3,(R2,#0)
1082 
 
1083 
        SIF
1084 
        RTS
1085 
 
1086 
BRA_FWARD
1087 
        BRA     _BRA_OK    ; Test backward branch caculation
1088 
 
1089 
 
1090 
;-------------------------------------------------------------------------------
1091 
;   Test Subroutine Call and return instructions
1092 
;-------------------------------------------------------------------------------
1093 
_START6
1094 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1095 
        LDH     R2,#$80
1096 
        LDL     R3,#$0b    ; Checkpoint Value
1097 
        STB     R3,(R2,#0)
1098 
        LDL     R3,#$06    ; Thread Value
1099 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
1100 
 
1101 
        LDL     R4,#$00
1102 
        TFR     R5,PC      ; Subroutine Call
1103 
        BRA     SUB_TST
1104 
 
1105 
RET_SUB
1106 
 
1107 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1108 
        LDH     R2,#$80
1109 
        LDL     R3,#$0c
1110 
        STB     R3,(R2,#0)
1111 
 
1112 
        SIF
1113 
        RTS
1114 
 
1115 
_FAIL6
1116 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
1117 
        LDH     R2,#$80
1118 
        LDL     R3,#$0c
1119 
        STB     R3,(R2,#0)
1120 
 
1121 
        SIF
1122 
        RTS
1123 
 
1124 
SUB_TST
1125 
        LDL     R4,#$88    ; If we branch to far then the wrong data will get loaded
1126 
        LDH     R4,#$99    ;  and we'll make a bad compare to cause test to fail
1127 
        LDL     R7,#$88    ; R7=$0088
1128 
        LDH     R7,#$99    ; R7=$9988
1129 
        SUB     R0,R7,R4   ; Compare R7 to R4
1130 
        BNE     _FAIL6
1131 
        JAL     R5         ; Jump to return address
1132 
 
1133 
;-------------------------------------------------------------------------------
1134 
;   Test 16 bit Addition and Substract instructions
1135 
;-------------------------------------------------------------------------------
1136 
_START7
1137 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1138 
        LDH     R2,#$80
1139 
        LDL     R3,#$0d    ; Checkpoint Value
1140 
        STB     R3,(R2,#0)
1141 
        LDL     R3,#$07    ; Thread Value
1142 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
1143 
 
1144 
       ;Test SUB instruction
1145 
        LDL     R4,#$0f    ; R4=$000f
1146 
        LDH     R4,#$01    ; R4=$010f
1147 
        LDL     R7,#$0e    ; R7=$000e
1148 
        LDH     R7,#$01    ; R7=$010e
1149 
        LDL     R2,#$0f
1150 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=1, Carry=1
1151 
        SUB     R1,R4,R7   ; R4 - R7 => R1
1152 
        BMI     _FAIL7     ; Negative Flag should be clear
1153 
        BEQ     _FAIL7     ; Zero Flag should be clear
1154 
        BVS     _FAIL7     ; Overflow Flag should be clear
1155 
        BCS     _FAIL7     ; Carry Flag should be clear
1156 
        LDL     R3,#$01    ; R3=$0001
1157 
        SUB     R0,R1,R3   ; Compare R1 to R3
1158 
        BNE     _FAIL7
1159 
 
1160 
        LDL     R7,#$0f    ; R7=$000f
1161 
        LDH     R7,#$01    ; R7=$010f
1162 
        LDL     R2,#$0b
1163 
        TFR     CCR,R2     ; Negative=1, Zero=0, Overflow=1, Carry=1
1164 
        SUB     R1,R4,R7   ; R4 - R7 => R1
1165 
        BMI     _FAIL7     ; Negative Flag should be clear
1166 
        BNE     _FAIL7     ; Zero Flag should be set
1167 
        BVS     _FAIL7     ; Overflow Flag should be clear
1168 
        BCS     _FAIL7     ; Carry Flag should be clear
1169 
 
1170 
 
1171 
       ;Test SBC instruction
1172 
        LDL     R4,#$11    ; R4=$0011
1173 
        LDH     R4,#$01    ; R4=$0111
1174 
        LDL     R7,#$0e    ; R7=$000e
1175 
        LDH     R7,#$01    ; R7=$010e
1176 
        LDL     R2,#$0f
1177 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=1, Carry=1
1178 
        SBC     R1,R4,R7   ; R4 - R7 => R1
1179 
        BMI     _FAIL7     ; Negative Flag should be clear
1180 
        BEQ     _FAIL7     ; Zero Flag should be clear
1181 
        BVS     _FAIL7     ; Overflow Flag should be clear
1182 
        BCS     _FAIL7     ; Carry Flag should be clear
1183 
        LDL     R3,#$02    ; R3=$0002
1184 
        SUB     R0,R1,R3   ; Compare R1 to R3
1185 
        BNE     _FAIL7
1186 
 
1187 
        LDL     R4,#$0f    ; R4=$000f
1188 
        LDH     R4,#$01    ; R4=$010f
1189 
        LDL     R7,#$0f    ; R7=$000f
1190 
        LDH     R7,#$01    ; R7=$010f
1191 
        LDL     R2,#$0a
1192 
        TFR     CCR,R2     ; Negative=1, Zero=0, Overflow=1, Carry=0
1193 
        SBC     R1,R4,R7   ; R4 - R7 => R1
1194 
        BMI     _FAIL7     ; Negative Flag should be clear
1195 
        BNE     _FAIL7     ; Zero Flag should be set
1196 
        BVS     _FAIL7     ; Overflow Flag should be clear
1197 
        BCS     _FAIL7     ; Carry Flag should be clear
1198 
 
1199 
 
1200 
       ;Test ADD instruction
1201 
        LDL     R4,#$0f    ; R4=$000f
1202 
        LDH     R4,#$70    ; R4=$700f
1203 
        LDL     R7,#$01    ; R7=$0001
1204 
        LDH     R7,#$10    ; R7=$1001
1205 
        LDL     R2,#$05
1206 
        TFR     CCR,R2     ; Negative=0, Zero=1, Overflow=0, Carry=1
1207 
        ADD     R1,R4,R7   ; R4 + R7 => R1
1208 
        BPL     _FAIL7     ; Negative Flag should be set
1209 
        BEQ     _FAIL7     ; Zero Flag should be clear
1210 
        BVC     _FAIL7     ; Overflow Flag should be set
1211 
        BCS     _FAIL7     ; Carry Flag should be clear
1212 
        LDL     R3,#$10    ; R3=$0010
1213 
        LDH     R3,#$80    ; R3=$8010
1214 
        SUB     R0,R1,R3   ; Compare R1 to R3
1215 
        BNE     _FAIL7
1216 
 
1217 
        LDL     R4,#$00    ; R4=$0000
1218 
        LDH     R4,#$80    ; R4=$8000
1219 
        LDL     R7,#$00    ; R7=$0000
1220 
        LDH     R7,#$80    ; R7=$8000
1221 
        LDL     R2,#$0f
1222 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=0, Carry=0
1223 
        ADD     R1,R4,R7   ; R4 + R7 => R1
1224 
        BMI     _FAIL7     ; Negative Flag should be clear
1225 
        BNE     _FAIL7     ; Zero Flag should be set
1226 
        BVC     _FAIL7     ; Overflow Flag should be set
1227 
        BCC     _FAIL7     ; Carry Flag should be set
1228 
        SUB     R0,R1,R0   ; Compare R1 to R0(Zero)
1229 
        BNE     _FAIL7
1230 
 
1231 
 
1232 
       ;Test ADC instruction
1233 
        LDL     R4,#$0f    ; R4=$000f
1234 
        LDH     R4,#$70    ; R4=$700f
1235 
        LDL     R7,#$01    ; R7=$0001
1236 
        LDH     R7,#$10    ; R7=$1001
1237 
        LDL     R2,#$05
1238 
        TFR     CCR,R2     ; Negative=0, Zero=1, Overflow=0, Carry=1
1239 
        ADC     R1,R4,R7   ; R4 + R7 => R1
1240 
        BPL     _FAIL7     ; Negative Flag should be set
1241 
        BEQ     _FAIL7     ; Zero Flag should be clear
1242 
        BVC     _FAIL7     ; Overflow Flag should be set
1243 
        BCS     _FAIL7     ; Carry Flag should be clear
1244 
        LDL     R3,#$11    ; R3=$0011
1245 
        LDH     R3,#$80    ; R3=$8011
1246 
        SUB     R0,R1,R3   ; Compare R1 to R3
1247 
        BNE     _FAIL7
1248 
 
1249 
        LDL     R4,#$00    ; R4=$0000
1250 
        LDH     R4,#$80    ; R4=$8000
1251 
        LDL     R7,#$00    ; R7=$0000
1252 
        LDH     R7,#$80    ; R7=$8000
1253 
        LDL     R2,#$0c
1254 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=0, Carry=0
1255 
        ADC     R1,R4,R7   ; R4 + R7 => R1
1256 
        BMI     _FAIL7     ; Negative Flag should be clear
1257 
        BNE     _FAIL7     ; Zero Flag should be set
1258 
        BVC     _FAIL7     ; Overflow Flag should be set
1259 
        BCC     _FAIL7     ; Carry Flag should be set
1260 
        SUB     R0,R1,R0   ; Compare R1 to R0(Zero)
1261 
        BNE     _FAIL7
1262 
 
1263 
 
1264 
_END_7
1265 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1266 
        LDH     R2,#$80
1267 
        LDL     R3,#$0e
1268 
        STB     R3,(R2,#0)
1269 
 
1270 
        SIF
1271 
        RTS
1272 
 
1273 
_FAIL7
1274 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
1275 
        LDH     R2,#$80
1276 
        LDL     R3,#$0e
1277 
        STB     R3,(R2,#0)
1278 
 
1279 
        SIF
1280 
        RTS
1281 
 
1282 
;-------------------------------------------------------------------------------
1283 
;   Test 8 bit Addition and Substract instructions
1284 
;-------------------------------------------------------------------------------
1285 
_START8
1286 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1287 
        LDH     R2,#$80
1288 
        LDL     R3,#$0f    ; Checkpoint Value
1289 
        STB     R3,(R2,#0)
1290 
        LDL     R3,#$08    ; Thread Value
1291 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
1292 
 
1293 
       ;Test SUBL instruction
1294 
        LDL     R5,#$0f    ; R5=$000f
1295 
        LDL     R2,#$0f
1296 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=1, Carry=1
1297 
        SUBL    R5,#$0e    ; R5 - $0e => R5
1298 
        BMI     _FAIL8     ; Negative Flag should be clear
1299 
        BEQ     _FAIL8     ; Zero Flag should be clear
1300 
        BVS     _FAIL8     ; Overflow Flag should be clear
1301 
        BCS     _FAIL8     ; Carry Flag should be clear
1302 
        LDL     R3,#$01    ; R3=$0001
1303 
        SUB     R0,R5,R3   ; Compare R5 to R3
1304 
        BNE     _FAIL8
1305 
 
1306 
        LDL     R7,#$0f    ; R7=$000f
1307 
        LDL     R2,#$0d
1308 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=1, Carry=0
1309 
        SUBL    R7,#$10    ; R7 - $10 => R7
1310 
        BPL     _FAIL8     ; Negative Flag should be set
1311 
        BEQ     _FAIL8     ; Zero Flag should be clear
1312 
        BVS     _FAIL8     ; Overflow Flag should be clear
1313 
        BCC     _FAIL8     ; Carry Flag should be set
1314 
 
1315 
       ;Test SUBH instruction
1316 
        LDL     R6,#$11    ; R4=$0011
1317 
        LDH     R6,#$81    ; R4=$8111
1318 
        LDL     R2,#$0d
1319 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=0, Carry=1
1320 
        SUBH    R6,#$70    ; R6 - $70 => R6
1321 
        BMI     _FAIL8     ; Negative Flag should be clear
1322 
        BEQ     _FAIL8     ; Zero Flag should be clear
1323 
        BVC     _FAIL8     ; Overflow Flag should be set
1324 
        BCS     _FAIL8     ; Carry Flag should be clear
1325 
        LDL     R3,#$11    ; R3=$0011
1326 
        LDH     R3,#$11    ; R3=$1111
1327 
        SUB     R0,R6,R3   ; Compare R6 to R3
1328 
        BNE     _FAIL8
1329 
 
1330 
        LDL     R6,#$00    ; R6=$0000
1331 
        LDH     R6,#$01    ; R6=$0100
1332 
        LDL     R2,#$06
1333 
        TFR     CCR,R2     ; Negative=0, Zero=1, Overflow=1, Carry=0
1334 
        SUBH    R6,#$02    ; R6 - $70 => R6
1335 
        BPL     _FAIL8     ; Negative Flag should be set
1336 
        BEQ     _FAIL8     ; Zero Flag should be clear
1337 
        BVS     _FAIL8     ; Overflow Flag should be clear
1338 
        BCC     _FAIL8     ; Carry Flag should be set
1339 
 
1340 
 
1341 
       ;Test CMPL instruction
1342 
        LDL     R5,#$0f    ; R5=$000f
1343 
        LDL     R2,#$0b
1344 
        TFR     CCR,R2     ; Negative=1, Zero=0, Overflow=1, Carry=1
1345 
        CMPL    R5,#$0f    ; R5 - $0f => R5
1346 
        BMI     _FAIL8     ; Negative Flag should be clear
1347 
        BNE     _FAIL8     ; Zero Flag should be set
1348 
        BVS     _FAIL8     ; Overflow Flag should be clear
1349 
        BCS     _FAIL8     ; Carry Flag should be clear
1350 
 
1351 
        LDL     R7,#$0f    ; R7=$000f
1352 
        LDL     R2,#$07
1353 
        TFR     CCR,R2     ; Negative=0, Zero=1, Overflow=1, Carry=1
1354 
        CMPL    R7,#$10    ; R7 - $10 => R7
1355 
        BPL     _FAIL8     ; Negative Flag should be set
1356 
        BEQ     _FAIL8     ; Zero Flag should be clear
1357 
        BVS     _FAIL8     ; Overflow Flag should be clear
1358 
        BCC     _FAIL8     ; Carry Flag should be set
1359 
 
1360 
 
1361 
       ;Test CPCH instruction
1362 
        LDL     R5,#$00    ; R5=$0000
1363 
        LDH     R5,#$01    ; R5=$0001
1364 
        LDL     R2,#$0f
1365 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=1, Carry=1
1366 
        CPCH    R5,#$00    ; R5 - $00 - carryflag => nowhere
1367 
        BMI     _FAIL8     ; Negative Flag should be clear
1368 
        BNE     _FAIL8     ; Zero Flag should be set
1369 
        BVS     _FAIL8     ; Overflow Flag should be clear
1370 
        BCS     _FAIL8     ; Carry Flag should be clear
1371 
        LDL     R2,#$06
1372 
        TFR     CCR,R2     ; Negative=0, Zero=1, Overflow=1, Carry=0
1373 
        CPCH    R5,#$02    ; R5 - $00 - carryflag => nowhere
1374 
        BPL     _FAIL8     ; Negative Flag should be set
1375 
        BEQ     _FAIL8     ; Zero Flag should be clear
1376 
        BVS     _FAIL8     ; Overflow Flag should be clear
1377 
        BCC     _FAIL8     ; Carry Flag should be set
1378 
 
1379 
 
1380 
       ;Test ADDH instruction
1381 
        LDL     R5,#$0f    ; R5=$000f
1382 
        LDH     R5,#$70    ; R5=$700f
1383 
        LDL     R2,#$0e
1384 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=1, Carry=0
1385 
        ADDH    R5,#$a0    ; R5 + $a0 => R5
1386 
        BMI     _FAIL8     ; Negative Flag should be clear
1387 
        BEQ     _FAIL8     ; Zero Flag should be clear
1388 
        BVS     _FAIL8     ; Overflow Flag should be clear
1389 
        BCC     _FAIL8     ; Carry Flag should be set
1390 
        LDL     R3,#$0f    ; R3=$000f
1391 
        LDH     R3,#$10    ; R3=$100f
1392 
        SUB     R0,R5,R3   ; Compare R5 to R3
1393 
        BNE     _FAIL8
1394 
 
1395 
        LDL     R2,#$07
1396 
        TFR     CCR,R2     ; Negative=0, Zero=1, Overflow=1, Carry=1
1397 
        ADDH    R5,#$70    ; R5 + $70 => R5
1398 
        BPL     _FAIL8     ; Negative Flag should be set
1399 
        BEQ     _FAIL8     ; Zero Flag should be clear
1400 
        BVC     _FAIL8     ; Overflow Flag should be set
1401 
        BCS     _FAIL8     ; Carry Flag should be clear
1402 
        LDL     R3,#$0f    ; R3=$000f
1403 
        LDH     R3,#$80    ; R3=$800f
1404 
        SUB     R0,R5,R3   ; Compare R5 to R3
1405 
        BNE     _FAIL8
1406 
 
1407 
 
1408 
       ;Test ADDL instruction
1409 
        LDL     R4,#$ff    ; R4=$00ff
1410 
        LDH     R4,#$70    ; R4=$70ff
1411 
        LDL     R2,#$0e
1412 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=1, Carry=0
1413 
        ADDL    R4,#$01    ; R4 + $01 => R4
1414 
        BMI     _FAIL8     ; Negative Flag should be clear
1415 
        BEQ     _FAIL8     ; Zero Flag should be clear
1416 
        BVS     _FAIL8     ; Overflow Flag should be clear
1417 
        BCC     _FAIL8     ; Carry Flag should be set
1418 
        LDL     R5,#$00    ; R5=$0000
1419 
        LDH     R5,#$71    ; R5=$7100
1420 
        SUB     R0,R4,R5   ; Compare R4 to R5
1421 
        BNE     _FAIL8
1422 
 
1423 
        LDL     R4,#$8e    ; R4=$008e
1424 
        LDH     R4,#$7f    ; R4=$7f8e
1425 
        LDL     R2,#$0c
1426 
        TFR     CCR,R2     ; Negative=1, Zero=1, Overflow=0, Carry=0
1427 
        ADDL    R4,#$81    ; R4 + $81 => R4
1428 
        BPL     _FAIL8     ; Negative Flag should be set
1429 
        BEQ     _FAIL8     ; Zero Flag should be clear
1430 
        BVC     _FAIL8     ; Overflow Flag should be set
1431 
        BCC     _FAIL8     ; Carry Flag should be set
1432 
        LDL     R6,#$0f    ; R6=$000f
1433 
        LDH     R6,#$80    ; R6=$800f
1434 
        SUB     R0,R4,R6   ; Compare R4 to R6
1435 
        BNE     _FAIL8
1436 
 
1437 
 
1438 
_END_8
1439 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1440 
        LDH     R2,#$80
1441 
        LDL     R3,#$10
1442 
        STB     R3,(R2,#0)
1443 
 
1444 
        SIF
1445 
        RTS
1446 
 
1447 
_FAIL8
1448 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
1449 
        LDH     R2,#$80
1450 
        LDL     R3,#$10
1451 
        STB     R3,(R2,#0)
1452 
 
1453 
        SIF
1454 
        RTS
1455 
 
1456 
 
1457 
;-------------------------------------------------------------------------------
1458 
;   Test Load and Store instructions
1459 
;-------------------------------------------------------------------------------
1460 
_START9
1461 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1462 
        LDH     R2,#$80
1463 
        LDL     R3,#$11    ; Checkpoint Value
1464 
        STB     R3,(R2,#0)
1465 
        LDL     R3,#$09    ; Thread Value
1466 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
1467 
 
1468 
        LDL     R1,#$aa    ; R1=$00aa
1469 
        LDH     R1,#$7f    ; R1=$7faa
1470 
        LDL     R2,#$55    ; R2=$0055
1471 
        LDH     R2,#$6f    ; R2=$6f55
1472 
        LDL     R3,#$66    ; R3=$0066
1473 
        LDH     R3,#$5f    ; R3=$5f66
1474 
        LDL     R7,#$ff    ; R7=$00ff
1475 
        LDH     R7,#$ff    ; R7=$ffff
1476 
 
1477 
        ;Test STB/LDB instruction
1478 
        STB     R1,(R0,#$00)    ;
1479 
        STB     R2,(R0,#$01)    ;
1480 
        STB     R3,(R0,#$1f)    ;
1481 
        LDL     R4,#$00         ; R4=$0000
1482 
        LDB     R5,(R4,#$00)    ;
1483 
        LDB     R6,(R4,#$01)    ;
1484 
        LDB     R7,(R4,#$1f)    ;
1485 
        CMPL    R5,#$aa         ;
1486 
        BNE     _FAIL9
1487 
        CMPL    R6,#$55         ;
1488 
        BNE     _FAIL9
1489 
        CMPL    R7,#$66         ;
1490 
        BNE     _FAIL9
1491 
        LDL     R6,#$66         ; R6=$0066
1492 
        CMP     R6,R7           ; Make sure the high byte has been cleared
1493 
        BNE     _FAIL9
1494 
 
1495 
        ;Test STW/LDW instruction
1496 
        STW     R1,(R0,#$04)    ; Should be even offsets
1497 
        STW     R2,(R0,#$06)    ;
1498 
        STW     R3,(R0,#$0a)    ;
1499 
        LDL     R4,#$00         ; R4=$0000
1500 
        LDL     R5,#$00         ; R5=$0000
1501 
        LDL     R6,#$00         ; R6=$0000
1502 
        LDL     R7,#$00         ; R7=$0000
1503 
        LDW     R5,(R4,#$04)    ;
1504 
        LDW     R6,(R4,#$06)    ;
1505 
        LDW     R7,(R4,#$0a)    ;
1506 
        CMP     R1,R5           ;
1507 
        BNE     _FAIL9
1508 
        CMP     R2,R6           ;
1509 
        BNE     _FAIL9
1510 
        CMP     R3,R7           ;
1511 
        BNE     _FAIL9
1512 
 
1513 
        ;Test STB/LDB instruction
1514 
        LDL     R1,#$cc    ; R1=$00cc
1515 
        LDH     R1,#$1f    ; R1=$1f66
1516 
        LDL     R2,#$99    ; R2=$0099
1517 
        LDH     R2,#$2f    ; R2=$2f99
1518 
 
1519 
        LDL     R4,#$20         ; R4=$0020 - Base Address
1520 
        LDL     R5,#$02         ; R5=$0002 - even offset
1521 
        LDL     R6,#$07         ; R6=$0007 - odd offset
1522 
        STB     R1,(R4,R5)      ;
1523 
        STB     R2,(R4,R6)      ;
1524 
        LDB     R5,(R4,R5)      ;
1525 
        LDB     R6,(R4,R6)      ;
1526 
        CMPL    R5,#$cc         ;
1527 
        BNE     _FAIL9
1528 
        LDL     R3,#$99         ; R3=$0099
1529 
        CMP     R3,R6           ; Make sure the high byte has been cleared
1530 
        BNE     _FAIL9
1531 
 
1532 
        ;Test STW/LDW instruction
1533 
        LDL     R1,#$cc    ; R1=$00cc
1534 
        LDH     R1,#$1f    ; R1=$1f66
1535 
        LDL     R2,#$99    ; R2=$0099
1536 
        LDH     R2,#$2f    ; R2=$2f99
1537 
 
1538 
        LDL     R4,#$30         ; R3=$0030 - Base Address
1539 
        LDL     R5,#$02         ; R5=$0002
1540 
        LDL     R6,#$08         ; R6=$0008
1541 
        STW     R1,(R4,R5)      ;
1542 
        STW     R2,(R4,R6)      ;
1543 
        LDW     R5,(R4,R5)      ;
1544 
        LDW     R6,(R4,R6)      ;
1545 
        CMP     R5,R1           ;
1546 
        BNE     _FAIL9
1547 
        CMP     R6,R2           ;
1548 
        BNE     _FAIL9
1549 
 
1550 
        ;Test STB/LDB instruction
1551 
        LDL     R1,#$33    ; R1=$0033
1552 
        LDH     R1,#$1f    ; R1=$1f33
1553 
        LDL     R2,#$55    ; R2=$0055
1554 
        LDH     R2,#$2f    ; R2=$2f55
1555 
 
1556 
        LDL     R4,#$40         ; R4=$0040 - Base Address
1557 
        LDL     R5,#$02         ; R5=$0002 - even offset
1558 
        LDL     R6,#$07         ; R6=$0007 - odd offset
1559 
        STB     R1,(R4,R5+)     ;
1560 
        STB     R2,(R4,R6+)     ;
1561 
        CMPL    R5,#$03         ; Test for 1 byte increment
1562 
        BNE     _FAIL9
1563 
        CMPL    R6,#$08         ; Test for 1 byte increment
1564 
        BNE     _FAIL9
1565 
        LDB     R3,(R4,-R5)     ;
1566 
        LDB     R7,(R4,-R6)     ;
1567 
        CMPL    R5,#$02         ; Test for 1 byte decrement
1568 
        BNE     _FAIL9
1569 
        CMPL    R6,#$07         ; Test for 1 byte decrement
1570 
        BNE     _FAIL9
1571 
        CMPL    R3,#$33         ;
1572 
        BNE     _FAIL9
1573 
        LDL     R3,#$55         ; R3=$0055
1574 
        CMP     R3,R7           ; Make sure the high byte has been cleared
1575 
        BNE     _FAIL9
1576 
 
1577 
        ;Test STB/LDB instruction
1578 
        LDL     R1,#$66    ; R1=$0066
1579 
        LDH     R1,#$1f    ; R1=$1f66
1580 
        LDL     R2,#$99    ; R2=$0099
1581 
        LDH     R2,#$2f    ; R2=$2f99
1582 
 
1583 
        LDL     R4,#$50         ; R4=$0050 - Base Address
1584 
        LDL     R5,#$04         ; R5=$0004 - even offset
1585 
        LDL     R6,#$09         ; R6=$0009 - odd offset
1586 
        STB     R1,(R4,-R5)     ;
1587 
        STB     R2,(R4,-R6)     ;
1588 
        CMPL    R5,#$03         ; Test for 1 byte decrement
1589 
        BNE     _FAIL9
1590 
        CMPL    R6,#$08         ; Test for 1 byte decrement
1591 
        BNE     _FAIL9
1592 
        LDB     R3,(R4,R5+)     ;
1593 
        LDB     R7,(R4,R6+)     ;
1594 
        CMPL    R5,#$04         ; Test for 1 byte increment
1595 
        BNE     _FAIL9
1596 
        CMPL    R6,#$09         ; Test for 1 byte increment
1597 
        BNE     _FAIL9
1598 
        CMPL    R3,#$66         ;
1599 
        BNE     _FAIL9
1600 
        LDL     R3,#$99         ; R3=$0099
1601 
        CMP     R3,R7           ; Make sure the high byte has been cleared
1602 
        BNE     _FAIL9
1603 
 
1604 
        ;Test STW/LDW instruction
1605 
        LDL     R1,#$aa    ; R1=$00aa
1606 
        LDH     R1,#$1f    ; R1=$1faa
1607 
        LDL     R2,#$cc    ; R2=$00cc
1608 
        LDH     R2,#$2f    ; R2=$2fcc
1609 
 
1610 
        LDL     R4,#$60         ; R4=$0060 - Base Address
1611 
        LDL     R5,#$02         ; R5=$0002 - even offset
1612 
        LDL     R6,#$08         ; R6=$0008
1613 
        STW     R1,(R4,R5+)     ;
1614 
        STW     R2,(R4,R6+)     ;
1615 
        CMPL    R5,#$04         ; Test for 2 byte increment
1616 
        BNE     _FAIL9
1617 
        CMPL    R6,#$0a         ; Test for 2 byte increment
1618 
        BNE     _FAIL9
1619 
        LDW     R3,(R4,-R5)     ;
1620 
        LDW     R7,(R4,-R6)     ;
1621 
        CMPL    R5,#$02         ; Test for 2 byte decrement
1622 
        BNE     _FAIL9
1623 
        CMPL    R6,#$08         ; Test for 2 byte decrement
1624 
        BNE     _FAIL9
1625 
        CMP     R1,R3           ;
1626 
        BNE     _FAIL9
1627 
        CMP     R2,R7           ;
1628 
        BNE     _FAIL9
1629 
 
1630 
_END_9
1631 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1632 
        LDH     R2,#$80
1633 
        LDL     R3,#$12
1634 
        STB     R3,(R2,#0)
1635 
 
1636 
        SIF
1637 
        RTS
1638 
 
1639 
_FAIL9
1640 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
1641 
        LDH     R2,#$80
1642 
        LDL     R3,#$12
1643 
        STB     R3,(R2,#0)
1644 
 
1645 
        SIF
1646 
        RTS
1647 
 
1648 
 
1649 
;-------------------------------------------------------------------------------
1650 
;   Test Semaphore instructions
1651 
;-------------------------------------------------------------------------------
1652 
_START10
1653 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1654 
        LDH     R2,#$80
1655 
        LDL     R3,#$13    ; Checkpoint Value
1656 
        STB     R3,(R2,#0)
1657 
        LDL     R3,#$0a    ; Thread Value
1658 
        STB     R3,(R2,#2) ; Send Message to clear Testbench interrupt register
1659 
 
1660 
        LDL     R1,#$5     ; R1=$0005
1661 
 
1662 
        ;Test SSEM instruction
1663 
        SSEM    #7      ; semaphores
1664 
        BCC     _FAIL10 ; Should be set
1665 
        SSEM    R1      ; semaphores
1666 
        BCC     _FAIL10 ; Should be set
1667 
 
1668 
        SSEM    #6      ; semaphore has been set by host
1669 
        BCS     _FAIL10 ; Should be clear
1670 
 
1671 
        CSEM    #7      ; semaphore
1672 
        CSEM    R1      ; semaphore #5
1673 
                        ; Host will test that these semaphores are clear
1674 
 
1675 
        SSEM    #3      ; set this semaphore for the host to test
1676 
 
1677 
 
1678 
_END_10
1679 
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
1680 
        LDH     R2,#$80
1681 
        LDL     R3,#$14
1682 
        STB     R3,(R2,#0)
1683 
 
1684 
        SIF
1685 
        RTS
1686 
 
1687 
_FAIL10
1688 
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
1689 
        LDH     R2,#$80
1690 
        LDL     R3,#$14
1691 
        STB     R3,(R2,#0)
1692 
 
1693 
        SIF
1694 
        RTS
1695 
 
1696 
 
1697 
;-------------------------------------------------------------------------------
1698 
;-------------------------------------------------------------------------------
1699 
 
1700 
        TFR     R2,CCR          ; R2 = CCR
1701 
 
1702 
;empty line
1703 
 
1704 
BACK_
1705 
 
1706 
 
1707 
        SIF     R7
1708 
        BRK
1709 
 
1710 
        ORG     $8000 ; Special Testbench Addresses
1711 
_BENCH  DS.W    8
1712 
 
1713 
 
1714 
 
1715 
 

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