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rehayes |
; 345678901234567890123456789012345678901234567890123456789012345678901234567890
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; Instruction set test for xgate RISC processor core
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; Bob Hayes - Sept 1 2009
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; Version 0.1 Basic test of all instruction done. Need to improve Condition
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; Code function testing.
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CPU XGATE
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ORG $fe00
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DS.W 2 ; reserve two words at channel 0
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; channel 1
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DC.W _START ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 2
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DC.W _START2 ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 3
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DC.W _START3 ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 4
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DC.W _START4 ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 5
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DC.W _START5 ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 6
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DC.W _START6 ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 7
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DC.W _START7 ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 8
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DC.W _START8 ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 9
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DC.W _START9 ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 10
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DC.W _START10 ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 11
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 12
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 13
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 14
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 15
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 16
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 17
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 18
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 19
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 20
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 21
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 22
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 23
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 24
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 25
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 26
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 27
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 28
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 29
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 30
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 31
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 32
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 33
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 34
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 35
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 36
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 37
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 38
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 39
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 40
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 41
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 42
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 43
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 44
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 45
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 46
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 47
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 48
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 49
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 50
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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ORG $2000 ; with comment
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V_PTR EQU 123
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DC.W BACK_
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DS.W 8
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DC.B $56
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DS.B 11
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ALIGN 1
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;-------------------------------------------------------------------------------
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; Place where undefined interrupts go
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;-------------------------------------------------------------------------------
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_ERROR
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LDL R2,#$04 ; Sent Message to Testbench Error Register
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LDH R2,#$80
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LDL R3,#$ff
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STB R3,(R2,#0)
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SIF
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RTS
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;-------------------------------------------------------------------------------
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; Test Shift instructions
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;-------------------------------------------------------------------------------
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_START
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LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDH R2,#$80
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LDL R3,#$01
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STB R3,(R2,#0)
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STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
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; Test Bit Field Find First One
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LDL R5,#$01 ; R5=$0001
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LDH R5,#$4f ; R5=$4f01
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BFFO R4,R5
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BVS _FAIL ; Negative Flag should be clear
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LDL R6,#$0e ; First one should have been in bit position 14
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SUB R0,R6,R4
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BNE _FAIL
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BFFO R4,R0 ; Zero Value should set Carry Bit
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BCC _FAIL
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LDH R5,#$00 ; R5=$0001
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BFFO R4,R5
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BCS _FAIL ; Carry should be clear
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BVS _FAIL ; Overflow Flag should be clear
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SUB R0,R0,R4 ; R4 Should be zero
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BNE _FAIL
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; Test ASR instruction
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LDL R5,#$04 ; R5=$0008
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LDH R5,#$81 ; R5=$8108
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LDL R3,#$03
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ASR R5,R3 ; R5=$f000, Carry flag set
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BCC _FAIL
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BVS _FAIL ; Negative Flag should be clear
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LDL R4,#$20 ; R4=$0020
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LDH R4,#$f0 ; R4=$f020
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SUB R0,R5,R4 ; Compare R5 to R4
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BNE _FAIL
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; Test CSL insrtruction
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LDL R5,#$10 ; R5=$0010
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LDH R5,#$88 ; R5=$8810
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LDL R3,#$05
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CSL R5,R3 ; R5=$081f, Carry flag set
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BCC _FAIL
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LDL R4,#$00 ; R4=$0000
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LDH R4,#$02 ; R4=$0200
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SUB R0,R5,R4 ; Compare R5 to R4
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BNE _FAIL
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;Test CSR instruction
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LDL R5,#$88 ; R5=$0088
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LDH R5,#$10 ; R5=$1088
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LDL R3,#$04
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CSR R5,R3 ; R5=$0108, Carry flag set
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BCC _FAIL
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LDL R4,#$08 ; R4=$0008
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LDH R4,#$01 ; R4=$0108
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SUB R0,R5,R4 ; Compare R5 to R4
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BNE _FAIL
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;Test LSL instruction
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LDL R2,#$ff ; R2=$00ff
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LDH R2,#$07 ; R2=$07ff
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LDL R1,#$06
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LSL R2,R1 ; R2=$ffc0, Carry flag set
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BCC _FAIL
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LDL R4,#$c0 ; R4=$0008
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LDH R4,#$ff ; R4=$0108
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SUB R0,R2,R4 ; Compare R2 to R4
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BNE _FAIL
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;Test LSR instruction
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LDL R7,#$02 ; R7=$0002
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LDH R7,#$c3 ; R7=$c302
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LDL R6,#$02
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LSR R7,R6 ; R7=$30c0, Carry flag set
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BCC _FAIL
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LDL R4,#$c0 ; R4=$00c0
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LDH R4,#$30 ; R4=$30c0
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SUB R0,R7,R4 ; Compare R7 to R4
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BNE _FAIL
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;Test ROL instruction
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LDL R7,#$62 ; R7=$0062
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LDH R7,#$c3 ; R7=$c362
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LDL R6,#$04
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ROL R7,R6 ; R7=$362c
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BVS _FAIL ; Overflow Flag should be clear
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| 277 |
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LDL R4,#$2c ; R4=$002c
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| 278 |
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LDH R4,#$36 ; R4=$362c
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| 279 |
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SUB R0,R7,R4 ; Compare R7 to R4
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| 280 |
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BNE _FAIL
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| 281 |
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| 282 |
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;Test ROR instruction
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| 283 |
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LDL R7,#$62 ; R7=$0062
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| 284 |
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LDH R7,#$c3 ; R7=$c362
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| 285 |
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LDL R6,#$08
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| 286 |
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ROL R7,R6 ; R7=$62c3
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| 287 |
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BVS _FAIL ; Overflow Flag should be clear
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| 288 |
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LDL R4,#$c3 ; R4=$00c3
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| 289 |
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LDH R4,#$62 ; R4=$62c3
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| 290 |
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SUB R0,R7,R4 ; Compare R7 to R4
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| 291 |
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BNE _FAIL
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| 292 |
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| 293 |
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; Test ASR instruction
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| 294 |
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LDL R5,#$00 ; R5=$0000
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| 295 |
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LDH R5,#$80 ; R5=$8000
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| 296 |
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ASR R5,#0 ; R5=$ffff, Carry flag set
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| 297 |
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BCC _FAIL
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| 298 |
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BVS _FAIL ; Overflow Flag should be clear
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| 299 |
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LDL R4,#$ff ; R4=$00ff
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| 300 |
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LDH R4,#$ff ; R4=$ffff
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| 301 |
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SUB R0,R5,R4 ; Compare R5 to R4
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| 302 |
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BNE _FAIL
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| 303 |
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| 304 |
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; Test CSL insrtruction
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| 305 |
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LDL R5,#$01 ; R5=$0001
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| 306 |
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LDH R5,#$0f ; R5=$0f01
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| 307 |
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CSL R5,#0 ; R5=$0000, Carry flag set
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| 308 |
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BCC _FAIL
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| 309 |
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LDL R4,#$00 ; R4=$0000
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| 310 |
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LDH R4,#$00 ; R4=$0000
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| 311 |
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SUB R0,R5,R4 ; Compare R5 to R4
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| 312 |
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BNE _FAIL
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| 313 |
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| 314 |
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;Test CSR instruction
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| 315 |
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LDL R5,#$ff ; R5=$00ff
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| 316 |
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LDH R5,#$80 ; R5=$80ff
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| 317 |
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CSR R5,#15 ; R5=$0001, Carry flag clear
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| 318 |
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BCS _FAIL
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| 319 |
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LDL R4,#$01 ; R4=$0001
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| 320 |
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LDH R4,#$00 ; R4=$0001
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| 321 |
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SUB R0,R5,R4 ; Compare R5 to R4
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| 322 |
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BNE _FAIL
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| 323 |
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| 324 |
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;Test LSL instruction
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| 325 |
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LDL R2,#$1a ; R2=$001a
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| 326 |
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LDH R2,#$ff ; R2=$ff1a
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| 327 |
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LSL R2,#12 ; R2=$a000, Carry flag set
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| 328 |
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BCC _FAIL
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| 329 |
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LDL R4,#$00 ; R4=$0000
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| 330 |
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LDH R4,#$a0 ; R4=$a000
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| 331 |
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SUB R0,R2,R4 ; Compare R2 to R4
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| 332 |
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BNE _FAIL
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| 333 |
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| 334 |
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;Test LSR instruction
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| 335 |
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LDL R7,#$8f ; R7=$008f
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| 336 |
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LDH R7,#$b2 ; R7=$b18f
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| 337 |
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LSR R7,#8 ; R7=$00b0, Carry flag set
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| 338 |
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BCC _FAIL
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| 339 |
|
|
LDL R4,#$b2 ; R4=$00b0
|
| 340 |
|
|
LDH R4,#$00 ; R4=$00b0
|
| 341 |
|
|
SUB R0,R7,R4 ; Compare R7 to R4
|
| 342 |
|
|
BNE _FAIL
|
| 343 |
|
|
|
| 344 |
|
|
;Test ROL instruction
|
| 345 |
|
|
LDL R7,#$62 ; R7=$0062
|
| 346 |
|
|
LDH R7,#$c3 ; R7=$c362
|
| 347 |
|
|
ROL R7,#8 ; R7=$62c3
|
| 348 |
|
|
BVS _FAIL ; Overflow Flag should be clear
|
| 349 |
|
|
LDL R4,#$c3 ; R4=$00c3
|
| 350 |
|
|
LDH R4,#$62 ; R4=$62c3
|
| 351 |
|
|
SUB R0,R7,R4 ; Compare R7 to R4
|
| 352 |
|
|
BNE _FAIL
|
| 353 |
|
|
|
| 354 |
|
|
;Test ROR instruction
|
| 355 |
|
|
LDL R7,#$62 ; R7=$0062
|
| 356 |
|
|
LDH R7,#$c3 ; R7=$c362
|
| 357 |
|
|
ROL R7,#12 ; R7=$2c36
|
| 358 |
|
|
BVS _FAIL ; Overflow Flag should be clear
|
| 359 |
|
|
LDL R4,#$36 ; R4=$0036
|
| 360 |
|
|
LDH R4,#$2c ; R4=$2c36
|
| 361 |
|
|
SUB R0,R7,R4 ; Compare R7 to R4
|
| 362 |
|
|
BNE _FAIL
|
| 363 |
|
|
|
| 364 |
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
| 365 |
|
|
LDH R2,#$80
|
| 366 |
|
|
LDL R3,#$02
|
| 367 |
|
|
STB R3,(R2,#0)
|
| 368 |
|
|
|
| 369 |
|
|
NOP
|
| 370 |
|
|
NOP
|
| 371 |
|
|
SIF
|
| 372 |
|
|
RTS
|
| 373 |
|
|
|
| 374 |
|
|
_FAIL
|
| 375 |
|
|
LDL R2,#$04 ; Sent Message to Testbench Error Register
|
| 376 |
|
|
LDH R2,#$80
|
| 377 |
|
|
LDL R3,#$02
|
| 378 |
|
|
STB R3,(R2,#0)
|
| 379 |
|
|
|
| 380 |
|
|
SIF
|
| 381 |
|
|
RTS
|
| 382 |
|
|
|
| 383 |
|
|
;-------------------------------------------------------------------------------
|
| 384 |
|
|
; Test Logical Byte wide instructions
|
| 385 |
|
|
;-------------------------------------------------------------------------------
|
| 386 |
|
|
_START2
|
| 387 |
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
| 388 |
|
|
LDH R2,#$80
|
| 389 |
|
|
LDL R3,#$03 ; Checkpoint Value
|
| 390 |
|
|
STB R3,(R2,#0)
|
| 391 |
|
|
LDL R3,#$02 ; Thread Value
|
| 392 |
|
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
| 393 |
|
|
|
| 394 |
|
|
;Test ANDL instruction
|
| 395 |
|
|
LDL R7,#$55 ; R7=$0055
|
| 396 |
|
|
LDH R7,#$a5 ; R7=$a555
|
| 397 |
|
|
ANDL R7,#$00 ; R7=&a500
|
| 398 |
|
|
BNE _FAIL2 ; Zero Flag should be set
|
| 399 |
|
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| 400 |
|
|
BMI _FAIL2 ; Negative Flag should be clear
|
| 401 |
|
|
LDL R3,#$00 ; R3=$0000
|
| 402 |
|
|
LDH R3,#$a5 ; R3=$a500
|
| 403 |
|
|
SUB R0,R7,R3 ; Compare R7 to R3
|
| 404 |
|
|
BNE _FAIL2
|
| 405 |
|
|
LDL R7,#$c5 ; R7=$00c5
|
| 406 |
|
|
LDH R7,#$a5 ; R7=$a5c5
|
| 407 |
|
|
ANDL R7,#$80 ; R7=$a580
|
| 408 |
|
|
BPL _FAIL2 ; Negative Flag should be set
|
| 409 |
|
|
BEQ _FAIL2 ; Zero Flag should be clear
|
| 410 |
|
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| 411 |
|
|
LDL R3,#$80 ; R3=$0080
|
| 412 |
|
|
LDH R3,#$a5 ; R3=$a580
|
| 413 |
|
|
SUB R0,R7,R3 ; Compare R7 to R3
|
| 414 |
|
|
BNE _FAIL2
|
| 415 |
|
|
|
| 416 |
|
|
;Test ANDH instruction
|
| 417 |
|
|
LDL R7,#$55 ; R7=$0055
|
| 418 |
|
|
LDH R7,#$a5 ; R7=$a555
|
| 419 |
|
|
ANDH R7,#$00 ; R7=&0055
|
| 420 |
|
|
BNE _FAIL2 ; Zero Flag should be set
|
| 421 |
|
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| 422 |
|
|
BMI _FAIL2 ; Negative Flag should be clear
|
| 423 |
|
|
LDL R3,#$55 ; R3=$0000
|
| 424 |
|
|
LDH R3,#$00 ; R3=$a500
|
| 425 |
|
|
SUB R0,R7,R3 ; Compare R7 to R3
|
| 426 |
|
|
BNE _FAIL2
|
| 427 |
|
|
LDL R7,#$c5 ; R7=$00c5
|
| 428 |
|
|
LDH R7,#$a5 ; R7=$a5c5
|
| 429 |
|
|
ANDH R7,#$80 ; R7=$80c5
|
| 430 |
|
|
BPL _FAIL2 ; Negative Flag should be set
|
| 431 |
|
|
BEQ _FAIL2 ; Zero Flag should be clear
|
| 432 |
|
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| 433 |
|
|
LDL R3,#$c5 ; R3=$00c5
|
| 434 |
|
|
LDH R3,#$80 ; R3=$80c5
|
| 435 |
|
|
SUB R0,R7,R3 ; Compare R7 to R3
|
| 436 |
|
|
BNE _FAIL2
|
| 437 |
|
|
|
| 438 |
|
|
;Test BITL instruction
|
| 439 |
|
|
LDL R7,#$55 ; R7=$0055
|
| 440 |
|
|
LDH R7,#$a5 ; R7=$a555
|
| 441 |
|
|
BITL R7,#$00 ; R7=&a500
|
| 442 |
|
|
BNE _FAIL2 ; Zero Flag should be set
|
| 443 |
|
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| 444 |
|
|
BMI _FAIL2 ; Negative Flag should be clear
|
| 445 |
|
|
LDL R7,#$c5 ; R7=$00c5
|
| 446 |
|
|
LDH R7,#$a5 ; R7=$a5c5
|
| 447 |
|
|
BITL R7,#$80 ; R7=$a580
|
| 448 |
|
|
BPL _FAIL2 ; Negative Flag should be set
|
| 449 |
|
|
BEQ _FAIL2 ; Zero Flag should be clear
|
| 450 |
|
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| 451 |
|
|
|
| 452 |
|
|
;Test BITH instruction
|
| 453 |
|
|
LDL R7,#$55 ; R7=$0055
|
| 454 |
|
|
LDH R7,#$a5 ; R7=$a555
|
| 455 |
|
|
BITH R7,#$00 ; R7=&0055
|
| 456 |
|
|
BNE _FAIL2 ; Zero Flag should be set
|
| 457 |
|
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| 458 |
|
|
BMI _FAIL2 ; Negative Flag should be clear
|
| 459 |
|
|
LDL R7,#$c5 ; R7=$00c5
|
| 460 |
|
|
LDH R7,#$a5 ; R7=$a5c5
|
| 461 |
|
|
BITH R7,#$80 ; R7=$80c5
|
| 462 |
|
|
BPL _FAIL2 ; Negative Flag should be set
|
| 463 |
|
|
BEQ _FAIL2 ; Zero Flag should be clear
|
| 464 |
|
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| 465 |
|
|
|
| 466 |
|
|
;Test ORL instruction
|
| 467 |
|
|
LDL R2,#$0b
|
| 468 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
| 469 |
|
|
LDL R7,#$00 ; R7=$0000
|
| 470 |
|
|
LDH R7,#$a5 ; R7=$a500
|
| 471 |
|
|
ORL R7,#$00 ; R7=&a500
|
| 472 |
|
|
BMI _FAIL2 ; Negative Flag should be clear
|
| 473 |
|
|
BNE _FAIL2 ; Zero Flag should be set
|
| 474 |
|
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| 475 |
|
|
BCC _FAIL2 ; Carry Flag should be set
|
| 476 |
|
|
LDL R3,#$00 ; R3=$0000
|
| 477 |
|
|
LDH R3,#$a5 ; R3=$a500
|
| 478 |
|
|
SUB R0,R7,R3 ; Compare R7 to R3
|
| 479 |
|
|
BNE _FAIL2
|
| 480 |
|
|
LDL R2,#$06
|
| 481 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
|
| 482 |
|
|
LDL R7,#$9f ; R7=$009f
|
| 483 |
|
|
LDH R7,#$a5 ; R7=$a59f
|
| 484 |
|
|
ORL R7,#$60 ; R7=$a5ff
|
| 485 |
|
|
BPL _FAIL2 ; Negative Flag should be set
|
| 486 |
|
|
BEQ _FAIL2 ; Zero Flag should be clear
|
| 487 |
|
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| 488 |
|
|
BCS _FAIL2 ; Carry Flag should be clear
|
| 489 |
|
|
LDL R3,#$ff ; R3=$00ff
|
| 490 |
|
|
LDH R3,#$a5 ; R3=$a5ff
|
| 491 |
|
|
SUB R0,R7,R3 ; Compare R7 to R3
|
| 492 |
|
|
BNE _FAIL2
|
| 493 |
|
|
|
| 494 |
|
|
;Test ORH instruction
|
| 495 |
|
|
LDL R2,#$0b
|
| 496 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
| 497 |
|
|
LDL R7,#$88 ; R7=$0088
|
| 498 |
|
|
LDH R7,#$00 ; R7=$0088
|
| 499 |
|
|
ORH R7,#$00 ; R7=&0088
|
| 500 |
|
|
BMI _FAIL2 ; Negative Flag should be clear
|
| 501 |
|
|
BNE _FAIL2 ; Zero Flag should be set
|
| 502 |
|
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| 503 |
|
|
BCC _FAIL2 ; Carry Flag should be set
|
| 504 |
|
|
LDL R3,#$88 ; R3=$0088
|
| 505 |
|
|
LDH R3,#$00 ; R3=$0088
|
| 506 |
|
|
SUB R0,R7,R3 ; Compare R7 to R3
|
| 507 |
|
|
BNE _FAIL2
|
| 508 |
|
|
LDL R2,#$06
|
| 509 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
|
| 510 |
|
|
LDL R7,#$36 ; R7=$0036
|
| 511 |
|
|
LDH R7,#$a1 ; R7=$a136
|
| 512 |
|
|
ORH R7,#$50 ; R7=$f136
|
| 513 |
|
|
BPL _FAIL2 ; Negative Flag should be set
|
| 514 |
|
|
BEQ _FAIL2 ; Zero Flag should be clear
|
| 515 |
|
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| 516 |
|
|
BCS _FAIL2 ; Carry Flag should be clear
|
| 517 |
|
|
LDL R3,#$36 ; R3=$0036
|
| 518 |
|
|
LDH R3,#$f1 ; R3=$f136
|
| 519 |
|
|
SUB R0,R7,R3 ; Compare R7 to R3
|
| 520 |
|
|
BNE _FAIL2
|
| 521 |
|
|
|
| 522 |
|
|
;Test XNORL instruction
|
| 523 |
|
|
LDL R2,#$0b
|
| 524 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
| 525 |
|
|
LDL R7,#$c3 ; R7=$00c3
|
| 526 |
|
|
LDH R7,#$96 ; R7=$96c3
|
| 527 |
|
|
XNORL R7,#$3c ; R7=$9600
|
| 528 |
|
|
BMI _FAIL2 ; Negative Flag should be clear
|
| 529 |
|
|
BNE _FAIL2 ; Zero Flag should be set
|
| 530 |
|
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| 531 |
|
|
BCC _FAIL2 ; Carry Flag should be set
|
| 532 |
|
|
LDL R3,#$00 ; R3=$0000
|
| 533 |
|
|
LDH R3,#$96 ; R3=$9600
|
| 534 |
|
|
SUB R0,R7,R3 ; Compare R7 to R3
|
| 535 |
|
|
BNE _FAIL2
|
| 536 |
|
|
LDL R2,#$06
|
| 537 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
|
| 538 |
|
|
LDL R6,#$00 ; R6=$0000
|
| 539 |
|
|
LDH R6,#$a5 ; R6=$a500
|
| 540 |
|
|
XNORL R6,#$73 ; R6=$a58c
|
| 541 |
|
|
BPL _FAIL2 ; Negative Flag should be set
|
| 542 |
|
|
BEQ _FAIL2 ; Zero Flag should be clear
|
| 543 |
|
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| 544 |
|
|
BCS _FAIL2 ; Carry Flag should be clear
|
| 545 |
|
|
LDL R3,#$8c ; R3=$008c
|
| 546 |
|
|
LDH R3,#$a5 ; R3=$a58c
|
| 547 |
|
|
SUB R0,R6,R3 ; Compare R6 to R3
|
| 548 |
|
|
BNE _FAIL2
|
| 549 |
|
|
|
| 550 |
|
|
;Test XNORH instruction
|
| 551 |
|
|
LDL R2,#$0b
|
| 552 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
| 553 |
|
|
LDL R7,#$c3 ; R7=$00c3
|
| 554 |
|
|
LDH R7,#$96 ; R7=$96c3
|
| 555 |
|
|
XNORH R7,#$69 ; R7=$00c3
|
| 556 |
|
|
BMI _FAIL2 ; Negative Flag should be clear
|
| 557 |
|
|
BNE _FAIL2 ; Zero Flag should be set
|
| 558 |
|
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| 559 |
|
|
BCC _FAIL2 ; Carry Flag should be set
|
| 560 |
|
|
LDL R3,#$c3 ; R3=$00c3
|
| 561 |
|
|
LDH R3,#$00 ; R3=$00c3
|
| 562 |
|
|
SUB R0,R7,R3 ; Compare R7 to R3
|
| 563 |
|
|
BNE _FAIL2
|
| 564 |
|
|
LDL R2,#$06
|
| 565 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
|
| 566 |
|
|
LDL R6,#$66 ; R6=$0066
|
| 567 |
|
|
LDH R6,#$66 ; R6=$6666
|
| 568 |
|
|
XNORH R6,#$66 ; R6=$ff66
|
| 569 |
|
|
BPL _FAIL2 ; Negative Flag should be set
|
| 570 |
|
|
BEQ _FAIL2 ; Zero Flag should be clear
|
| 571 |
|
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| 572 |
|
|
BCS _FAIL2 ; Carry Flag should be clear
|
| 573 |
|
|
LDL R3,#$66 ; R3=$0066
|
| 574 |
|
|
LDH R3,#$ff ; R3=$ff66
|
| 575 |
|
|
SUB R0,R6,R3 ; Compare R6 to R3
|
| 576 |
|
|
BNE _FAIL2
|
| 577 |
|
|
|
| 578 |
|
|
|
| 579 |
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
| 580 |
|
|
LDH R2,#$80
|
| 581 |
|
|
LDL R3,#$04
|
| 582 |
|
|
STB R3,(R2,#0)
|
| 583 |
|
|
|
| 584 |
|
|
SIF
|
| 585 |
|
|
RTS
|
| 586 |
|
|
|
| 587 |
|
|
_FAIL2
|
| 588 |
|
|
LDL R2,#$04 ; Sent Message to Testbench Error Register
|
| 589 |
|
|
LDH R2,#$80
|
| 590 |
|
|
LDL R3,#$04
|
| 591 |
|
|
STB R3,(R2,#0)
|
| 592 |
|
|
|
| 593 |
|
|
SIF
|
| 594 |
|
|
RTS
|
| 595 |
|
|
|
| 596 |
|
|
;-------------------------------------------------------------------------------
|
| 597 |
|
|
; Test Logical Word Wide instructions
|
| 598 |
|
|
;-------------------------------------------------------------------------------
|
| 599 |
|
|
_START3
|
| 600 |
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
| 601 |
|
|
LDH R2,#$80
|
| 602 |
|
|
LDL R3,#$05 ; Checkpoint Value
|
| 603 |
|
|
STB R3,(R2,#0)
|
| 604 |
|
|
LDL R3,#$03 ; Thread Value
|
| 605 |
|
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
| 606 |
|
|
|
| 607 |
|
|
;Test SEX instruction
|
| 608 |
|
|
LDL R2,#$0b
|
| 609 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
| 610 |
|
|
LDL R3,#$00 ; R3=$0000
|
| 611 |
|
|
LDH R3,#$ff ; R3=$ff00
|
| 612 |
|
|
SEX R3 ; R3=$0000
|
| 613 |
|
|
BMI _FAIL3 ; Negative Flag should be clear
|
| 614 |
|
|
BNE _FAIL3 ; Zero Flag should be set
|
| 615 |
|
|
BVS _FAIL3 ; Overflow Flag should be clear
|
| 616 |
|
|
BCC _FAIL3 ; Carry Flag should be set
|
| 617 |
|
|
LDL R6,#$00 ; R6=$0000
|
| 618 |
|
|
LDH R6,#$00 ; R6=$0000
|
| 619 |
|
|
SUB R0,R6,R3 ; Compare R6 to R3
|
| 620 |
|
|
BNE _FAIL3
|
| 621 |
|
|
LDL R2,#$06
|
| 622 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
|
| 623 |
|
|
LDL R6,#$83 ; R6=$0083
|
| 624 |
|
|
LDH R6,#$00 ; R6=$0083
|
| 625 |
|
|
SEX R6 ; R6=$ff83
|
| 626 |
|
|
BPL _FAIL3 ; Negative Flag should be set
|
| 627 |
|
|
BEQ _FAIL3 ; Zero Flag should be clear
|
| 628 |
|
|
BVS _FAIL3 ; Overflow Flag should be clear
|
| 629 |
|
|
BCS _FAIL3 ; Carry Flag should be clear
|
| 630 |
|
|
LDL R3,#$83 ; R3=$0083
|
| 631 |
|
|
LDH R3,#$ff ; R3=$ff83
|
| 632 |
|
|
SUB R0,R6,R3 ; Compare R6 to R3
|
| 633 |
|
|
BNE _FAIL3
|
| 634 |
|
|
|
| 635 |
|
|
;Test PAR instruction
|
| 636 |
|
|
LDL R2,#$0a
|
| 637 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
| 638 |
|
|
LDL R4,#$00 ; R4=$0000
|
| 639 |
|
|
LDH R4,#$00 ; R4=$0000
|
| 640 |
|
|
PAR R4 ; R4=$0000
|
| 641 |
|
|
BMI _FAIL3 ; Negative Flag should be clear
|
| 642 |
|
|
BNE _FAIL3 ; Zero Flag should be set
|
| 643 |
|
|
BVS _FAIL3 ; Overflow Flag should be clear
|
| 644 |
|
|
BCS _FAIL3 ; Carry Flag should be clear
|
| 645 |
|
|
LDL R6,#$00 ; R6=$0000
|
| 646 |
|
|
LDH R6,#$00 ; R6=$0000
|
| 647 |
|
|
SUB R0,R6,R4 ; Compare R6 to R4
|
| 648 |
|
|
BNE _FAIL3
|
| 649 |
|
|
LDL R2,#$0e
|
| 650 |
|
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
|
| 651 |
|
|
LDL R6,#$01 ; R6=$0001
|
| 652 |
|
|
LDH R6,#$03 ; R6=$0301
|
| 653 |
|
|
PAR R6 ; R6=$0301
|
| 654 |
|
|
BMI _FAIL3 ; Negative Flag should be clear
|
| 655 |
|
|
BEQ _FAIL3 ; Zero Flag should be clear
|
| 656 |
|
|
BVS _FAIL3 ; Overflow Flag should be clear
|
| 657 |
|
|
BCC _FAIL3 ; Carry Flag should be set
|
| 658 |
|
|
LDL R3,#$01 ; R3=$0001
|
| 659 |
|
|
LDH R3,#$03 ; R3=$0301
|
| 660 |
|
|
SUB R0,R6,R3 ; Compare R6 to R3
|
| 661 |
|
|
BNE _FAIL3
|
| 662 |
|
|
|
| 663 |
|
|
;Test AND instruction
|
| 664 |
|
|
LDL R2,#$0a
|
| 665 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
| 666 |
|
|
LDL R6,#$55 ; R6=$0055
|
| 667 |
|
|
LDH R6,#$aa ; R6=$aa55
|
| 668 |
|
|
LDL R5,#$aa ; R5=$00aa
|
| 669 |
|
|
LDH R5,#$55 ; R5=$55aa
|
| 670 |
|
|
AND R3,R5,R6 ; R3=$0000
|
| 671 |
|
|
BMI _FAIL3 ; Negative Flag should be clear
|
| 672 |
|
|
BNE _FAIL3 ; Zero Flag should be set
|
| 673 |
|
|
BVS _FAIL3 ; Overflow Flag should be clear
|
| 674 |
|
|
BCS _FAIL3 ; Carry Flag should be clear
|
| 675 |
|
|
SUB R0,R0,R3 ; Compare R0 to R3
|
| 676 |
|
|
BNE _FAIL3
|
| 677 |
|
|
LDL R7,#$55 ; R7=$00c5
|
| 678 |
|
|
LDH R7,#$aa ; R7=$aa55
|
| 679 |
|
|
LDL R2,#$07
|
| 680 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
|
| 681 |
|
|
AND R4,R6,R7 ; R4=$aa55
|
| 682 |
|
|
BPL _FAIL3 ; Negative Flag should be set
|
| 683 |
|
|
BEQ _FAIL3 ; Zero Flag should be clear
|
| 684 |
|
|
BVS _FAIL3 ; Overflow Flag should be clear
|
| 685 |
|
|
BCC _FAIL3 ; Carry Flag should be set
|
| 686 |
|
|
SUB R0,R4,R7 ; Compare R4 to R7
|
| 687 |
|
|
BNE _FAIL2
|
| 688 |
|
|
|
| 689 |
|
|
;Test OR instruction
|
| 690 |
|
|
LDL R2,#$0a
|
| 691 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
| 692 |
|
|
LDL R6,#$00 ; R6=$0000
|
| 693 |
|
|
LDL R5,#$00 ; R5=$0000
|
| 694 |
|
|
OR R3,R5,R6 ; R3=$0000
|
| 695 |
|
|
BMI _FAIL3 ; Negative Flag should be clear
|
| 696 |
|
|
BNE _FAIL3 ; Zero Flag should be set
|
| 697 |
|
|
BVS _FAIL3 ; Overflow Flag should be clear
|
| 698 |
|
|
BCS _FAIL3 ; Carry Flag should be clear
|
| 699 |
|
|
SUB R0,R0,R3 ; Compare R0 to R3
|
| 700 |
|
|
BNE _FAIL3
|
| 701 |
|
|
LDL R7,#$55 ; R7=$00c5
|
| 702 |
|
|
LDH R7,#$aa ; R7=$aa55
|
| 703 |
|
|
LDL R6,#$8a ; R6=$008a
|
| 704 |
|
|
LDH R6,#$10 ; R7=$108a
|
| 705 |
|
|
LDL R2,#$07
|
| 706 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
|
| 707 |
|
|
OR R4,R6,R7 ; R4=$badf
|
| 708 |
|
|
BPL _FAIL3 ; Negative Flag should be set
|
| 709 |
|
|
BEQ _FAIL3 ; Zero Flag should be clear
|
| 710 |
|
|
BVS _FAIL3 ; Overflow Flag should be clear
|
| 711 |
|
|
BCC _FAIL3 ; Carry Flag should be set
|
| 712 |
|
|
LDL R3,#$df ; R3=$00df
|
| 713 |
|
|
LDH R3,#$ba ; R3=$badf
|
| 714 |
|
|
SUB R0,R4,R3 ; Compare R6 to R3
|
| 715 |
|
|
BNE _FAIL3
|
| 716 |
|
|
|
| 717 |
|
|
;Test XNOR instruction
|
| 718 |
|
|
LDL R2,#$0a
|
| 719 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
| 720 |
|
|
LDL R1,#$55 ; R1=$0055
|
| 721 |
|
|
LDH R1,#$aa ; R1=$aa55
|
| 722 |
|
|
LDL R5,#$aa ; R5=$00aa
|
| 723 |
|
|
LDH R5,#$55 ; R5=$55aa
|
| 724 |
|
|
XNOR R3,R5,R1 ; R3=$0000
|
| 725 |
|
|
BMI _FAIL3 ; Negative Flag should be clear
|
| 726 |
|
|
BNE _FAIL3 ; Zero Flag should be set
|
| 727 |
|
|
BVS _FAIL3 ; Overflow Flag should be clear
|
| 728 |
|
|
BCS _FAIL3 ; Carry Flag should be clear
|
| 729 |
|
|
SUB R0,R0,R3 ; Compare R0 to R3
|
| 730 |
|
|
BNE _FAIL3
|
| 731 |
|
|
LDL R7,#$cc ; R7=$00cc
|
| 732 |
|
|
LDH R7,#$33 ; R7=$33cc
|
| 733 |
|
|
LDL R2,#$01 ; R2=$0001
|
| 734 |
|
|
LDH R2,#$40 ; R2=$4001
|
| 735 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
|
| 736 |
|
|
XNOR R4,R7,R2 ; R4=$8c32
|
| 737 |
|
|
BPL _FAIL3 ; Negative Flag should be set
|
| 738 |
|
|
BEQ _FAIL3 ; Zero Flag should be clear
|
| 739 |
|
|
BVS _FAIL3 ; Overflow Flag should be clear
|
| 740 |
|
|
BCC _FAIL3 ; Carry Flag should be set
|
| 741 |
|
|
LDL R3,#$32 ; R3=$0032
|
| 742 |
|
|
LDH R3,#$8c ; R3=$8c32
|
| 743 |
|
|
SUB R0,R4,R3 ; Compare R4 to R3
|
| 744 |
|
|
BNE _FAIL3
|
| 745 |
|
|
|
| 746 |
|
|
|
| 747 |
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
| 748 |
|
|
LDH R2,#$80
|
| 749 |
|
|
LDL R3,#$06
|
| 750 |
|
|
STB R3,(R2,#0)
|
| 751 |
|
|
|
| 752 |
|
|
NOP
|
| 753 |
|
|
SIF
|
| 754 |
|
|
RTS
|
| 755 |
|
|
|
| 756 |
|
|
_FAIL3
|
| 757 |
|
|
LDL R2,#$04 ; Sent Message to Testbench Error Register
|
| 758 |
|
|
LDH R2,#$80
|
| 759 |
|
|
LDL R3,#$06
|
| 760 |
|
|
STB R3,(R2,#0)
|
| 761 |
|
|
|
| 762 |
|
|
SIF
|
| 763 |
|
|
RTS
|
| 764 |
|
|
|
| 765 |
|
|
|
| 766 |
|
|
;-------------------------------------------------------------------------------
|
| 767 |
|
|
; Test Bit Field instructions
|
| 768 |
|
|
;-------------------------------------------------------------------------------
|
| 769 |
|
|
_START4
|
| 770 |
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
| 771 |
|
|
LDH R2,#$80
|
| 772 |
|
|
LDL R3,#$07 ; Checkpoint Value
|
| 773 |
|
|
STB R3,(R2,#0)
|
| 774 |
|
|
LDL R3,#$04 ; Thread Value
|
| 775 |
|
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
| 776 |
|
|
|
| 777 |
|
|
;Test BFEXT instruction
|
| 778 |
|
|
LDL R2,#$0e
|
| 779 |
|
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
|
| 780 |
|
|
LDL R6,#$34 ; Set offset to 4 and width to 3(4 bits)
|
| 781 |
|
|
LDL R5,#$a6 ; Set R5=$00a6
|
| 782 |
|
|
LDH R5,#$c3 ; Set R5=$c3a6
|
| 783 |
|
|
LDL R4,#$ff ; Set R4=$00ff
|
| 784 |
|
|
SEX R4 ; Set R4=$ffff
|
| 785 |
|
|
BFEXT R4,R5,R6 ; R4=$000a
|
| 786 |
|
|
BMI _FAIL4 ; Negative Flag should be clear
|
| 787 |
|
|
BEQ _FAIL4 ; Zero Flag should be clear
|
| 788 |
|
|
BVS _FAIL4 ; Overflow Flag should be clear
|
| 789 |
|
|
BCS _FAIL4 ; Carry Flag should be clear
|
| 790 |
|
|
LDL R7,#$0a ; R7=$00cc
|
| 791 |
|
|
SUB R0,R7,R4 ; Compare R7 to R4
|
| 792 |
|
|
BNE _FAIL4
|
| 793 |
|
|
|
| 794 |
|
|
LDL R6,#$b8 ; Set offset to 8 and width to 11(12 bits)
|
| 795 |
|
|
BFEXT R4,R5,R6 ; R4=$00c3
|
| 796 |
|
|
LDL R7,#$c3 ; R7=$00c3
|
| 797 |
|
|
SUB R0,R7,R4 ; Compare R7 to R4
|
| 798 |
|
|
BNE _FAIL4
|
| 799 |
|
|
|
| 800 |
|
|
;Test BFINS instruction
|
| 801 |
|
|
LDL R2,#$06
|
| 802 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
|
| 803 |
|
|
LDL R6,#$34 ; Set offset to 4 and width to 3(4 bits)
|
| 804 |
|
|
LDL R5,#$a6 ; Set R5=$00a6
|
| 805 |
|
|
LDH R5,#$c3 ; Set R5=$c3a6
|
| 806 |
|
|
LDL R4,#$ff ; Set R4=$00ff
|
| 807 |
|
|
SEX R4 ; Set R4=$ffff
|
| 808 |
|
|
BFINS R4,R5,R6 ; R4=$ffaf
|
| 809 |
|
|
BPL _FAIL4 ; Negative Flag should be set
|
| 810 |
|
|
BEQ _FAIL4 ; Zero Flag should be clear
|
| 811 |
|
|
BVS _FAIL4 ; Overflow Flag should be clear
|
| 812 |
|
|
BCS _FAIL4 ; Carry Flag should be clear
|
| 813 |
|
|
LDL R7,#$6f ; R7=$006f
|
| 814 |
|
|
LDH R7,#$ff ; R7=$ff6f
|
| 815 |
|
|
SUB R0,R7,R4 ; Compare R7 to R4
|
| 816 |
|
|
BNE _FAIL4
|
| 817 |
|
|
|
| 818 |
|
|
LDL R6,#$b0 ; Set offset to 0 and width to 11(12 bits)
|
| 819 |
|
|
BFINS R4,R5,R6 ; R4=$f3a6
|
| 820 |
|
|
LDL R7,#$a6 ; R7=$00a6
|
| 821 |
|
|
LDH R7,#$f3 ; R7=$f3a6
|
| 822 |
|
|
SUB R0,R7,R4 ; Compare R7 to R4
|
| 823 |
|
|
BNE _FAIL4
|
| 824 |
|
|
|
| 825 |
|
|
;Test BFINSI instruction
|
| 826 |
|
|
LDL R2,#$06
|
| 827 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
|
| 828 |
|
|
LDL R6,#$3c ; Set offset to 12 and width to 3(4 bits)
|
| 829 |
|
|
LDL R5,#$a6 ; Set R5=$00a6
|
| 830 |
|
|
LDH R5,#$c3 ; Set R5=$c3a6
|
| 831 |
|
|
LDL R4,#$ff ; Set R4=$00ff
|
| 832 |
|
|
SEX R4 ; Set R4=$ffff
|
| 833 |
|
|
BFINSI R4,R5,R6 ; R4=$9fff
|
| 834 |
|
|
BPL _FAIL4 ; Negative Flag should be set
|
| 835 |
|
|
BEQ _FAIL4 ; Zero Flag should be clear
|
| 836 |
|
|
BVS _FAIL4 ; Overflow Flag should be clear
|
| 837 |
|
|
BCS _FAIL4 ; Carry Flag should be clear
|
| 838 |
|
|
LDL R7,#$ff ; R7=$00ff
|
| 839 |
|
|
LDH R7,#$9f ; R7=$ff6f
|
| 840 |
|
|
SUB R0,R7,R4 ; Compare R7 to R4
|
| 841 |
|
|
BNE _FAIL4
|
| 842 |
|
|
|
| 843 |
|
|
LDL R6,#$78 ; Set offset to 8 and width to 7(8 bits)
|
| 844 |
|
|
BFINSI R4,R5,R6 ; R4=$59ff
|
| 845 |
|
|
LDL R7,#$ff ; R7=$00ff
|
| 846 |
|
|
LDH R7,#$59 ; R7=$59ff
|
| 847 |
|
|
SUB R0,R7,R4 ; Compare R7 to R4
|
| 848 |
|
|
BNE _FAIL4
|
| 849 |
|
|
|
| 850 |
|
|
;Test BFINSX instruction
|
| 851 |
|
|
LDL R2,#$06
|
| 852 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
|
| 853 |
|
|
LDL R6,#$38 ; Set offset to 8 and width to 3(4 bits)
|
| 854 |
|
|
LDL R5,#$a6 ; Set R5=$00a6
|
| 855 |
|
|
LDH R5,#$c3 ; Set R5=$c3a6
|
| 856 |
|
|
LDL R4,#$ff ; Set R4=$00ff
|
| 857 |
|
|
LDH R4,#$fa ; Set R4=$faff
|
| 858 |
|
|
BFINSX R4,R5,R6 ; R4=$f3ff
|
| 859 |
|
|
BPL _FAIL4 ; Negative Flag should be set
|
| 860 |
|
|
BEQ _FAIL4 ; Zero Flag should be clear
|
| 861 |
|
|
BVS _FAIL4 ; Overflow Flag should be clear
|
| 862 |
|
|
BCS _FAIL4 ; Carry Flag should be clear
|
| 863 |
|
|
LDL R7,#$ff ; R7=$00ff
|
| 864 |
|
|
LDH R7,#$f3 ; R7=$f3ff
|
| 865 |
|
|
SUB R0,R7,R4 ; Compare R7 to R4
|
| 866 |
|
|
BNE _FAIL4
|
| 867 |
|
|
|
| 868 |
|
|
LDL R6,#$70 ; Set offset to 0 and width to 7(8 bits)
|
| 869 |
|
|
BFINSX R4,R5,R6 ; R4=$f3a6
|
| 870 |
|
|
LDL R7,#$a6 ; R7=$00a6
|
| 871 |
|
|
LDH R7,#$f3 ; R7=$f3a6
|
| 872 |
|
|
SUB R0,R7,R4 ; Compare R7 to R4
|
| 873 |
|
|
BNE _FAIL4
|
| 874 |
|
|
|
| 875 |
|
|
|
| 876 |
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
| 877 |
|
|
LDH R2,#$80
|
| 878 |
|
|
LDL R3,#$08
|
| 879 |
|
|
STB R3,(R2,#0)
|
| 880 |
|
|
|
| 881 |
|
|
NOP
|
| 882 |
|
|
SIF
|
| 883 |
|
|
RTS
|
| 884 |
|
|
|
| 885 |
|
|
_FAIL4
|
| 886 |
|
|
LDL R2,#$04 ; Sent Message to Testbench Error Register
|
| 887 |
|
|
LDH R2,#$80
|
| 888 |
|
|
LDL R3,#$08
|
| 889 |
|
|
STB R3,(R2,#0)
|
| 890 |
|
|
|
| 891 |
|
|
SIF
|
| 892 |
|
|
RTS
|
| 893 |
|
|
|
| 894 |
|
|
|
| 895 |
|
|
;-------------------------------------------------------------------------------
|
| 896 |
|
|
; Test Branch instructions
|
| 897 |
|
|
;-------------------------------------------------------------------------------
|
| 898 |
|
|
_START5
|
| 899 |
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
| 900 |
|
|
LDH R2,#$80
|
| 901 |
|
|
LDL R3,#$09 ; Checkpoint Value
|
| 902 |
|
|
STB R3,(R2,#0)
|
| 903 |
|
|
LDL R3,#$05 ; Thread Value
|
| 904 |
|
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
| 905 |
|
|
|
| 906 |
|
|
;Test BCC instruction C = 0
|
| 907 |
|
|
LDL R2,#$00
|
| 908 |
|
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
| 909 |
|
|
BCC _BCC_OK1 ; Take Branch
|
| 910 |
|
|
BRA _BR_ERR
|
| 911 |
|
|
_BCC_OK1
|
| 912 |
|
|
LDL R2,#$01
|
| 913 |
|
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
|
| 914 |
|
|
BCC _BR_ERR ; Don't take branch
|
| 915 |
|
|
|
| 916 |
|
|
|
| 917 |
|
|
;Test BCS instruction C = 1
|
| 918 |
|
|
LDL R2,#$01
|
| 919 |
|
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
|
| 920 |
|
|
BCS _BCS_OK1 ; Take Branch
|
| 921 |
|
|
BRA _BR_ERR
|
| 922 |
|
|
_BCS_OK1
|
| 923 |
|
|
LDL R2,#$00
|
| 924 |
|
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
| 925 |
|
|
BCS _BR_ERR ; Don't take branch
|
| 926 |
|
|
|
| 927 |
|
|
|
| 928 |
|
|
;Test BEQ instruction Z = 1
|
| 929 |
|
|
LDL R2,#$04
|
| 930 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=0
|
| 931 |
|
|
BEQ _BEQ_OK1 ; Take Branch
|
| 932 |
|
|
BRA _BR_ERR
|
| 933 |
|
|
_BEQ_OK1
|
| 934 |
|
|
LDL R2,#$00
|
| 935 |
|
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
| 936 |
|
|
BEQ _BR_ERR ; Don't take branch
|
| 937 |
|
|
|
| 938 |
|
|
|
| 939 |
|
|
;Test BNE instruction Z = 0
|
| 940 |
|
|
LDL R2,#$00
|
| 941 |
|
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
| 942 |
|
|
BNE _BNE_OK1 ; Take Branch
|
| 943 |
|
|
BRA _BR_ERR
|
| 944 |
|
|
_BNE_OK1
|
| 945 |
|
|
LDL R2,#$04
|
| 946 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=0
|
| 947 |
|
|
BNE _BR_ERR ; Don't take branch
|
| 948 |
|
|
|
| 949 |
|
|
|
| 950 |
|
|
;Test BPL instruction N = 0
|
| 951 |
|
|
LDL R2,#$00
|
| 952 |
|
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
| 953 |
|
|
BPL _BPL_OK1 ; Take Branch
|
| 954 |
|
|
BRA _BR_ERR
|
| 955 |
|
|
_BPL_OK1
|
| 956 |
|
|
LDL R2,#$08
|
| 957 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
|
| 958 |
|
|
BPL _BR_ERR ; Don't take branch
|
| 959 |
|
|
|
| 960 |
|
|
|
| 961 |
|
|
;Test BMI instruction N = 1
|
| 962 |
|
|
LDL R2,#$08
|
| 963 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
|
| 964 |
|
|
BMI _BMI_OK1 ; Take Branch
|
| 965 |
|
|
BRA _BR_ERR
|
| 966 |
|
|
_BMI_OK1
|
| 967 |
|
|
LDL R2,#$00
|
| 968 |
|
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
| 969 |
|
|
BMI _BR_ERR ; Don't take branch
|
| 970 |
|
|
|
| 971 |
|
|
|
| 972 |
|
|
;Test BVC instruction V = 0
|
| 973 |
|
|
LDL R2,#$00
|
| 974 |
|
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
| 975 |
|
|
BVC _BVC_OK1 ; Take Branch
|
| 976 |
|
|
BRA _BR_ERR
|
| 977 |
|
|
_BVC_OK1
|
| 978 |
|
|
LDL R2,#$02
|
| 979 |
|
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=1, Carry=0
|
| 980 |
|
|
BVC _BR_ERR ; Don't take branch
|
| 981 |
|
|
|
| 982 |
|
|
|
| 983 |
|
|
;Test BVS instruction V = 1
|
| 984 |
|
|
LDL R2,#$02
|
| 985 |
|
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=1, Carry=0
|
| 986 |
|
|
BVS _BVS_OK1 ; Take Branch
|
| 987 |
|
|
BRA _BR_ERR
|
| 988 |
|
|
_BVS_OK1
|
| 989 |
|
|
LDL R2,#$00
|
| 990 |
|
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
| 991 |
|
|
BVS _BR_ERR ; Don't take branch
|
| 992 |
|
|
|
| 993 |
|
|
|
| 994 |
|
|
;Test BLS instruction C | Z = 1
|
| 995 |
|
|
LDL R2,#$01
|
| 996 |
|
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
|
| 997 |
|
|
BLS _BLS_OK1 ; Take Branch
|
| 998 |
|
|
BRA _BR_ERR
|
| 999 |
|
|
_BLS_OK1
|
| 1000 |
|
|
LDL R2,#$04
|
| 1001 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=0
|
| 1002 |
|
|
BLS _BLS_OK2 ; Take Branch
|
| 1003 |
|
|
BRA _BR_ERR
|
| 1004 |
|
|
_BLS_OK2
|
| 1005 |
|
|
LDL R2,#$00
|
| 1006 |
|
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
| 1007 |
|
|
BLS _BR_ERR ; Don't take branch
|
| 1008 |
|
|
|
| 1009 |
|
|
|
| 1010 |
|
|
;Test BGE instruction N ^ V = 0
|
| 1011 |
|
|
LDL R2,#$0a
|
| 1012 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
| 1013 |
|
|
BGE _BGE_OK1 ; Take Branch
|
| 1014 |
|
|
BRA _BR_ERR
|
| 1015 |
|
|
_BGE_OK1
|
| 1016 |
|
|
LDL R2,#$05
|
| 1017 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=1
|
| 1018 |
|
|
BGE _BGE_OK2 ; Take Branch
|
| 1019 |
|
|
BRA _BR_ERR
|
| 1020 |
|
|
_BGE_OK2
|
| 1021 |
|
|
LDL R2,#$08
|
| 1022 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
|
| 1023 |
|
|
BGE _BR_ERR ; Don't take branch
|
| 1024 |
|
|
|
| 1025 |
|
|
|
| 1026 |
|
|
;Test BHI instruction Z | C = 0
|
| 1027 |
|
|
LDL R2,#$0a
|
| 1028 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
| 1029 |
|
|
BHI _BHI_OK1 ; Take Branch
|
| 1030 |
|
|
BRA _BR_ERR
|
| 1031 |
|
|
_BHI_OK1
|
| 1032 |
|
|
LDL R2,#$0b
|
| 1033 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
| 1034 |
|
|
BHI _BR_ERR ; Don't take branch
|
| 1035 |
|
|
|
| 1036 |
|
|
LDL R2,#$0e
|
| 1037 |
|
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
|
| 1038 |
|
|
BHI _BR_ERR ; Don't take branch
|
| 1039 |
|
|
|
| 1040 |
|
|
|
| 1041 |
|
|
;Test BGT instruction Z | (N ^ V) = 0
|
| 1042 |
|
|
LDL R2,#$0a
|
| 1043 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
| 1044 |
|
|
BGT _BGT_OK1 ; Take Branch
|
| 1045 |
|
|
BRA _BR_ERR
|
| 1046 |
|
|
_BGT_OK1
|
| 1047 |
|
|
LDL R2,#$01
|
| 1048 |
|
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
|
| 1049 |
|
|
BGT _BGT_OK2 ; Take Branch
|
| 1050 |
|
|
BRA _BR_ERR
|
| 1051 |
|
|
_BGT_OK2
|
| 1052 |
|
|
LDL R2,#$0e
|
| 1053 |
|
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
|
| 1054 |
|
|
BGT _BR_ERR ; Don't take branch
|
| 1055 |
|
|
|
| 1056 |
|
|
LDL R2,#$02
|
| 1057 |
|
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=1, Carry=0
|
| 1058 |
|
|
BGT _BR_ERR ; Don't take branch
|
| 1059 |
|
|
|
| 1060 |
|
|
LDL R2,#$08
|
| 1061 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
|
| 1062 |
|
|
BGT _BR_ERR ; Don't take branch
|
| 1063 |
|
|
|
| 1064 |
|
|
|
| 1065 |
|
|
BRA BRA_FWARD
|
| 1066 |
|
|
|
| 1067 |
|
|
|
| 1068 |
|
|
_BR_ERR
|
| 1069 |
|
|
LDL R2,#$04 ; Sent Message to Testbench Error Register
|
| 1070 |
|
|
LDH R2,#$80
|
| 1071 |
|
|
LDL R3,#$0a
|
| 1072 |
|
|
STB R3,(R2,#0)
|
| 1073 |
|
|
|
| 1074 |
|
|
SIF
|
| 1075 |
|
|
RTS
|
| 1076 |
|
|
|
| 1077 |
|
|
_BRA_OK
|
| 1078 |
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
| 1079 |
|
|
LDH R2,#$80
|
| 1080 |
|
|
LDL R3,#$0a
|
| 1081 |
|
|
STB R3,(R2,#0)
|
| 1082 |
|
|
|
| 1083 |
|
|
SIF
|
| 1084 |
|
|
RTS
|
| 1085 |
|
|
|
| 1086 |
|
|
BRA_FWARD
|
| 1087 |
|
|
BRA _BRA_OK ; Test backward branch caculation
|
| 1088 |
|
|
|
| 1089 |
|
|
|
| 1090 |
|
|
;-------------------------------------------------------------------------------
|
| 1091 |
|
|
; Test Subroutine Call and return instructions
|
| 1092 |
|
|
;-------------------------------------------------------------------------------
|
| 1093 |
|
|
_START6
|
| 1094 |
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
| 1095 |
|
|
LDH R2,#$80
|
| 1096 |
|
|
LDL R3,#$0b ; Checkpoint Value
|
| 1097 |
|
|
STB R3,(R2,#0)
|
| 1098 |
|
|
LDL R3,#$06 ; Thread Value
|
| 1099 |
|
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
| 1100 |
|
|
|
| 1101 |
|
|
LDL R4,#$00
|
| 1102 |
|
|
TFR R5,PC ; Subroutine Call
|
| 1103 |
|
|
BRA SUB_TST
|
| 1104 |
|
|
|
| 1105 |
|
|
RET_SUB
|
| 1106 |
|
|
|
| 1107 |
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
| 1108 |
|
|
LDH R2,#$80
|
| 1109 |
|
|
LDL R3,#$0c
|
| 1110 |
|
|
STB R3,(R2,#0)
|
| 1111 |
|
|
|
| 1112 |
|
|
SIF
|
| 1113 |
|
|
RTS
|
| 1114 |
|
|
|
| 1115 |
|
|
_FAIL6
|
| 1116 |
|
|
LDL R2,#$04 ; Sent Message to Testbench Error Register
|
| 1117 |
|
|
LDH R2,#$80
|
| 1118 |
|
|
LDL R3,#$0c
|
| 1119 |
|
|
STB R3,(R2,#0)
|
| 1120 |
|
|
|
| 1121 |
|
|
SIF
|
| 1122 |
|
|
RTS
|
| 1123 |
|
|
|
| 1124 |
|
|
SUB_TST
|
| 1125 |
|
|
LDL R4,#$88 ; If we branch to far then the wrong data will get loaded
|
| 1126 |
|
|
LDH R4,#$99 ; and we'll make a bad compare to cause test to fail
|
| 1127 |
|
|
LDL R7,#$88 ; R7=$0088
|
| 1128 |
|
|
LDH R7,#$99 ; R7=$9988
|
| 1129 |
|
|
SUB R0,R7,R4 ; Compare R7 to R4
|
| 1130 |
|
|
BNE _FAIL6
|
| 1131 |
|
|
JAL R5 ; Jump to return address
|
| 1132 |
|
|
|
| 1133 |
|
|
;-------------------------------------------------------------------------------
|
| 1134 |
|
|
; Test 16 bit Addition and Substract instructions
|
| 1135 |
|
|
;-------------------------------------------------------------------------------
|
| 1136 |
|
|
_START7
|
| 1137 |
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
| 1138 |
|
|
LDH R2,#$80
|
| 1139 |
|
|
LDL R3,#$0d ; Checkpoint Value
|
| 1140 |
|
|
STB R3,(R2,#0)
|
| 1141 |
|
|
LDL R3,#$07 ; Thread Value
|
| 1142 |
|
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
| 1143 |
|
|
|
| 1144 |
|
|
;Test SUB instruction
|
| 1145 |
|
|
LDL R4,#$0f ; R4=$000f
|
| 1146 |
|
|
LDH R4,#$01 ; R4=$010f
|
| 1147 |
|
|
LDL R7,#$0e ; R7=$000e
|
| 1148 |
|
|
LDH R7,#$01 ; R7=$010e
|
| 1149 |
|
|
LDL R2,#$0f
|
| 1150 |
|
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
|
| 1151 |
|
|
SUB R1,R4,R7 ; R4 - R7 => R1
|
| 1152 |
|
|
BMI _FAIL7 ; Negative Flag should be clear
|
| 1153 |
|
|
BEQ _FAIL7 ; Zero Flag should be clear
|
| 1154 |
|
|
BVS _FAIL7 ; Overflow Flag should be clear
|
| 1155 |
|
|
BCS _FAIL7 ; Carry Flag should be clear
|
| 1156 |
|
|
LDL R3,#$01 ; R3=$0001
|
| 1157 |
|
|
SUB R0,R1,R3 ; Compare R1 to R3
|
| 1158 |
|
|
BNE _FAIL7
|
| 1159 |
|
|
|
| 1160 |
|
|
LDL R7,#$0f ; R7=$000f
|
| 1161 |
|
|
LDH R7,#$01 ; R7=$010f
|
| 1162 |
|
|
LDL R2,#$0b
|
| 1163 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
| 1164 |
|
|
SUB R1,R4,R7 ; R4 - R7 => R1
|
| 1165 |
|
|
BMI _FAIL7 ; Negative Flag should be clear
|
| 1166 |
|
|
BNE _FAIL7 ; Zero Flag should be set
|
| 1167 |
|
|
BVS _FAIL7 ; Overflow Flag should be clear
|
| 1168 |
|
|
BCS _FAIL7 ; Carry Flag should be clear
|
| 1169 |
|
|
|
| 1170 |
|
|
|
| 1171 |
|
|
;Test SBC instruction
|
| 1172 |
|
|
LDL R4,#$11 ; R4=$0011
|
| 1173 |
|
|
LDH R4,#$01 ; R4=$0111
|
| 1174 |
|
|
LDL R7,#$0e ; R7=$000e
|
| 1175 |
|
|
LDH R7,#$01 ; R7=$010e
|
| 1176 |
|
|
LDL R2,#$0f
|
| 1177 |
|
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
|
| 1178 |
|
|
SBC R1,R4,R7 ; R4 - R7 => R1
|
| 1179 |
|
|
BMI _FAIL7 ; Negative Flag should be clear
|
| 1180 |
|
|
BEQ _FAIL7 ; Zero Flag should be clear
|
| 1181 |
|
|
BVS _FAIL7 ; Overflow Flag should be clear
|
| 1182 |
|
|
BCS _FAIL7 ; Carry Flag should be clear
|
| 1183 |
|
|
LDL R3,#$02 ; R3=$0002
|
| 1184 |
|
|
SUB R0,R1,R3 ; Compare R1 to R3
|
| 1185 |
|
|
BNE _FAIL7
|
| 1186 |
|
|
|
| 1187 |
|
|
LDL R4,#$0f ; R4=$000f
|
| 1188 |
|
|
LDH R4,#$01 ; R4=$010f
|
| 1189 |
|
|
LDL R7,#$0f ; R7=$000f
|
| 1190 |
|
|
LDH R7,#$01 ; R7=$010f
|
| 1191 |
|
|
LDL R2,#$0a
|
| 1192 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
| 1193 |
|
|
SBC R1,R4,R7 ; R4 - R7 => R1
|
| 1194 |
|
|
BMI _FAIL7 ; Negative Flag should be clear
|
| 1195 |
48 |
rehayes |
BEQ _FAIL7 ; Zero Flag should be clear
|
| 1196 |
16 |
rehayes |
BVS _FAIL7 ; Overflow Flag should be clear
|
| 1197 |
|
|
BCS _FAIL7 ; Carry Flag should be clear
|
| 1198 |
|
|
|
| 1199 |
|
|
|
| 1200 |
|
|
;Test ADD instruction
|
| 1201 |
|
|
LDL R4,#$0f ; R4=$000f
|
| 1202 |
|
|
LDH R4,#$70 ; R4=$700f
|
| 1203 |
|
|
LDL R7,#$01 ; R7=$0001
|
| 1204 |
|
|
LDH R7,#$10 ; R7=$1001
|
| 1205 |
|
|
LDL R2,#$05
|
| 1206 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=1
|
| 1207 |
|
|
ADD R1,R4,R7 ; R4 + R7 => R1
|
| 1208 |
|
|
BPL _FAIL7 ; Negative Flag should be set
|
| 1209 |
|
|
BEQ _FAIL7 ; Zero Flag should be clear
|
| 1210 |
|
|
BVC _FAIL7 ; Overflow Flag should be set
|
| 1211 |
|
|
BCS _FAIL7 ; Carry Flag should be clear
|
| 1212 |
|
|
LDL R3,#$10 ; R3=$0010
|
| 1213 |
|
|
LDH R3,#$80 ; R3=$8010
|
| 1214 |
|
|
SUB R0,R1,R3 ; Compare R1 to R3
|
| 1215 |
|
|
BNE _FAIL7
|
| 1216 |
|
|
|
| 1217 |
|
|
LDL R4,#$00 ; R4=$0000
|
| 1218 |
|
|
LDH R4,#$80 ; R4=$8000
|
| 1219 |
|
|
LDL R7,#$00 ; R7=$0000
|
| 1220 |
|
|
LDH R7,#$80 ; R7=$8000
|
| 1221 |
|
|
LDL R2,#$0f
|
| 1222 |
|
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=0, Carry=0
|
| 1223 |
|
|
ADD R1,R4,R7 ; R4 + R7 => R1
|
| 1224 |
|
|
BMI _FAIL7 ; Negative Flag should be clear
|
| 1225 |
|
|
BNE _FAIL7 ; Zero Flag should be set
|
| 1226 |
|
|
BVC _FAIL7 ; Overflow Flag should be set
|
| 1227 |
|
|
BCC _FAIL7 ; Carry Flag should be set
|
| 1228 |
|
|
SUB R0,R1,R0 ; Compare R1 to R0(Zero)
|
| 1229 |
|
|
BNE _FAIL7
|
| 1230 |
|
|
|
| 1231 |
|
|
|
| 1232 |
|
|
;Test ADC instruction
|
| 1233 |
|
|
LDL R4,#$0f ; R4=$000f
|
| 1234 |
|
|
LDH R4,#$70 ; R4=$700f
|
| 1235 |
|
|
LDL R7,#$01 ; R7=$0001
|
| 1236 |
|
|
LDH R7,#$10 ; R7=$1001
|
| 1237 |
|
|
LDL R2,#$05
|
| 1238 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=1
|
| 1239 |
|
|
ADC R1,R4,R7 ; R4 + R7 => R1
|
| 1240 |
|
|
BPL _FAIL7 ; Negative Flag should be set
|
| 1241 |
|
|
BEQ _FAIL7 ; Zero Flag should be clear
|
| 1242 |
|
|
BVC _FAIL7 ; Overflow Flag should be set
|
| 1243 |
|
|
BCS _FAIL7 ; Carry Flag should be clear
|
| 1244 |
|
|
LDL R3,#$11 ; R3=$0011
|
| 1245 |
|
|
LDH R3,#$80 ; R3=$8011
|
| 1246 |
|
|
SUB R0,R1,R3 ; Compare R1 to R3
|
| 1247 |
|
|
BNE _FAIL7
|
| 1248 |
|
|
|
| 1249 |
|
|
LDL R4,#$00 ; R4=$0000
|
| 1250 |
|
|
LDH R4,#$80 ; R4=$8000
|
| 1251 |
|
|
LDL R7,#$00 ; R7=$0000
|
| 1252 |
|
|
LDH R7,#$80 ; R7=$8000
|
| 1253 |
|
|
LDL R2,#$0c
|
| 1254 |
|
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=0, Carry=0
|
| 1255 |
|
|
ADC R1,R4,R7 ; R4 + R7 => R1
|
| 1256 |
|
|
BMI _FAIL7 ; Negative Flag should be clear
|
| 1257 |
|
|
BNE _FAIL7 ; Zero Flag should be set
|
| 1258 |
|
|
BVC _FAIL7 ; Overflow Flag should be set
|
| 1259 |
|
|
BCC _FAIL7 ; Carry Flag should be set
|
| 1260 |
|
|
SUB R0,R1,R0 ; Compare R1 to R0(Zero)
|
| 1261 |
|
|
BNE _FAIL7
|
| 1262 |
|
|
|
| 1263 |
|
|
|
| 1264 |
|
|
_END_7
|
| 1265 |
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
| 1266 |
|
|
LDH R2,#$80
|
| 1267 |
|
|
LDL R3,#$0e
|
| 1268 |
|
|
STB R3,(R2,#0)
|
| 1269 |
|
|
|
| 1270 |
|
|
SIF
|
| 1271 |
|
|
RTS
|
| 1272 |
|
|
|
| 1273 |
|
|
_FAIL7
|
| 1274 |
|
|
LDL R2,#$04 ; Sent Message to Testbench Error Register
|
| 1275 |
|
|
LDH R2,#$80
|
| 1276 |
|
|
LDL R3,#$0e
|
| 1277 |
|
|
STB R3,(R2,#0)
|
| 1278 |
|
|
|
| 1279 |
|
|
SIF
|
| 1280 |
|
|
RTS
|
| 1281 |
|
|
|
| 1282 |
|
|
;-------------------------------------------------------------------------------
|
| 1283 |
|
|
; Test 8 bit Addition and Substract instructions
|
| 1284 |
|
|
;-------------------------------------------------------------------------------
|
| 1285 |
|
|
_START8
|
| 1286 |
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
| 1287 |
|
|
LDH R2,#$80
|
| 1288 |
|
|
LDL R3,#$0f ; Checkpoint Value
|
| 1289 |
|
|
STB R3,(R2,#0)
|
| 1290 |
|
|
LDL R3,#$08 ; Thread Value
|
| 1291 |
|
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
| 1292 |
|
|
|
| 1293 |
|
|
;Test SUBL instruction
|
| 1294 |
|
|
LDL R5,#$0f ; R5=$000f
|
| 1295 |
|
|
LDL R2,#$0f
|
| 1296 |
|
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
|
| 1297 |
|
|
SUBL R5,#$0e ; R5 - $0e => R5
|
| 1298 |
|
|
BMI _FAIL8 ; Negative Flag should be clear
|
| 1299 |
|
|
BEQ _FAIL8 ; Zero Flag should be clear
|
| 1300 |
|
|
BVS _FAIL8 ; Overflow Flag should be clear
|
| 1301 |
|
|
BCS _FAIL8 ; Carry Flag should be clear
|
| 1302 |
|
|
LDL R3,#$01 ; R3=$0001
|
| 1303 |
|
|
SUB R0,R5,R3 ; Compare R5 to R3
|
| 1304 |
|
|
BNE _FAIL8
|
| 1305 |
|
|
|
| 1306 |
|
|
LDL R7,#$0f ; R7=$000f
|
| 1307 |
|
|
LDL R2,#$0d
|
| 1308 |
|
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
|
| 1309 |
|
|
SUBL R7,#$10 ; R7 - $10 => R7
|
| 1310 |
|
|
BPL _FAIL8 ; Negative Flag should be set
|
| 1311 |
|
|
BEQ _FAIL8 ; Zero Flag should be clear
|
| 1312 |
|
|
BVS _FAIL8 ; Overflow Flag should be clear
|
| 1313 |
|
|
BCC _FAIL8 ; Carry Flag should be set
|
| 1314 |
48 |
rehayes |
CMPL R7,#$FF ; Result should be -1 or $FFFF
|
| 1315 |
|
|
CPCH R7,#$FF
|
| 1316 |
|
|
BNE _FAIL8
|
| 1317 |
16 |
rehayes |
|
| 1318 |
|
|
;Test SUBH instruction
|
| 1319 |
|
|
LDL R6,#$11 ; R4=$0011
|
| 1320 |
|
|
LDH R6,#$81 ; R4=$8111
|
| 1321 |
|
|
LDL R2,#$0d
|
| 1322 |
|
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=0, Carry=1
|
| 1323 |
|
|
SUBH R6,#$70 ; R6 - $70 => R6
|
| 1324 |
|
|
BMI _FAIL8 ; Negative Flag should be clear
|
| 1325 |
|
|
BEQ _FAIL8 ; Zero Flag should be clear
|
| 1326 |
|
|
BVC _FAIL8 ; Overflow Flag should be set
|
| 1327 |
|
|
BCS _FAIL8 ; Carry Flag should be clear
|
| 1328 |
|
|
LDL R3,#$11 ; R3=$0011
|
| 1329 |
|
|
LDH R3,#$11 ; R3=$1111
|
| 1330 |
|
|
SUB R0,R6,R3 ; Compare R6 to R3
|
| 1331 |
|
|
BNE _FAIL8
|
| 1332 |
|
|
|
| 1333 |
|
|
LDL R6,#$00 ; R6=$0000
|
| 1334 |
|
|
LDH R6,#$01 ; R6=$0100
|
| 1335 |
|
|
LDL R2,#$06
|
| 1336 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
|
| 1337 |
|
|
SUBH R6,#$02 ; R6 - $70 => R6
|
| 1338 |
|
|
BPL _FAIL8 ; Negative Flag should be set
|
| 1339 |
|
|
BEQ _FAIL8 ; Zero Flag should be clear
|
| 1340 |
|
|
BVS _FAIL8 ; Overflow Flag should be clear
|
| 1341 |
|
|
BCC _FAIL8 ; Carry Flag should be set
|
| 1342 |
|
|
|
| 1343 |
|
|
|
| 1344 |
|
|
;Test CMPL instruction
|
| 1345 |
|
|
LDL R5,#$0f ; R5=$000f
|
| 1346 |
|
|
LDL R2,#$0b
|
| 1347 |
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
| 1348 |
|
|
CMPL R5,#$0f ; R5 - $0f => R5
|
| 1349 |
|
|
BMI _FAIL8 ; Negative Flag should be clear
|
| 1350 |
|
|
BNE _FAIL8 ; Zero Flag should be set
|
| 1351 |
|
|
BVS _FAIL8 ; Overflow Flag should be clear
|
| 1352 |
|
|
BCS _FAIL8 ; Carry Flag should be clear
|
| 1353 |
|
|
|
| 1354 |
|
|
LDL R7,#$0f ; R7=$000f
|
| 1355 |
|
|
LDL R2,#$07
|
| 1356 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
|
| 1357 |
|
|
CMPL R7,#$10 ; R7 - $10 => R7
|
| 1358 |
|
|
BPL _FAIL8 ; Negative Flag should be set
|
| 1359 |
|
|
BEQ _FAIL8 ; Zero Flag should be clear
|
| 1360 |
|
|
BVS _FAIL8 ; Overflow Flag should be clear
|
| 1361 |
|
|
BCC _FAIL8 ; Carry Flag should be set
|
| 1362 |
|
|
|
| 1363 |
|
|
|
| 1364 |
|
|
;Test CPCH instruction
|
| 1365 |
|
|
LDL R5,#$00 ; R5=$0000
|
| 1366 |
|
|
LDH R5,#$01 ; R5=$0001
|
| 1367 |
|
|
LDL R2,#$0f
|
| 1368 |
|
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
|
| 1369 |
|
|
CPCH R5,#$00 ; R5 - $00 - carryflag => nowhere
|
| 1370 |
|
|
BMI _FAIL8 ; Negative Flag should be clear
|
| 1371 |
|
|
BNE _FAIL8 ; Zero Flag should be set
|
| 1372 |
|
|
BVS _FAIL8 ; Overflow Flag should be clear
|
| 1373 |
|
|
BCS _FAIL8 ; Carry Flag should be clear
|
| 1374 |
|
|
LDL R2,#$06
|
| 1375 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
|
| 1376 |
|
|
CPCH R5,#$02 ; R5 - $00 - carryflag => nowhere
|
| 1377 |
|
|
BPL _FAIL8 ; Negative Flag should be set
|
| 1378 |
|
|
BEQ _FAIL8 ; Zero Flag should be clear
|
| 1379 |
|
|
BVS _FAIL8 ; Overflow Flag should be clear
|
| 1380 |
|
|
BCC _FAIL8 ; Carry Flag should be set
|
| 1381 |
|
|
|
| 1382 |
|
|
|
| 1383 |
|
|
;Test ADDH instruction
|
| 1384 |
|
|
LDL R5,#$0f ; R5=$000f
|
| 1385 |
|
|
LDH R5,#$70 ; R5=$700f
|
| 1386 |
|
|
LDL R2,#$0e
|
| 1387 |
|
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
|
| 1388 |
|
|
ADDH R5,#$a0 ; R5 + $a0 => R5
|
| 1389 |
|
|
BMI _FAIL8 ; Negative Flag should be clear
|
| 1390 |
|
|
BEQ _FAIL8 ; Zero Flag should be clear
|
| 1391 |
|
|
BVS _FAIL8 ; Overflow Flag should be clear
|
| 1392 |
|
|
BCC _FAIL8 ; Carry Flag should be set
|
| 1393 |
|
|
LDL R3,#$0f ; R3=$000f
|
| 1394 |
|
|
LDH R3,#$10 ; R3=$100f
|
| 1395 |
|
|
SUB R0,R5,R3 ; Compare R5 to R3
|
| 1396 |
|
|
BNE _FAIL8
|
| 1397 |
|
|
|
| 1398 |
|
|
LDL R2,#$07
|
| 1399 |
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=1
|
| 1400 |
|
|
ADDH R5,#$70 ; R5 + $70 => R5
|
| 1401 |
|
|
BPL _FAIL8 ; Negative Flag should be set
|
| 1402 |
|
|
BEQ _FAIL8 ; Zero Flag should be clear
|
| 1403 |
|
|
BVC _FAIL8 ; Overflow Flag should be set
|
| 1404 |
|
|
BCS _FAIL8 ; Carry Flag should be clear
|
| 1405 |
|
|
LDL R3,#$0f ; R3=$000f
|
| 1406 |
|
|
LDH R3,#$80 ; R3=$800f
|
| 1407 |
|
|
SUB R0,R5,R3 ; Compare R5 to R3
|
| 1408 |
|
|
BNE _FAIL8
|
| 1409 |
|
|
|
| 1410 |
|
|
|
| 1411 |
|
|
;Test ADDL instruction
|
| 1412 |
|
|
LDL R4,#$ff ; R4=$00ff
|
| 1413 |
|
|
LDH R4,#$70 ; R4=$70ff
|
| 1414 |
|
|
LDL R2,#$0e
|
| 1415 |
|
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
|
| 1416 |
|
|
ADDL R4,#$01 ; R4 + $01 => R4
|
| 1417 |
|
|
BMI _FAIL8 ; Negative Flag should be clear
|
| 1418 |
|
|
BEQ _FAIL8 ; Zero Flag should be clear
|
| 1419 |
|
|
BVS _FAIL8 ; Overflow Flag should be clear
|
| 1420 |
|
|
BCC _FAIL8 ; Carry Flag should be set
|
| 1421 |
|
|
LDL R5,#$00 ; R5=$0000
|
| 1422 |
|
|
LDH R5,#$71 ; R5=$7100
|
| 1423 |
|
|
SUB R0,R4,R5 ; Compare R4 to R5
|
| 1424 |
|
|
BNE _FAIL8
|
| 1425 |
|
|
|
| 1426 |
|
|
LDL R4,#$8e ; R4=$008e
|
| 1427 |
|
|
LDH R4,#$7f ; R4=$7f8e
|
| 1428 |
|
|
LDL R2,#$0c
|
| 1429 |
|
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=0, Carry=0
|
| 1430 |
|
|
ADDL R4,#$81 ; R4 + $81 => R4
|
| 1431 |
|
|
BPL _FAIL8 ; Negative Flag should be set
|
| 1432 |
|
|
BEQ _FAIL8 ; Zero Flag should be clear
|
| 1433 |
|
|
BVC _FAIL8 ; Overflow Flag should be set
|
| 1434 |
|
|
BCC _FAIL8 ; Carry Flag should be set
|
| 1435 |
|
|
LDL R6,#$0f ; R6=$000f
|
| 1436 |
|
|
LDH R6,#$80 ; R6=$800f
|
| 1437 |
|
|
SUB R0,R4,R6 ; Compare R4 to R6
|
| 1438 |
|
|
BNE _FAIL8
|
| 1439 |
|
|
|
| 1440 |
|
|
|
| 1441 |
|
|
_END_8
|
| 1442 |
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
| 1443 |
|
|
LDH R2,#$80
|
| 1444 |
|
|
LDL R3,#$10
|
| 1445 |
|
|
STB R3,(R2,#0)
|
| 1446 |
|
|
|
| 1447 |
|
|
SIF
|
| 1448 |
|
|
RTS
|
| 1449 |
|
|
|
| 1450 |
|
|
_FAIL8
|
| 1451 |
48 |
rehayes |
LDL R2,#$00 ; Sent Message to Testbench Error Register
|
| 1452 |
16 |
rehayes |
LDH R2,#$80
|
| 1453 |
|
|
LDL R3,#$10
|
| 1454 |
48 |
rehayes |
STB R3,(R2,#4)
|
| 1455 |
16 |
rehayes |
|
| 1456 |
|
|
SIF
|
| 1457 |
|
|
RTS
|
| 1458 |
|
|
|
| 1459 |
|
|
|
| 1460 |
|
|
;-------------------------------------------------------------------------------
|
| 1461 |
|
|
; Test Load and Store instructions
|
| 1462 |
|
|
;-------------------------------------------------------------------------------
|
| 1463 |
|
|
_START9
|
| 1464 |
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
| 1465 |
|
|
LDH R2,#$80
|
| 1466 |
|
|
LDL R3,#$11 ; Checkpoint Value
|
| 1467 |
|
|
STB R3,(R2,#0)
|
| 1468 |
|
|
LDL R3,#$09 ; Thread Value
|
| 1469 |
|
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
| 1470 |
|
|
|
| 1471 |
|
|
LDL R1,#$aa ; R1=$00aa
|
| 1472 |
|
|
LDH R1,#$7f ; R1=$7faa
|
| 1473 |
|
|
LDL R2,#$55 ; R2=$0055
|
| 1474 |
|
|
LDH R2,#$6f ; R2=$6f55
|
| 1475 |
|
|
LDL R3,#$66 ; R3=$0066
|
| 1476 |
|
|
LDH R3,#$5f ; R3=$5f66
|
| 1477 |
|
|
LDL R7,#$ff ; R7=$00ff
|
| 1478 |
|
|
LDH R7,#$ff ; R7=$ffff
|
| 1479 |
|
|
|
| 1480 |
|
|
;Test STB/LDB instruction
|
| 1481 |
|
|
STB R1,(R0,#$00) ;
|
| 1482 |
|
|
STB R2,(R0,#$01) ;
|
| 1483 |
|
|
STB R3,(R0,#$1f) ;
|
| 1484 |
|
|
LDL R4,#$00 ; R4=$0000
|
| 1485 |
|
|
LDB R5,(R4,#$00) ;
|
| 1486 |
|
|
LDB R6,(R4,#$01) ;
|
| 1487 |
|
|
LDB R7,(R4,#$1f) ;
|
| 1488 |
|
|
CMPL R5,#$aa ;
|
| 1489 |
|
|
BNE _FAIL9
|
| 1490 |
|
|
CMPL R6,#$55 ;
|
| 1491 |
|
|
BNE _FAIL9
|
| 1492 |
|
|
CMPL R7,#$66 ;
|
| 1493 |
|
|
BNE _FAIL9
|
| 1494 |
|
|
LDL R6,#$66 ; R6=$0066
|
| 1495 |
|
|
CMP R6,R7 ; Make sure the high byte has been cleared
|
| 1496 |
|
|
BNE _FAIL9
|
| 1497 |
|
|
|
| 1498 |
|
|
;Test STW/LDW instruction
|
| 1499 |
|
|
STW R1,(R0,#$04) ; Should be even offsets
|
| 1500 |
|
|
STW R2,(R0,#$06) ;
|
| 1501 |
|
|
STW R3,(R0,#$0a) ;
|
| 1502 |
|
|
LDL R4,#$00 ; R4=$0000
|
| 1503 |
|
|
LDL R5,#$00 ; R5=$0000
|
| 1504 |
|
|
LDL R6,#$00 ; R6=$0000
|
| 1505 |
|
|
LDL R7,#$00 ; R7=$0000
|
| 1506 |
|
|
LDW R5,(R4,#$04) ;
|
| 1507 |
|
|
LDW R6,(R4,#$06) ;
|
| 1508 |
|
|
LDW R7,(R4,#$0a) ;
|
| 1509 |
|
|
CMP R1,R5 ;
|
| 1510 |
|
|
BNE _FAIL9
|
| 1511 |
|
|
CMP R2,R6 ;
|
| 1512 |
|
|
BNE _FAIL9
|
| 1513 |
|
|
CMP R3,R7 ;
|
| 1514 |
|
|
BNE _FAIL9
|
| 1515 |
|
|
|
| 1516 |
|
|
;Test STB/LDB instruction
|
| 1517 |
|
|
LDL R1,#$cc ; R1=$00cc
|
| 1518 |
|
|
LDH R1,#$1f ; R1=$1f66
|
| 1519 |
|
|
LDL R2,#$99 ; R2=$0099
|
| 1520 |
|
|
LDH R2,#$2f ; R2=$2f99
|
| 1521 |
|
|
|
| 1522 |
|
|
LDL R4,#$20 ; R4=$0020 - Base Address
|
| 1523 |
|
|
LDL R5,#$02 ; R5=$0002 - even offset
|
| 1524 |
|
|
LDL R6,#$07 ; R6=$0007 - odd offset
|
| 1525 |
|
|
STB R1,(R4,R5) ;
|
| 1526 |
|
|
STB R2,(R4,R6) ;
|
| 1527 |
|
|
LDB R5,(R4,R5) ;
|
| 1528 |
|
|
LDB R6,(R4,R6) ;
|
| 1529 |
|
|
CMPL R5,#$cc ;
|
| 1530 |
|
|
BNE _FAIL9
|
| 1531 |
|
|
LDL R3,#$99 ; R3=$0099
|
| 1532 |
|
|
CMP R3,R6 ; Make sure the high byte has been cleared
|
| 1533 |
|
|
BNE _FAIL9
|
| 1534 |
|
|
|
| 1535 |
|
|
;Test STW/LDW instruction
|
| 1536 |
|
|
LDL R1,#$cc ; R1=$00cc
|
| 1537 |
|
|
LDH R1,#$1f ; R1=$1f66
|
| 1538 |
|
|
LDL R2,#$99 ; R2=$0099
|
| 1539 |
|
|
LDH R2,#$2f ; R2=$2f99
|
| 1540 |
|
|
|
| 1541 |
|
|
LDL R4,#$30 ; R3=$0030 - Base Address
|
| 1542 |
|
|
LDL R5,#$02 ; R5=$0002
|
| 1543 |
|
|
LDL R6,#$08 ; R6=$0008
|
| 1544 |
|
|
STW R1,(R4,R5) ;
|
| 1545 |
|
|
STW R2,(R4,R6) ;
|
| 1546 |
|
|
LDW R5,(R4,R5) ;
|
| 1547 |
|
|
LDW R6,(R4,R6) ;
|
| 1548 |
|
|
CMP R5,R1 ;
|
| 1549 |
|
|
BNE _FAIL9
|
| 1550 |
|
|
CMP R6,R2 ;
|
| 1551 |
|
|
BNE _FAIL9
|
| 1552 |
|
|
|
| 1553 |
|
|
;Test STB/LDB instruction
|
| 1554 |
|
|
LDL R1,#$33 ; R1=$0033
|
| 1555 |
|
|
LDH R1,#$1f ; R1=$1f33
|
| 1556 |
|
|
LDL R2,#$55 ; R2=$0055
|
| 1557 |
|
|
LDH R2,#$2f ; R2=$2f55
|
| 1558 |
|
|
|
| 1559 |
|
|
LDL R4,#$40 ; R4=$0040 - Base Address
|
| 1560 |
|
|
LDL R5,#$02 ; R5=$0002 - even offset
|
| 1561 |
|
|
LDL R6,#$07 ; R6=$0007 - odd offset
|
| 1562 |
|
|
STB R1,(R4,R5+) ;
|
| 1563 |
|
|
STB R2,(R4,R6+) ;
|
| 1564 |
|
|
CMPL R5,#$03 ; Test for 1 byte increment
|
| 1565 |
|
|
BNE _FAIL9
|
| 1566 |
|
|
CMPL R6,#$08 ; Test for 1 byte increment
|
| 1567 |
|
|
BNE _FAIL9
|
| 1568 |
|
|
LDB R3,(R4,-R5) ;
|
| 1569 |
|
|
LDB R7,(R4,-R6) ;
|
| 1570 |
|
|
CMPL R5,#$02 ; Test for 1 byte decrement
|
| 1571 |
|
|
BNE _FAIL9
|
| 1572 |
|
|
CMPL R6,#$07 ; Test for 1 byte decrement
|
| 1573 |
|
|
BNE _FAIL9
|
| 1574 |
|
|
CMPL R3,#$33 ;
|
| 1575 |
|
|
BNE _FAIL9
|
| 1576 |
|
|
LDL R3,#$55 ; R3=$0055
|
| 1577 |
|
|
CMP R3,R7 ; Make sure the high byte has been cleared
|
| 1578 |
|
|
BNE _FAIL9
|
| 1579 |
|
|
|
| 1580 |
|
|
;Test STB/LDB instruction
|
| 1581 |
|
|
LDL R1,#$66 ; R1=$0066
|
| 1582 |
|
|
LDH R1,#$1f ; R1=$1f66
|
| 1583 |
|
|
LDL R2,#$99 ; R2=$0099
|
| 1584 |
|
|
LDH R2,#$2f ; R2=$2f99
|
| 1585 |
|
|
|
| 1586 |
|
|
LDL R4,#$50 ; R4=$0050 - Base Address
|
| 1587 |
|
|
LDL R5,#$04 ; R5=$0004 - even offset
|
| 1588 |
|
|
LDL R6,#$09 ; R6=$0009 - odd offset
|
| 1589 |
|
|
STB R1,(R4,-R5) ;
|
| 1590 |
|
|
STB R2,(R4,-R6) ;
|
| 1591 |
|
|
CMPL R5,#$03 ; Test for 1 byte decrement
|
| 1592 |
|
|
BNE _FAIL9
|
| 1593 |
|
|
CMPL R6,#$08 ; Test for 1 byte decrement
|
| 1594 |
|
|
BNE _FAIL9
|
| 1595 |
|
|
LDB R3,(R4,R5+) ;
|
| 1596 |
|
|
LDB R7,(R4,R6+) ;
|
| 1597 |
|
|
CMPL R5,#$04 ; Test for 1 byte increment
|
| 1598 |
|
|
BNE _FAIL9
|
| 1599 |
|
|
CMPL R6,#$09 ; Test for 1 byte increment
|
| 1600 |
|
|
BNE _FAIL9
|
| 1601 |
|
|
CMPL R3,#$66 ;
|
| 1602 |
|
|
BNE _FAIL9
|
| 1603 |
|
|
LDL R3,#$99 ; R3=$0099
|
| 1604 |
|
|
CMP R3,R7 ; Make sure the high byte has been cleared
|
| 1605 |
|
|
BNE _FAIL9
|
| 1606 |
|
|
|
| 1607 |
|
|
;Test STW/LDW instruction
|
| 1608 |
|
|
LDL R1,#$aa ; R1=$00aa
|
| 1609 |
|
|
LDH R1,#$1f ; R1=$1faa
|
| 1610 |
|
|
LDL R2,#$cc ; R2=$00cc
|
| 1611 |
|
|
LDH R2,#$2f ; R2=$2fcc
|
| 1612 |
|
|
|
| 1613 |
|
|
LDL R4,#$60 ; R4=$0060 - Base Address
|
| 1614 |
|
|
LDL R5,#$02 ; R5=$0002 - even offset
|
| 1615 |
|
|
LDL R6,#$08 ; R6=$0008
|
| 1616 |
|
|
STW R1,(R4,R5+) ;
|
| 1617 |
|
|
STW R2,(R4,R6+) ;
|
| 1618 |
|
|
CMPL R5,#$04 ; Test for 2 byte increment
|
| 1619 |
|
|
BNE _FAIL9
|
| 1620 |
|
|
CMPL R6,#$0a ; Test for 2 byte increment
|
| 1621 |
|
|
BNE _FAIL9
|
| 1622 |
|
|
LDW R3,(R4,-R5) ;
|
| 1623 |
|
|
LDW R7,(R4,-R6) ;
|
| 1624 |
|
|
CMPL R5,#$02 ; Test for 2 byte decrement
|
| 1625 |
|
|
BNE _FAIL9
|
| 1626 |
|
|
CMPL R6,#$08 ; Test for 2 byte decrement
|
| 1627 |
|
|
BNE _FAIL9
|
| 1628 |
|
|
CMP R1,R3 ;
|
| 1629 |
|
|
BNE _FAIL9
|
| 1630 |
|
|
CMP R2,R7 ;
|
| 1631 |
|
|
BNE _FAIL9
|
| 1632 |
|
|
|
| 1633 |
|
|
_END_9
|
| 1634 |
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
| 1635 |
|
|
LDH R2,#$80
|
| 1636 |
|
|
LDL R3,#$12
|
| 1637 |
|
|
STB R3,(R2,#0)
|
| 1638 |
|
|
|
| 1639 |
|
|
SIF
|
| 1640 |
|
|
RTS
|
| 1641 |
|
|
|
| 1642 |
|
|
_FAIL9
|
| 1643 |
|
|
LDL R2,#$04 ; Sent Message to Testbench Error Register
|
| 1644 |
|
|
LDH R2,#$80
|
| 1645 |
|
|
LDL R3,#$12
|
| 1646 |
|
|
STB R3,(R2,#0)
|
| 1647 |
|
|
|
| 1648 |
|
|
SIF
|
| 1649 |
|
|
RTS
|
| 1650 |
|
|
|
| 1651 |
|
|
|
| 1652 |
|
|
;-------------------------------------------------------------------------------
|
| 1653 |
|
|
; Test Semaphore instructions
|
| 1654 |
|
|
;-------------------------------------------------------------------------------
|
| 1655 |
|
|
_START10
|
| 1656 |
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
| 1657 |
|
|
LDH R2,#$80
|
| 1658 |
|
|
LDL R3,#$13 ; Checkpoint Value
|
| 1659 |
|
|
STB R3,(R2,#0)
|
| 1660 |
|
|
LDL R3,#$0a ; Thread Value
|
| 1661 |
|
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
| 1662 |
|
|
|
| 1663 |
|
|
LDL R1,#$5 ; R1=$0005
|
| 1664 |
|
|
|
| 1665 |
|
|
;Test SSEM instruction
|
| 1666 |
|
|
SSEM #7 ; semaphores
|
| 1667 |
|
|
BCC _FAIL10 ; Should be set
|
| 1668 |
|
|
SSEM R1 ; semaphores
|
| 1669 |
|
|
BCC _FAIL10 ; Should be set
|
| 1670 |
|
|
|
| 1671 |
|
|
SSEM #6 ; semaphore has been set by host
|
| 1672 |
|
|
BCS _FAIL10 ; Should be clear
|
| 1673 |
|
|
|
| 1674 |
|
|
CSEM #7 ; semaphore
|
| 1675 |
|
|
CSEM R1 ; semaphore #5
|
| 1676 |
|
|
; Host will test that these semaphores are clear
|
| 1677 |
|
|
|
| 1678 |
|
|
SSEM #3 ; set this semaphore for the host to test
|
| 1679 |
|
|
|
| 1680 |
|
|
|
| 1681 |
|
|
_END_10
|
| 1682 |
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
| 1683 |
|
|
LDH R2,#$80
|
| 1684 |
|
|
LDL R3,#$14
|
| 1685 |
|
|
STB R3,(R2,#0)
|
| 1686 |
|
|
|
| 1687 |
|
|
SIF
|
| 1688 |
|
|
RTS
|
| 1689 |
|
|
|
| 1690 |
|
|
_FAIL10
|
| 1691 |
|
|
LDL R2,#$04 ; Sent Message to Testbench Error Register
|
| 1692 |
|
|
LDH R2,#$80
|
| 1693 |
|
|
LDL R3,#$14
|
| 1694 |
|
|
STB R3,(R2,#0)
|
| 1695 |
|
|
|
| 1696 |
|
|
SIF
|
| 1697 |
|
|
RTS
|
| 1698 |
|
|
|
| 1699 |
|
|
|
| 1700 |
|
|
;-------------------------------------------------------------------------------
|
| 1701 |
|
|
;-------------------------------------------------------------------------------
|
| 1702 |
|
|
|
| 1703 |
|
|
TFR R2,CCR ; R2 = CCR
|
| 1704 |
|
|
|
| 1705 |
|
|
;empty line
|
| 1706 |
|
|
|
| 1707 |
|
|
BACK_
|
| 1708 |
|
|
|
| 1709 |
|
|
|
| 1710 |
|
|
SIF R7
|
| 1711 |
|
|
BRK
|
| 1712 |
|
|
|
| 1713 |
|
|
ORG $8000 ; Special Testbench Addresses
|
| 1714 |
|
|
_BENCH DS.W 8
|
| 1715 |
|
|
|
| 1716 |
|
|
|
| 1717 |
|
|
|
| 1718 |
|
|
|
