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[/] [xgate/] [trunk/] [sw/] [xgate_test_code/] [irq_test/] [irq_test.s] - Blame information for rev 89

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Line No. Rev Author Line
1 69 rehayes
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2
; Interrupt test for xgate RISC processor core
3
; Bob Hayes - May 11 2010
4
 
5
 
6 89 rehayes
        CPU     XGATE
7 69 rehayes
 
8 89 rehayes
        ORG     $fe00
9
        DS.W    2       ; reserve two words at channel 0
10
        ; channel 1
11
        DC.W    _IRQ1   ; point to start address
12
        DC.W    V_PTR   ; point to initial variables
13
        ; channel 2
14
        DC.W    _IRQ2   ; point to start address
15
        DC.W    V_PTR   ; point to initial variables
16
        ; channel 3
17
        DC.W    _IRQ3   ; point to start address
18
        DC.W    V_PTR   ; point to initial variables
19
        ; channel 4
20
        DC.W    _IRQ4   ; point to start address
21
        DC.W    V_PTR   ; point to initial variables
22
        ; channel 5
23
        DC.W    _IRQ5   ; point to start address
24
        DC.W    V_PTR   ; point to initial variables
25
        ; channel 6
26
        DC.W    _IRQ6   ; point to start address
27
        DC.W    V_PTR   ; point to initial variables
28
        ; channel 7
29
        DC.W    _IRQ7   ; point to start address
30
        DC.W    V_PTR   ; point to initial variables
31
        ; channel 8
32
        DC.W    _IRQ8   ; point to start address
33
        DC.W    V_PTR   ; point to initial variables
34
        ; channel 9
35
        DC.W    _IRQ9   ; point to start address
36
        DC.W    V_PTR   ; point to initial variables
37
        ; channel 10
38
        DC.W    _IRQ10  ; point to start address
39
        DC.W    V_PTR   ; point to initial variables
40
        ; channel 11
41
        DC.W    _ERROR  ; point to start address
42
        DC.W    V_PTR   ; point to initial variables
43
        ; channel 12
44
        DC.W    _ERROR  ; point to start address
45
        DC.W    V_PTR   ; point to initial variables
46
        ; channel 13
47
        DC.W    _ERROR  ; point to start address
48
        DC.W    V_PTR   ; point to initial variables
49
        ; channel 14
50
        DC.W    _ERROR  ; point to start address
51
        DC.W    V_PTR   ; point to initial variables
52
        ; channel 15
53
        DC.W    _ERROR  ; point to start address
54
        DC.W    V_PTR   ; point to initial variables
55
        ; channel 16
56
        DC.W    _ERROR  ; point to start address
57
        DC.W    V_PTR   ; point to initial variables
58
        ; channel 17
59
        DC.W    _ERROR  ; point to start address
60
        DC.W    V_PTR   ; point to initial variables
61
        ; channel 18
62
        DC.W    _ERROR  ; point to start address
63
        DC.W    V_PTR   ; point to initial variables
64
        ; channel 19
65
        DC.W    _ERROR  ; point to start address
66
        DC.W    V_PTR   ; point to initial variables
67
        ; channel 20
68
        DC.W    _ERROR  ; point to start address
69
        DC.W    V_PTR   ; point to initial variables
70
        ; channel 21
71
        DC.W    _ERROR  ; point to start address
72
        DC.W    V_PTR   ; point to initial variables
73
        ; channel 22
74
        DC.W    _ERROR  ; point to start address
75
        DC.W    V_PTR   ; point to initial variables
76
        ; channel 23
77
        DC.W    _ERROR  ; point to start address
78
        DC.W    V_PTR   ; point to initial variables
79
        ; channel 24
80
        DC.W    _ERROR  ; point to start address
81
        DC.W    V_PTR   ; point to initial variables
82
        ; channel 25
83
        DC.W    _ERROR  ; point to start address
84
        DC.W    V_PTR   ; point to initial variables
85
        ; channel 26
86
        DC.W    _ERROR  ; point to start address
87
        DC.W    V_PTR   ; point to initial variables
88
        ; channel 27
89
        DC.W    _ERROR  ; point to start address
90
        DC.W    V_PTR   ; point to initial variables
91
        ; channel 28
92
        DC.W    _ERROR  ; point to start address
93
        DC.W    V_PTR   ; point to initial variables
94
        ; channel 29
95
        DC.W    _ERROR  ; point to start address
96
        DC.W    V_PTR   ; point to initial variables
97
        ; channel 30
98
        DC.W    _ERROR  ; point to start address
99
        DC.W    V_PTR   ; point to initial variables
100
        ; channel 31
101
        DC.W    _ERROR  ; point to start address
102
        DC.W    V_PTR   ; point to initial variables
103
        ; channel 32
104
        DC.W    _ERROR  ; point to start address
105
        DC.W    V_PTR   ; point to initial variables
106
        ; channel 33
107
        DC.W    _ERROR  ; point to start address
108
        DC.W    V_PTR   ; point to initial variables
109
        ; channel 34
110
        DC.W    _ERROR  ; point to start address
111
        DC.W    V_PTR   ; point to initial variables
112
        ; channel 35
113
        DC.W    _ERROR  ; point to start address
114
        DC.W    V_PTR   ; point to initial variables
115
        ; channel 36
116
        DC.W    _ERROR  ; point to start address
117
        DC.W    V_PTR   ; point to initial variables
118
        ; channel 37
119
        DC.W    _ERROR  ; point to start address
120
        DC.W    V_PTR   ; point to initial variables
121
        ; channel 38
122
        DC.W    _ERROR  ; point to start address
123
        DC.W    V_PTR   ; point to initial variables
124
        ; channel 39
125
        DC.W    _ERROR  ; point to start address
126
        DC.W    V_PTR   ; point to initial variables
127
        ; channel 40
128
        DC.W    _ERROR  ; point to start address
129
        DC.W    V_PTR   ; point to initial variables
130
        ; channel 41
131
        DC.W    _ERROR  ; point to start address
132
        DC.W    V_PTR   ; point to initial variables
133
        ; channel 42
134
        DC.W    _ERROR  ; point to start address
135
        DC.W    V_PTR   ; point to initial variables
136
        ; channel 43
137
        DC.W    _ERROR  ; point to start address
138
        DC.W    V_PTR   ; point to initial variables
139
        ; channel 44
140
        DC.W    _ERROR  ; point to start address
141
        DC.W    V_PTR   ; point to initial variables
142
        ; channel 45
143
        DC.W    _ERROR  ; point to start address
144
        DC.W    V_PTR   ; point to initial variables
145
        ; channel 46
146
        DC.W    _ERROR  ; point to start address
147
        DC.W    V_PTR   ; point to initial variables
148
        ; channel 47
149
        DC.W    _ERROR  ; point to start address
150
        DC.W    V_PTR   ; point to initial variables
151
        ; channel 48
152
        DC.W    _ERROR  ; point to start address
153
        DC.W    V_PTR   ; point to initial variables
154
        ; channel 49
155
        DC.W    _ERROR  ; point to start address
156
        DC.W    V_PTR   ; point to initial variables
157
        ; channel 50
158
        DC.W    _ERROR  ; point to start address
159
        DC.W    V_PTR   ; point to initial variables
160 69 rehayes
 
161 89 rehayes
        ORG     $2000 ; with comment
162 69 rehayes
 
163 89 rehayes
V_PTR   EQU     123
164 69 rehayes
 
165 89 rehayes
        DC.W    END_CODE_
166
        DS.W    8
167
        DC.B    $56
168
        DS.B    11
169 69 rehayes
 
170 89 rehayes
        ALIGN   1
171 69 rehayes
 
172
;-------------------------------------------------------------------------------
173
;   Place where undefined interrupts go
174
;-------------------------------------------------------------------------------
175
_ERROR
176 89 rehayes
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
177
        LDH     R2,#$80
178
        LDL     R3,#$ff
179
        STB     R3,(R2,#0)
180 69 rehayes
 
181
        SIF
182 89 rehayes
        RTS
183 69 rehayes
 
184
 
185
;-------------------------------------------------------------------------------
186
;   Test IRQ
187
;-------------------------------------------------------------------------------
188
_IRQ1
189 89 rehayes
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
190
        LDH     R2,#$80    ; R3 = Testbench base address = Checkpoint address
191
        LDL     R3,#1      ; Checkpoint Value
192
        STB     R3,(R2,#0) ; Send Checkpoint value
193 69 rehayes
 
194 89 rehayes
        ;Test Interrupt
195
        STW     R3,(R2,#$0a)    ; Should be even offsets
196 69 rehayes
_TB_POLL_1
197 89 rehayes
        LDW     R4,(R2,#$0a)    ;
198
        CMP     R3,R4           ;
199
        BEQ     _TB_POLL_1
200 69 rehayes
 
201
_END_1
202 89 rehayes
        LDL     R3,#101
203
        STB     R3,(R2,#0) ; Send Checkpoint value
204 69 rehayes
 
205 89 rehayes
        SIF
206
        RTS
207 69 rehayes
 
208
 
209
;-------------------------------------------------------------------------------
210
;   Test Interrupt
211
;-------------------------------------------------------------------------------
212
_IRQ2
213 89 rehayes
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
214
        LDH     R2,#$80    ; R3 = Testbench base address = Checkpoint address
215
        LDL     R3,#2      ; Checkpoint Value
216
        STB     R3,(R2,#0) ; Send Checkpoint value
217 69 rehayes
 
218 89 rehayes
        ;Test Interrupt
219
        STW     R3,(R2,#$0a)    ; Should be even offsets
220 69 rehayes
_TB_POLL_2
221 89 rehayes
        LDW     R4,(R2,#$0a)    ;
222
        CMP     R3,R4           ;
223
        BEQ     _TB_POLL_2
224 69 rehayes
 
225
_END_2
226 89 rehayes
        LDL     R3,#102
227
        STB     R3,(R2,#0) ; Send Checkpoint value
228 69 rehayes
 
229 89 rehayes
        SIF
230
        RTS
231 69 rehayes
 
232
 
233
;-------------------------------------------------------------------------------
234
;   Test Interrupt
235
;-------------------------------------------------------------------------------
236
_IRQ3
237 89 rehayes
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
238
        LDH     R2,#$80    ; R3 = Testbench base address = Checkpoint address
239
        LDL     R3,#3      ; Checkpoint Value
240
        STB     R3,(R2,#0) ; Send Checkpoint value
241 69 rehayes
 
242 89 rehayes
        ;Test Interrupt
243
        STW     R3,(R2,#$0a)    ; Should be even offsets
244 69 rehayes
_TB_POLL_3
245 89 rehayes
        LDW     R4,(R2,#$0a)    ;
246
        CMP     R3,R4           ;
247
        BEQ     _TB_POLL_3
248 69 rehayes
 
249
_END_3
250 89 rehayes
        LDL     R3,#103
251
        STB     R3,(R2,#0) ; Send Checkpoint value
252 69 rehayes
 
253 89 rehayes
        SIF
254
        RTS
255 69 rehayes
 
256
 
257
;-------------------------------------------------------------------------------
258
;   Test Interrupt
259
;-------------------------------------------------------------------------------
260
_IRQ4
261 89 rehayes
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
262
        LDH     R2,#$80
263
        LDL     R3,#4      ; Checkpoint Value
264
        STB     R3,(R2,#0)
265 69 rehayes
 
266 89 rehayes
        ;Test Interrupt
267
        STW     R3,(R2,#$0a)    ; Should be even offsets
268 69 rehayes
_TB_POLL_4
269 89 rehayes
        LDW     R4,(R2,#$0a)    ;
270
        CMP     R3,R4           ;
271
        BEQ     _TB_POLL_4
272 69 rehayes
 
273
_END_4
274 89 rehayes
        LDL     R3,#8
275
        STB     R3,(R2,#0) ; Send Checkpoint value
276 69 rehayes
 
277 89 rehayes
        SIF
278
        RTS
279 69 rehayes
 
280
 
281
;-------------------------------------------------------------------------------
282
;   Test Interrupt
283
;-------------------------------------------------------------------------------
284
_IRQ5
285 89 rehayes
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
286
        LDH     R2,#$80
287
        LDL     R3,#$05    ; Checkpoint Value
288
        STB     R3,(R2,#0)
289 69 rehayes
 
290 89 rehayes
        ;Test Interrupt
291
        STW     R3,(R2,#$0a)    ; Should be even offsets
292 69 rehayes
_TB_POLL_5
293 89 rehayes
        LDW     R4,(R2,#$0a)    ;
294
        CMP     R3,R4           ;
295
        BEQ     _TB_POLL_5
296 69 rehayes
 
297
_END_5
298 89 rehayes
        LDL     R3,#10
299
        STB     R3,(R2,#0) ; Send Checkpoint value
300 69 rehayes
 
301 89 rehayes
        SIF
302
        RTS
303 69 rehayes
 
304
 
305
;-------------------------------------------------------------------------------
306
;   Test Interrupt
307
;-------------------------------------------------------------------------------
308
_IRQ6
309 89 rehayes
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
310
        LDH     R2,#$80
311
        LDL     R3,#6      ; Checkpoint Value
312
        STB     R3,(R2,#0)
313 69 rehayes
 
314 89 rehayes
        ;Test Interrupt
315
        STW     R3,(R2,#$0a)    ; Should be even offsets
316 69 rehayes
_TB_POLL_6
317 89 rehayes
        LDW     R4,(R2,#$0a)    ;
318
        CMP     R3,R4           ;
319
        BEQ     _TB_POLL_6
320 69 rehayes
 
321
_END_6
322 89 rehayes
        LDL     R3,#$12
323
        STB     R3,(R2,#0) ; Send Checkpoint value
324 69 rehayes
 
325 89 rehayes
        SIF
326
        RTS
327 69 rehayes
 
328
 
329
;-------------------------------------------------------------------------------
330
;   Test Interrupt
331
;-------------------------------------------------------------------------------
332
_IRQ7
333 89 rehayes
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
334
        LDH     R2,#$80
335
        LDL     R3,#7      ; Checkpoint Value
336
        STB     R3,(R2,#0)
337 69 rehayes
 
338 89 rehayes
        ;Test Interrupt
339
        STW     R3,(R2,#$0a)    ; Should be even offsets
340 69 rehayes
_TB_POLL_7
341 89 rehayes
        LDW     R4,(R2,#$0a)    ;
342
        CMP     R3,R4           ;
343
        BEQ     _TB_POLL_7
344 69 rehayes
 
345
_END_7
346 89 rehayes
        LDL     R3,#14
347
        STB     R3,(R2,#0) ; Send Checkpoint value
348 69 rehayes
 
349 89 rehayes
        SIF
350
        RTS
351 69 rehayes
 
352
 
353
;-------------------------------------------------------------------------------
354
;   Test Interrupt
355
;-------------------------------------------------------------------------------
356
_IRQ8
357 89 rehayes
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
358
        LDH     R2,#$80
359
        LDL     R3,#8      ; Checkpoint Value
360
        STB     R3,(R2,#0)
361 69 rehayes
 
362 89 rehayes
        ;Test Interrupt
363
        STW     R3,(R2,#$0a)    ; Should be even offsets
364 69 rehayes
_TB_POLL_8
365 89 rehayes
        LDW     R4,(R2,#$0a)    ;
366
        CMP     R3,R4           ;
367
        BEQ     _TB_POLL_8
368 69 rehayes
 
369
_END_8
370 89 rehayes
        LDL     R3,#16
371
        STB     R3,(R2,#0) ; Send Checkpoint value
372 69 rehayes
 
373 89 rehayes
        SIF
374
        RTS
375 69 rehayes
 
376
 
377
;-------------------------------------------------------------------------------
378
;   Test Interrupt
379
;-------------------------------------------------------------------------------
380
_IRQ9
381 89 rehayes
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
382
        LDH     R2,#$80
383
        LDL     R3,#9      ; Checkpoint Value
384
        STB     R3,(R2,#0)
385 69 rehayes
 
386 89 rehayes
        ;Test Interrupt
387
        STW     R3,(R2,#$0a)    ; Should be even offsets
388 69 rehayes
_TB_POLL_9
389 89 rehayes
        LDW     R4,(R2,#$0a)    ;
390
        CMP     R3,R4           ;
391
        BEQ     _TB_POLL_9
392 69 rehayes
 
393
_END_9
394 89 rehayes
        LDL     R3,#18
395
        STB     R3,(R2,#0) ; Send Checkpoint value
396 69 rehayes
 
397 89 rehayes
        SIF
398
        RTS
399 69 rehayes
 
400
 
401
;-------------------------------------------------------------------------------
402
;   Test Interrupt
403
;-------------------------------------------------------------------------------
404
_IRQ10
405 89 rehayes
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
406
        LDH     R2,#$80
407
        LDL     R3,#10     ; Checkpoint Value
408
        STB     R3,(R2,#0)
409 69 rehayes
 
410 89 rehayes
        ;Test Interrupt
411
        STW     R3,(R2,#$0a)    ; Should be even offsets
412 69 rehayes
_TB_POLL_10
413 89 rehayes
        LDW     R4,(R2,#$0a)    ;
414
        CMP     R3,R4           ;
415
        BEQ     _TB_POLL_10
416 69 rehayes
 
417
_END_10
418 89 rehayes
        LDL     R3,#$20
419
        STB     R3,(R2,#0) ; Send Checkpoint value
420 69 rehayes
 
421 89 rehayes
        SIF
422
        RTS
423 69 rehayes
 
424
 
425
;-------------------------------------------------------------------------------
426
;-------------------------------------------------------------------------------
427
END_CODE_
428
 
429 89 rehayes
        ORG     $8000 ; Special Testbench Addresses
430
_BENCH  DS.W    16
431 69 rehayes
 
432
 
433
 
434
 

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