URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [sw/] [xgate_test_code/] [irq_test/] [irq_test.s] - Blame information for rev 92

Go to most recent revision | Details | Compare with Previous | View Log


; 345678901234567890123456789012345678901234567890123456789012345678901234567890
; Interrupt test for xgate RISC processor core
; Bob Hayes - May 11 2010
 
 
        CPU     XGATE
 
        ORG     $fe00
        DS.W    2       ; reserve two words at channel 0
        ; channel 1
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 2
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 3
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 4
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 5
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 6
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 7
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 8
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 9
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 10
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 11
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 12
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 13
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 14
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 15
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 16
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 17
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 18
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 19
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 20
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 21
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 22
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 23
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 24
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 25
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 26
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 27
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 28
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 29
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 30
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 31
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 32
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 33
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 34
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 35
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 36
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 37
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 38
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 39
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 40
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 41
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 42
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 43
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 44
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 45
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 46
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 47
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 48
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 49
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 50
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 51
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 52
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 53
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 54
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 55
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 56
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 57
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 58
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 59
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 60
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 61
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 62
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 63
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 64
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 65
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 66
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 67
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 68
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 69
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 70
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 71
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 72
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 73
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 74
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 75
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 76
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 77
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 78
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 79
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 80
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 81
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 82
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 83
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 84
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 85
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 86
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 87
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 88
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 89
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 80
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 81
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 82
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 83
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 84
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 85
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 86
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 87
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 88
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 89
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 100
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 101
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 102
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 103
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 104
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 105
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 106
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 107
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 108
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 109
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 110
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 111
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 112
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 113
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 114
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 115
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 116
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 117
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 118
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 119
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 120
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 121
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 122
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 123
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 124
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 125
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 126
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
        ; channel 127
        DC.W    _IRQn   ; point to start address
        DC.W    V_PTR   ; point to initial variables
 
        ORG     $2000 ; with comment
 
V_PTR   DC.W    $0000  ; All Variable Pointers are set to here
 
        DC.W    END_CODE_
        DS.W    8
        DC.B    $56
        DS.B    11
 
        ALIGN   1
 
;-------------------------------------------------------------------------------
;   Place where undefined interrupts go
;-------------------------------------------------------------------------------
_ERROR
        LDL     R2,#$04    ; Sent Message to Testbench Error Register
        LDH     R2,#$80
        LDL     R3,#$ff
        STB     R3,(R2,#0)
 
        SIF
        RTS
 
 
;-------------------------------------------------------------------------------
;   Test IRQ - All interrupts are pointed here. For proper function the interrupts
;               must be activated in sequential order. The data at address V_PTR
;               holds the last interrupt processed and is incremented and
;               re-stored as part of the interrup service routine.
;-------------------------------------------------------------------------------
_IRQn
        LDL     R2,#$00    ; Sent Message to Testbench Check Point Register
        LDH     R2,#$80    ; R3 = Testbench base address = Checkpoint address
        LDW     R3,(R1,#0) ; Load Checkpoint Value from V_PTR address
        ADDL    R3,#1      ; Increment interrupt number
        STW     R3,(R1,#0) ; Store new value for next interrupt
        STB     R3,(R2,#0) ; Send Checkpoint value
 
        ;Test Interrupt
        STW     R3,(R2,#$0a)    ; TB_SEMPHORE address - Should be even offsets
_TB_POLL_n
        LDW     R4,(R2,#$0a)    ;
        CMP     R3,R4           ;
        BEQ     _TB_POLL_n
 
_END_n
        ADDL    R3,#100
        STB     R3,(R2,#0) ; Send Checkpoint value
 
        SIF
        RTS
 
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
END_CODE_
 
        ORG     $8000 ; Special Testbench Addresses
_BENCH  DS.W    16
 
 
 
 

Line No.	Rev	Author	Line
1	69	rehayes	`; 345678901234567890123456789012345678901234567890123456789012345678901234567890`
2			`; Interrupt test for xgate RISC processor core`
3			`; Bob Hayes - May 11 2010`
4
5
6	89	rehayes	`CPU XGATE`
7	69	rehayes
8	89	rehayes	`ORG $fe00`
9			`DS.W 2 ; reserve two words at channel 0`
10			`; channel 1`
11	91	rehayes	`DC.W _IRQn ; point to start address`
12	89	rehayes	`DC.W V_PTR ; point to initial variables`
13			`; channel 2`
14	91	rehayes	`DC.W _IRQn ; point to start address`
15	89	rehayes	`DC.W V_PTR ; point to initial variables`
16			`; channel 3`
17	91	rehayes	`DC.W _IRQn ; point to start address`
18	89	rehayes	`DC.W V_PTR ; point to initial variables`
19			`; channel 4`
20	91	rehayes	`DC.W _IRQn ; point to start address`
21	89	rehayes	`DC.W V_PTR ; point to initial variables`
22			`; channel 5`
23	91	rehayes	`DC.W _IRQn ; point to start address`
24	89	rehayes	`DC.W V_PTR ; point to initial variables`
25			`; channel 6`
26	91	rehayes	`DC.W _IRQn ; point to start address`
27	89	rehayes	`DC.W V_PTR ; point to initial variables`
28			`; channel 7`
29	91	rehayes	`DC.W _IRQn ; point to start address`
30	89	rehayes	`DC.W V_PTR ; point to initial variables`
31			`; channel 8`
32	91	rehayes	`DC.W _IRQn ; point to start address`
33	89	rehayes	`DC.W V_PTR ; point to initial variables`
34			`; channel 9`
35	91	rehayes	`DC.W _IRQn ; point to start address`
36	89	rehayes	`DC.W V_PTR ; point to initial variables`
37			`; channel 10`
38	91	rehayes	`DC.W _IRQn ; point to start address`
39	89	rehayes	`DC.W V_PTR ; point to initial variables`
40			`; channel 11`
41	91	rehayes	`DC.W _IRQn ; point to start address`
42	89	rehayes	`DC.W V_PTR ; point to initial variables`
43			`; channel 12`
44	91	rehayes	`DC.W _IRQn ; point to start address`
45	89	rehayes	`DC.W V_PTR ; point to initial variables`
46			`; channel 13`
47	91	rehayes	`DC.W _IRQn ; point to start address`
48	89	rehayes	`DC.W V_PTR ; point to initial variables`
49			`; channel 14`
50	91	rehayes	`DC.W _IRQn ; point to start address`
51	89	rehayes	`DC.W V_PTR ; point to initial variables`
52			`; channel 15`
53	91	rehayes	`DC.W _IRQn ; point to start address`
54	89	rehayes	`DC.W V_PTR ; point to initial variables`
55			`; channel 16`
56	91	rehayes	`DC.W _IRQn ; point to start address`
57	89	rehayes	`DC.W V_PTR ; point to initial variables`
58			`; channel 17`
59	91	rehayes	`DC.W _IRQn ; point to start address`
60	89	rehayes	`DC.W V_PTR ; point to initial variables`
61			`; channel 18`
62	91	rehayes	`DC.W _IRQn ; point to start address`
63	89	rehayes	`DC.W V_PTR ; point to initial variables`
64			`; channel 19`
65	91	rehayes	`DC.W _IRQn ; point to start address`
66	89	rehayes	`DC.W V_PTR ; point to initial variables`
67			`; channel 20`
68	91	rehayes	`DC.W _IRQn ; point to start address`
69	89	rehayes	`DC.W V_PTR ; point to initial variables`
70			`; channel 21`
71	91	rehayes	`DC.W _IRQn ; point to start address`
72	89	rehayes	`DC.W V_PTR ; point to initial variables`
73			`; channel 22`
74	91	rehayes	`DC.W _IRQn ; point to start address`
75	89	rehayes	`DC.W V_PTR ; point to initial variables`
76			`; channel 23`
77	91	rehayes	`DC.W _IRQn ; point to start address`
78	89	rehayes	`DC.W V_PTR ; point to initial variables`
79			`; channel 24`
80	91	rehayes	`DC.W _IRQn ; point to start address`
81	89	rehayes	`DC.W V_PTR ; point to initial variables`
82			`; channel 25`
83	91	rehayes	`DC.W _IRQn ; point to start address`
84	89	rehayes	`DC.W V_PTR ; point to initial variables`
85			`; channel 26`
86	91	rehayes	`DC.W _IRQn ; point to start address`
87	89	rehayes	`DC.W V_PTR ; point to initial variables`
88			`; channel 27`
89	91	rehayes	`DC.W _IRQn ; point to start address`
90	89	rehayes	`DC.W V_PTR ; point to initial variables`
91			`; channel 28`
92	91	rehayes	`DC.W _IRQn ; point to start address`
93	89	rehayes	`DC.W V_PTR ; point to initial variables`
94			`; channel 29`
95	91	rehayes	`DC.W _IRQn ; point to start address`
96	89	rehayes	`DC.W V_PTR ; point to initial variables`
97			`; channel 30`
98	91	rehayes	`DC.W _IRQn ; point to start address`
99	89	rehayes	`DC.W V_PTR ; point to initial variables`
100			`; channel 31`
101	91	rehayes	`DC.W _IRQn ; point to start address`
102	89	rehayes	`DC.W V_PTR ; point to initial variables`
103			`; channel 32`
104	91	rehayes	`DC.W _IRQn ; point to start address`
105	89	rehayes	`DC.W V_PTR ; point to initial variables`
106			`; channel 33`
107	91	rehayes	`DC.W _IRQn ; point to start address`
108	89	rehayes	`DC.W V_PTR ; point to initial variables`
109			`; channel 34`
110	91	rehayes	`DC.W _IRQn ; point to start address`
111	89	rehayes	`DC.W V_PTR ; point to initial variables`
112			`; channel 35`
113	91	rehayes	`DC.W _IRQn ; point to start address`
114	89	rehayes	`DC.W V_PTR ; point to initial variables`
115			`; channel 36`
116	91	rehayes	`DC.W _IRQn ; point to start address`
117	89	rehayes	`DC.W V_PTR ; point to initial variables`
118			`; channel 37`
119	91	rehayes	`DC.W _IRQn ; point to start address`
120	89	rehayes	`DC.W V_PTR ; point to initial variables`
121			`; channel 38`
122	91	rehayes	`DC.W _IRQn ; point to start address`
123	89	rehayes	`DC.W V_PTR ; point to initial variables`
124			`; channel 39`
125	91	rehayes	`DC.W _IRQn ; point to start address`
126	89	rehayes	`DC.W V_PTR ; point to initial variables`
127			`; channel 40`
128	91	rehayes	`DC.W _IRQn ; point to start address`
129	89	rehayes	`DC.W V_PTR ; point to initial variables`
130			`; channel 41`
131	91	rehayes	`DC.W _IRQn ; point to start address`
132	89	rehayes	`DC.W V_PTR ; point to initial variables`
133			`; channel 42`
134	91	rehayes	`DC.W _IRQn ; point to start address`
135	89	rehayes	`DC.W V_PTR ; point to initial variables`
136			`; channel 43`
137	91	rehayes	`DC.W _IRQn ; point to start address`
138	89	rehayes	`DC.W V_PTR ; point to initial variables`
139			`; channel 44`
140	91	rehayes	`DC.W _IRQn ; point to start address`
141	89	rehayes	`DC.W V_PTR ; point to initial variables`
142			`; channel 45`
143	91	rehayes	`DC.W _IRQn ; point to start address`
144	89	rehayes	`DC.W V_PTR ; point to initial variables`
145			`; channel 46`
146	91	rehayes	`DC.W _IRQn ; point to start address`
147	89	rehayes	`DC.W V_PTR ; point to initial variables`
148			`; channel 47`
149	91	rehayes	`DC.W _IRQn ; point to start address`
150	89	rehayes	`DC.W V_PTR ; point to initial variables`
151			`; channel 48`
152	91	rehayes	`DC.W _IRQn ; point to start address`
153	89	rehayes	`DC.W V_PTR ; point to initial variables`
154			`; channel 49`
155	91	rehayes	`DC.W _IRQn ; point to start address`
156	89	rehayes	`DC.W V_PTR ; point to initial variables`
157			`; channel 50`
158	91	rehayes	`DC.W _IRQn ; point to start address`
159	89	rehayes	`DC.W V_PTR ; point to initial variables`
160	91	rehayes	`; channel 51`
161			`DC.W _IRQn ; point to start address`
162			`DC.W V_PTR ; point to initial variables`
163			`; channel 52`
164			`DC.W _IRQn ; point to start address`
165			`DC.W V_PTR ; point to initial variables`
166			`; channel 53`
167			`DC.W _IRQn ; point to start address`
168			`DC.W V_PTR ; point to initial variables`
169			`; channel 54`
170			`DC.W _IRQn ; point to start address`
171			`DC.W V_PTR ; point to initial variables`
172			`; channel 55`
173			`DC.W _IRQn ; point to start address`
174			`DC.W V_PTR ; point to initial variables`
175			`; channel 56`
176			`DC.W _IRQn ; point to start address`
177			`DC.W V_PTR ; point to initial variables`
178			`; channel 57`
179			`DC.W _IRQn ; point to start address`
180			`DC.W V_PTR ; point to initial variables`
181			`; channel 58`
182			`DC.W _IRQn ; point to start address`
183			`DC.W V_PTR ; point to initial variables`
184			`; channel 59`
185			`DC.W _IRQn ; point to start address`
186			`DC.W V_PTR ; point to initial variables`
187			`; channel 60`
188			`DC.W _IRQn ; point to start address`
189			`DC.W V_PTR ; point to initial variables`
190			`; channel 61`
191			`DC.W _IRQn ; point to start address`
192			`DC.W V_PTR ; point to initial variables`
193			`; channel 62`
194			`DC.W _IRQn ; point to start address`
195			`DC.W V_PTR ; point to initial variables`
196			`; channel 63`
197			`DC.W _IRQn ; point to start address`
198			`DC.W V_PTR ; point to initial variables`
199			`; channel 64`
200			`DC.W _IRQn ; point to start address`
201			`DC.W V_PTR ; point to initial variables`
202			`; channel 65`
203			`DC.W _IRQn ; point to start address`
204			`DC.W V_PTR ; point to initial variables`
205			`; channel 66`
206			`DC.W _IRQn ; point to start address`
207			`DC.W V_PTR ; point to initial variables`
208			`; channel 67`
209			`DC.W _IRQn ; point to start address`
210			`DC.W V_PTR ; point to initial variables`
211			`; channel 68`
212			`DC.W _IRQn ; point to start address`
213			`DC.W V_PTR ; point to initial variables`
214			`; channel 69`
215			`DC.W _IRQn ; point to start address`
216			`DC.W V_PTR ; point to initial variables`
217			`; channel 70`
218			`DC.W _IRQn ; point to start address`
219			`DC.W V_PTR ; point to initial variables`
220			`; channel 71`
221			`DC.W _IRQn ; point to start address`
222			`DC.W V_PTR ; point to initial variables`
223			`; channel 72`
224			`DC.W _IRQn ; point to start address`
225			`DC.W V_PTR ; point to initial variables`
226			`; channel 73`
227			`DC.W _IRQn ; point to start address`
228			`DC.W V_PTR ; point to initial variables`
229			`; channel 74`
230			`DC.W _IRQn ; point to start address`
231			`DC.W V_PTR ; point to initial variables`
232			`; channel 75`
233			`DC.W _IRQn ; point to start address`
234			`DC.W V_PTR ; point to initial variables`
235			`; channel 76`
236			`DC.W _IRQn ; point to start address`
237			`DC.W V_PTR ; point to initial variables`
238			`; channel 77`
239			`DC.W _IRQn ; point to start address`
240			`DC.W V_PTR ; point to initial variables`
241			`; channel 78`
242			`DC.W _IRQn ; point to start address`
243			`DC.W V_PTR ; point to initial variables`
244			`; channel 79`
245			`DC.W _IRQn ; point to start address`
246			`DC.W V_PTR ; point to initial variables`
247			`; channel 80`
248			`DC.W _IRQn ; point to start address`
249			`DC.W V_PTR ; point to initial variables`
250			`; channel 81`
251			`DC.W _IRQn ; point to start address`
252			`DC.W V_PTR ; point to initial variables`
253			`; channel 82`
254			`DC.W _IRQn ; point to start address`
255			`DC.W V_PTR ; point to initial variables`
256			`; channel 83`
257			`DC.W _IRQn ; point to start address`
258			`DC.W V_PTR ; point to initial variables`
259			`; channel 84`
260			`DC.W _IRQn ; point to start address`
261			`DC.W V_PTR ; point to initial variables`
262			`; channel 85`
263			`DC.W _IRQn ; point to start address`
264			`DC.W V_PTR ; point to initial variables`
265			`; channel 86`
266			`DC.W _IRQn ; point to start address`
267			`DC.W V_PTR ; point to initial variables`
268			`; channel 87`
269			`DC.W _IRQn ; point to start address`
270			`DC.W V_PTR ; point to initial variables`
271			`; channel 88`
272			`DC.W _IRQn ; point to start address`
273			`DC.W V_PTR ; point to initial variables`
274			`; channel 89`
275			`DC.W _IRQn ; point to start address`
276			`DC.W V_PTR ; point to initial variables`
277			`; channel 80`
278			`DC.W _IRQn ; point to start address`
279			`DC.W V_PTR ; point to initial variables`
280			`; channel 81`
281			`DC.W _IRQn ; point to start address`
282			`DC.W V_PTR ; point to initial variables`
283			`; channel 82`
284			`DC.W _IRQn ; point to start address`
285			`DC.W V_PTR ; point to initial variables`
286			`; channel 83`
287			`DC.W _IRQn ; point to start address`
288			`DC.W V_PTR ; point to initial variables`
289			`; channel 84`
290			`DC.W _IRQn ; point to start address`
291			`DC.W V_PTR ; point to initial variables`
292			`; channel 85`
293			`DC.W _IRQn ; point to start address`
294			`DC.W V_PTR ; point to initial variables`
295			`; channel 86`
296			`DC.W _IRQn ; point to start address`
297			`DC.W V_PTR ; point to initial variables`
298			`; channel 87`
299			`DC.W _IRQn ; point to start address`
300			`DC.W V_PTR ; point to initial variables`
301			`; channel 88`
302			`DC.W _IRQn ; point to start address`
303			`DC.W V_PTR ; point to initial variables`
304			`; channel 89`
305			`DC.W _IRQn ; point to start address`
306			`DC.W V_PTR ; point to initial variables`
307			`; channel 100`
308			`DC.W _IRQn ; point to start address`
309			`DC.W V_PTR ; point to initial variables`
310			`; channel 101`
311			`DC.W _IRQn ; point to start address`
312			`DC.W V_PTR ; point to initial variables`
313			`; channel 102`
314			`DC.W _IRQn ; point to start address`
315			`DC.W V_PTR ; point to initial variables`
316			`; channel 103`
317			`DC.W _IRQn ; point to start address`
318			`DC.W V_PTR ; point to initial variables`
319			`; channel 104`
320			`DC.W _IRQn ; point to start address`
321			`DC.W V_PTR ; point to initial variables`
322			`; channel 105`
323			`DC.W _IRQn ; point to start address`
324			`DC.W V_PTR ; point to initial variables`
325			`; channel 106`
326			`DC.W _IRQn ; point to start address`
327			`DC.W V_PTR ; point to initial variables`
328			`; channel 107`
329			`DC.W _IRQn ; point to start address`
330			`DC.W V_PTR ; point to initial variables`
331			`; channel 108`
332			`DC.W _IRQn ; point to start address`
333			`DC.W V_PTR ; point to initial variables`
334			`; channel 109`
335			`DC.W _IRQn ; point to start address`
336			`DC.W V_PTR ; point to initial variables`
337			`; channel 110`
338			`DC.W _IRQn ; point to start address`
339			`DC.W V_PTR ; point to initial variables`
340			`; channel 111`
341			`DC.W _IRQn ; point to start address`
342			`DC.W V_PTR ; point to initial variables`
343			`; channel 112`
344			`DC.W _IRQn ; point to start address`
345			`DC.W V_PTR ; point to initial variables`
346			`; channel 113`
347			`DC.W _IRQn ; point to start address`
348			`DC.W V_PTR ; point to initial variables`
349			`; channel 114`
350			`DC.W _IRQn ; point to start address`
351			`DC.W V_PTR ; point to initial variables`
352			`; channel 115`
353			`DC.W _IRQn ; point to start address`
354			`DC.W V_PTR ; point to initial variables`
355			`; channel 116`
356			`DC.W _IRQn ; point to start address`
357			`DC.W V_PTR ; point to initial variables`
358			`; channel 117`
359			`DC.W _IRQn ; point to start address`
360			`DC.W V_PTR ; point to initial variables`
361			`; channel 118`
362			`DC.W _IRQn ; point to start address`
363			`DC.W V_PTR ; point to initial variables`
364			`; channel 119`
365			`DC.W _IRQn ; point to start address`
366			`DC.W V_PTR ; point to initial variables`
367			`; channel 120`
368			`DC.W _IRQn ; point to start address`
369			`DC.W V_PTR ; point to initial variables`
370			`; channel 121`
371			`DC.W _IRQn ; point to start address`
372			`DC.W V_PTR ; point to initial variables`
373			`; channel 122`
374			`DC.W _IRQn ; point to start address`
375			`DC.W V_PTR ; point to initial variables`
376			`; channel 123`
377			`DC.W _IRQn ; point to start address`
378			`DC.W V_PTR ; point to initial variables`
379			`; channel 124`
380			`DC.W _IRQn ; point to start address`
381			`DC.W V_PTR ; point to initial variables`
382			`; channel 125`
383			`DC.W _IRQn ; point to start address`
384			`DC.W V_PTR ; point to initial variables`
385			`; channel 126`
386			`DC.W _IRQn ; point to start address`
387			`DC.W V_PTR ; point to initial variables`
388			`; channel 127`
389			`DC.W _IRQn ; point to start address`
390			`DC.W V_PTR ; point to initial variables`
391	69	rehayes
392	89	rehayes	`ORG $2000 ; with comment`
393	69	rehayes
394	91	rehayes	`V_PTR DC.W $0000 ; All Variable Pointers are set to here`
395	69	rehayes
396	89	rehayes	`DC.W END_CODE_`
397			`DS.W 8`
398			`DC.B $56`
399			`DS.B 11`
400	69	rehayes
401	89	rehayes	`ALIGN 1`
402	69	rehayes
403			`;-------------------------------------------------------------------------------`
404			`; Place where undefined interrupts go`
405			`;-------------------------------------------------------------------------------`
406			`_ERROR`
407	89	rehayes	`LDL R2,#$04 ; Sent Message to Testbench Error Register`
408			`LDH R2,#$80`
409			`LDL R3,#$ff`
410			`STB R3,(R2,#0)`
411	69	rehayes
412			`SIF`
413	89	rehayes	`RTS`
414	69	rehayes
415
416			`;-------------------------------------------------------------------------------`
417	91	rehayes	`; Test IRQ - All interrupts are pointed here. For proper function the interrupts`
418			`; must be activated in sequential order. The data at address V_PTR`
419			`; holds the last interrupt processed and is incremented and`
420			`; re-stored as part of the interrup service routine.`
421	69	rehayes	`;-------------------------------------------------------------------------------`
422	91	rehayes	`_IRQn`
423	89	rehayes	`LDL R2,#$00 ; Sent Message to Testbench Check Point Register`
424			`LDH R2,#$80 ; R3 = Testbench base address = Checkpoint address`
425	91	rehayes	`LDW R3,(R1,#0) ; Load Checkpoint Value from V_PTR address`
426			`ADDL R3,#1 ; Increment interrupt number`
427			`STW R3,(R1,#0) ; Store new value for next interrupt`
428	89	rehayes	`STB R3,(R2,#0) ; Send Checkpoint value`
429	69	rehayes
430	89	rehayes	`;Test Interrupt`
431	91	rehayes	`STW R3,(R2,#$0a) ; TB_SEMPHORE address - Should be even offsets`
432			`_TB_POLL_n`
433	89	rehayes	`LDW R4,(R2,#$0a) ;`
434			`CMP R3,R4 ;`
435	91	rehayes	`BEQ _TB_POLL_n`
436	69	rehayes
437	91	rehayes	`_END_n`
438			`ADDL R3,#100`
439	89	rehayes	`STB R3,(R2,#0) ; Send Checkpoint value`
440	69	rehayes
441	89	rehayes	`SIF`
442			`RTS`
443	69	rehayes
444			`;-------------------------------------------------------------------------------`
445			`;-------------------------------------------------------------------------------`
446			`END_CODE_`
447
448	89	rehayes	`ORG $8000 ; Special Testbench Addresses`
449			`_BENCH DS.W 16`
450	69	rehayes
451
452
453

Browse

Tools

Subversion Repositories xgate

[/] [xgate/] [trunk/] [sw/] [xgate_test_code/] [irq_test/] [irq_test.s] - Blame information for rev 92