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rehayes |
; 345678901234567890123456789012345678901234567890123456789012345678901234567890
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; PC underflow/overflow test for xgate RISC processor core
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; Bob Hayes - Jan 21 2012
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CPU XGATE
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;-------------------------------------------------------------------------------
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; Error Code - Program should never get here
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;-------------------------------------------------------------------------------
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ORG $0000 ;
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_START_OF_MEM
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LDL R2,#$04 ; Sent Message to Testbench Error Register
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LDH R2,#$80
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LDL R3,#$08
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STB R3,(R2,#0)
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SIF
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RTS
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BRA _START_OF_MEM ; Final hex code for test will need hack
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BRA _START_OF_MEM ; Final hex code for test will need hack
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BRA _START_OF_MEM ; Final hex code for test will need hack
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BRA _START_OF_MEM ; Final hex code for test will need hack
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BRA _START_OF_MEM ; Final hex code for test will need hack
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BRA _START_OF_MEM ; Final hex code for test will need hack
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BRA _START_OF_MEM ; Final hex code for test will need hack
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;-------------------------------------------------------------------------------
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; Backward branch past #$0000
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;-------------------------------------------------------------------------------
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ORG $0200 ;
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_START3
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LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDH R2,#$80
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LDL R3,#$01
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STB R3,(R2,#0)
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STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
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BRA _START_OF_MEM ; Final hex code for test will need hack
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;-------------------------------------------------------------------------------
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; Dummy space to store initial variables for default interrupts
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ORG $2000 ; with comment
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V_PTR DC.W $0000 ; All Variable Pointers are set to here
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DC.W $AAAA
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DS.W 8
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DC.B $56
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DS.B 11
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ALIGN 1
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;-------------------------------------------------------------------------------
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; Place where undefined interrupts go
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;-------------------------------------------------------------------------------
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_ERROR
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LDL R2,#$04 ; Sent Message to Testbench Error Register
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LDH R2,#$80
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LDL R3,#$ff
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STB R3,(R2,#0)
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SIF
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RTS
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;-------------------------------------------------------------------------------
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ORG $8800 ; $8000 reserved for testbench
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DC.W $5555 ; reserve two words at channel 0
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DC.W $AAAA
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; channel 1
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DC.W _START ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 2
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DC.W _START2 ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 3
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DC.W _START3 ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 4
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 5
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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; channel 6
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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;-------------------------------------------------------------------------------
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ORG $fe00
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DC.W $3c3c
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DC.W $9696
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DC.W $a5a5
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DC.W $5a5a
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DC.W $7878
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DC.W $8181
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;-------------------------------------------------------------------------------
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; Foward branch past #$ffff
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;-------------------------------------------------------------------------------
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ORG $FFC0 ;
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_START2
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LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDH R2,#$80
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LDL R3,#$01
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STB R3,(R2,#0)
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STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
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BRA _END_OFCODE ; Final hex code for test will need hack
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;-------------------------------------------------------------------------------
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; Test PC single step past #$ffff
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;-------------------------------------------------------------------------------
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ORG $FFE8 ;
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_START
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LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDH R2,#$80
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LDL R3,#$01
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STB R3,(R2,#0)
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STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
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NOP
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NOP
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NOP
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NOP
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NOP
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_END_OFCODE
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NOP
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