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cleberCAG |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// This file is part of the "10GE LL MAC" project ////
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//// http://www.opencores.org/cores/xge_ll_mac/ ////
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//// ////
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//// This project is derived from the "10GE MAC" project of ////
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//// A. Tanguay (antanguay@opencores.org) by Andreas Peters ////
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//// for his Diploma Thesis at the University of Heidelberg. ////
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//// The Thesis was supervised by Christian Leber ////
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//// ////
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//// Author(s): ////
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//// - Andreas Peters ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008-2012 AUTHORS. All rights reserved. ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//`include "technology.h"
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`include "oc_mac.h"
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`default_nettype none
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module oc_mac (
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input wire res_n,
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input wire clk,
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input wire tx_start,
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input wire [63:0] tx_data,
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input wire [7:0] tx_data_valid,
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input wire [63:0] xgmii_rxd,
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input wire [7:0] xgmii_rxc,
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output wire tx_ack,
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output wire rx_bad_frame,
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output wire rx_good_frame,
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output wire [63:0] rx_data,
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output wire [7:0] rx_data_valid,
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output wire [7:0] xgmii_txc,
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output wire[63:0] xgmii_txd
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);
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wire [1:0] local_fault_msg_det;
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wire [1:0] remote_fault_msg_det;
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wire status_fragment_error_tog;
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wire status_pause_frame_rx_tog;
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wire [63:0] txdfifo_wdata;
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wire [7:0] txdfifo_wstatus;
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wire [63:0] xgmii_data_in;
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wire [7:0] xgmii_data_status;
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rx_enqueue rx_eq0(
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// Outputs
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.xgmii_data_in (xgmii_data_in),
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.xgmii_data_status (xgmii_data_status),
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.local_fault_msg_det (local_fault_msg_det),
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.remote_fault_msg_det (remote_fault_msg_det),
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.status_fragment_error_tog(status_fragment_error_tog),
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.status_pause_frame_rx_tog(status_pause_frame_rx_tog),
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// Inputs
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.clk (clk),
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.res_n (res_n),
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.xgmii_rxd (xgmii_rxd),
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.xgmii_rxc (xgmii_rxc));
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rx_control rx_ctrl(
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// Outputs
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.rx_data (rx_data),
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.rx_data_valid (rx_data_valid),
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.rx_good_frame (rx_good_frame),
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.rx_bad_frame (rx_bad_frame),
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//.status_rxdfifo_udflow_tog(status_rxdfifo_udflow_tog),
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// Inputs
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.clk (clk),
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.res_n (res_n),
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.rx_inc_data (xgmii_data_in),
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.rx_inc_status (xgmii_data_status));
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tx_dequeue tx_dq0(
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// Outputs
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.xgmii_txd (xgmii_txd),
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.xgmii_txc (xgmii_txc),
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// Inputs
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.clk (clk),
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.res_n (res_n),
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.txdfifo_rdata (txdfifo_wdata),
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.txdfifo_rstatus (txdfifo_wstatus));
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tx_control tx_ctrl(
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// Outputs
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.txdfifo_wdata (txdfifo_wdata),
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.txdfifo_wstatus (txdfifo_wstatus),
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.tx_ack (tx_ack),
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.clk (clk),
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.res_n (res_n),
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.tx_start (tx_start),
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.tx_data (tx_data),
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.tx_data_valid (tx_data_valid));
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endmodule
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`default_nettype wire
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