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cleberCAG |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// This file is part of the "10GE LL MAC" project ////
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//// http://www.opencores.org/cores/xge_ll_mac/ ////
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//// ////
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//// This project is derived from the "10GE MAC" project of ////
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//// A. Tanguay (antanguay@opencores.org) by Andreas Peters ////
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//// for his Diploma Thesis at the University of Heidelberg. ////
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//// The Thesis was supervised by Christian Leber ////
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//// ////
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//// Author(s): ////
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//// - Andreas Peters ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008-2012 AUTHORS. All rights reserved. ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`include "oc_mac.h"
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//`include "technology.h"
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`default_nettype none
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module rx_control(
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// Inputs
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input wire clk,
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input wire res_n,
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input wire [63:0] rx_inc_data,
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input wire [7:0] rx_inc_status,
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// Outputs
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output reg [63:0] rx_data,
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output reg [7:0] rx_data_valid,
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output reg rx_good_frame,
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output reg rx_bad_frame);
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reg error;
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`ifdef ASYNC_RES
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always @(posedge clk or negedge res_n) `else
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always @(posedge clk) `endif
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begin
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if (res_n == 1'b0) begin
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rx_data <= 64'b0;
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rx_data_valid <= 8'b0;
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rx_good_frame <= 1'b0;
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rx_bad_frame <= 1'b0;
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error <= 1'b0;
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end
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else begin
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rx_data <= rx_inc_data;
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case ({rx_inc_status[`RXSTATUS_SOP], rx_inc_status[`RXSTATUS_EOP], rx_inc_status[`RXSTATUS_VALID], rx_inc_status[`RXSTATUS_ERR]})
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4'b1010: begin // normal start
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rx_data_valid <= 8'hff;
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error <= 1'b0;
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rx_bad_frame <= 1'b0;
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rx_good_frame <= 1'b0;
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end
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4'b0110: begin // normal end
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if (error) begin
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rx_bad_frame <= 1'b1;
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rx_good_frame <= 1'b0;
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end
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else begin
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rx_bad_frame <= 1'b0;
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rx_good_frame <= 1'b1;
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end
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case(rx_inc_status[2:0])
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3'b000: rx_data_valid <= 8'b11111111;
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3'b001: rx_data_valid <= 8'b00000001;
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3'b010: rx_data_valid <= 8'b00000011;
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3'b011: rx_data_valid <= 8'b00000111;
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3'b100: rx_data_valid <= 8'b00001111;
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3'b101: rx_data_valid <= 8'b00011111;
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3'b110: rx_data_valid <= 8'b00111111;
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default: rx_data_valid <= 8'b01111111;
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endcase
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end
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4'b0111: begin // end of frame bad
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rx_bad_frame <= 1'b1;
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rx_good_frame <= 1'b0;
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case(rx_inc_status[2:0])
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3'b000: rx_data_valid <= 8'b11111111;
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3'b001: rx_data_valid <= 8'b00000001;
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3'b010: rx_data_valid <= 8'b00000011;
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3'b011: rx_data_valid <= 8'b00000111;
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3'b100: rx_data_valid <= 8'b00001111;
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3'b101: rx_data_valid <= 8'b00011111;
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3'b110: rx_data_valid <= 8'b00111111;
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default: rx_data_valid <= 8'b01111111;
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endcase
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end
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4'b0010: begin // ongoing transmission
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rx_data_valid <= 8'hff;
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rx_bad_frame <= 1'b0;
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rx_good_frame <= 1'b0;
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end
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4'b0011: begin
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rx_data_valid <= 8'hff;
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error <= 1'b1;
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rx_bad_frame <= 1'b0;
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rx_good_frame <= 1'b0;
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end
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default: begin
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rx_data_valid <= 8'h00;
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error <= 1'b1;
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rx_bad_frame <= 1'b0;
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rx_good_frame <= 1'b0;
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end
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endcase
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end
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end
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endmodule
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`default_nettype wire
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