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cleberCAG |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// This file is part of the "10GE LL MAC" project ////
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//// http://www.opencores.org/cores/xge_ll_mac/ ////
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//// ////
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//// This project is derived from the "10GE MAC" project of ////
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//// A. Tanguay (antanguay@opencores.org) by Andreas Peters ////
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//// for his Diploma Thesis at the University of Heidelberg. ////
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//// The Thesis was supervised by Christian Leber ////
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//// ////
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//// Author(s): ////
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//// - Andreas Peters ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008-2012 AUTHORS. All rights reserved. ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`include "oc_mac.h"
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`include "oc_mac_crc_func.h"
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module rx_enqueue(
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input wire clk,
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input wire res_n,
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input wire [63:0] xgmii_rxd,
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input wire [7:0] xgmii_rxc,
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output reg [63:0] xgmii_data_in,
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output reg [7:0] xgmii_data_status,
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output reg [1:0] local_fault_msg_det,
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output reg [1:0] remote_fault_msg_det,
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output reg status_fragment_error_tog,
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output reg status_pause_frame_rx_tog);
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| 63 |
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reg [63:32] xgmii_rxd_d1;
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reg [7:4] xgmii_rxc_d1;
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reg [63:0] xgxs_rxd_barrel;
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reg [7:0] xgxs_rxc_barrel;
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reg [63:0] xgxs_rxd_barrel_d1;
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reg [7:0] xgxs_rxc_barrel_d1;
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reg [63:0] rx_inc_data;
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reg [7:0] rx_inc_status;
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reg barrel_shift;
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reg [31:0] crc32_d64;
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`ifdef SIMULATION
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reg crc_good;
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`endif
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reg crc_clear;
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reg [31:0] crc_rx;
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reg [31:0] next_crc_rx;
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reg [2:0] curr_state;
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reg [2:0] next_state;
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reg [13:0] curr_byte_cnt;
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reg [13:0] next_byte_cnt;
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reg fragment_error;
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reg [7:0] addmask;
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reg [7:0] datamask;
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reg pause_frame;
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reg next_pause_frame;
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parameter [2:0]
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SM_IDLE = 3'd0,
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SM_RX = 3'd1;
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`ifdef ASYNC_RES
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always @(posedge clk or negedge res_n) `else
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always @(posedge clk) `endif
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begin
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if (res_n == 1'b0) begin
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xgmii_data_in <= 64'b0;
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xgmii_data_status <= 8'b0;
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xgmii_rxd_d1 <= 32'b0;
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xgmii_rxc_d1 <= 4'b0;
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xgxs_rxd_barrel <= 64'b0;
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xgxs_rxc_barrel <= 8'b0;
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xgxs_rxd_barrel_d1 <= 64'b0;
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xgxs_rxc_barrel_d1 <= 8'b0;
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barrel_shift <= 1'b0;
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local_fault_msg_det <= 2'b0;
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remote_fault_msg_det <= 2'b0;
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crc32_d64 <= 32'b0;
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crc_rx <= 32'b0;
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status_fragment_error_tog <= 1'b0;
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status_pause_frame_rx_tog <= 1'b0;
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//sm
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curr_state <= SM_IDLE;
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curr_byte_cnt <= 14'b0;
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pause_frame <= 1'b0;
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end
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else begin
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//sm
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xgmii_data_in <= rx_inc_data;
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xgmii_data_status <= rx_inc_status;
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curr_state <= next_state;
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curr_byte_cnt <= next_byte_cnt;
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pause_frame <= next_pause_frame;
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//---
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// Link status RC layer
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// Look for local/remote messages on lower 4 lanes and upper
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// 4 lanes. This is a 64-bit interface but look at each 32-bit
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// independantly.
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local_fault_msg_det[1] <= (xgmii_rxd[63:32] ==
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{`LOCAL_FAULT, 8'h0, 8'h0, `SEQUENCE} &&
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xgmii_rxc[7:4] == 4'b0001);
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local_fault_msg_det[0] <= (xgmii_rxd[31:0] ==
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{`LOCAL_FAULT, 8'h0, 8'h0, `SEQUENCE} &&
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xgmii_rxc[3:0] == 4'b0001);
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remote_fault_msg_det[1] <= (xgmii_rxd[63:32] ==
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{`REMOTE_FAULT, 8'h0, 8'h0, `SEQUENCE} &&
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xgmii_rxc[7:4] == 4'b0001);
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remote_fault_msg_det[0] <= (xgmii_rxd[31:0] ==
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{`REMOTE_FAULT, 8'h0, 8'h0, `SEQUENCE} &&
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xgmii_rxc[3:0] == 4'b0001);
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//---
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// Rotating barrel. This function allow us to always align the start of
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// a frame with LANE0. If frame starts in LANE4, it will be shifted 4 bytes
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// to LANE0, thus reducing the amount of logic needed at the next stage.
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xgmii_rxd_d1[63:32] <= xgmii_rxd[63:32];
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xgmii_rxc_d1[7:4] <= xgmii_rxc[7:4];
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if (xgmii_rxd[`LANE0] == `START && xgmii_rxc[0]) begin
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xgxs_rxd_barrel <= xgmii_rxd;
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xgxs_rxc_barrel <= xgmii_rxc;
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barrel_shift <= 1'b0;
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end
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else if (xgmii_rxd[`LANE4] == `START && xgmii_rxc[4]) begin
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xgxs_rxd_barrel <= {xgmii_rxd[31:0], xgmii_rxd_d1[63:32]};
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xgxs_rxc_barrel <= {xgmii_rxc[3:0], xgmii_rxc_d1[7:4]};
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barrel_shift <= 1'b1;
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end
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else if (barrel_shift) begin
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xgxs_rxd_barrel <= {xgmii_rxd[31:0], xgmii_rxd_d1[63:32]};
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xgxs_rxc_barrel <= {xgmii_rxc[3:0], xgmii_rxc_d1[7:4]};
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end
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else begin
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xgxs_rxd_barrel <= xgmii_rxd;
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xgxs_rxc_barrel <= xgmii_rxc;
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end
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xgxs_rxd_barrel_d1 <= xgxs_rxd_barrel;
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xgxs_rxc_barrel_d1 <= xgxs_rxc_barrel;
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crc_rx <= next_crc_rx;
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if (crc_clear) begin
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// CRC is cleared at the beginning of the frame, calculate
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// 64-bit at a time otherwise
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crc32_d64 <= 32'hffffffff;
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end
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else begin
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crc32_d64 <= next_crc32_data64_be(reverse_64b(xgxs_rxd_barrel_d1), crc32_d64, 3'b0);
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| 249 |
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end
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//---
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// Error detection
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| 254 |
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| 255 |
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if (fragment_error) begin
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status_fragment_error_tog <= ~status_fragment_error_tog;
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end
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| 259 |
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| 260 |
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//---
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// Frame receive indication
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| 263 |
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// if (good_pause_frame) begin
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// status_pause_frame_rx_tog <= ~status_pause_frame_rx_tog;
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// end
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| 266 |
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| 267 |
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end
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| 268 |
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| 269 |
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end
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| 271 |
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| 272 |
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| 273 |
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always @(/*AS*/crc_rx or curr_byte_cnt or curr_state
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| 274 |
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or pause_frame or xgxs_rxc_barrel or xgxs_rxc_barrel_d1
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| 275 |
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or xgxs_rxd_barrel or xgxs_rxd_barrel_d1)
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| 276 |
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begin
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| 277 |
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| 278 |
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next_state = curr_state;
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| 279 |
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| 280 |
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rx_inc_data = xgxs_rxd_barrel_d1;
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| 281 |
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rx_inc_status = `RXSTATUS_NONE;
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| 282 |
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| 283 |
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| 284 |
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addmask[0] = !(xgxs_rxd_barrel_d1[`LANE0] == `TERMINATE && xgxs_rxc_barrel_d1[0]);
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| 285 |
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addmask[1] = !(xgxs_rxd_barrel_d1[`LANE1] == `TERMINATE && xgxs_rxc_barrel_d1[1]);
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| 286 |
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addmask[2] = !(xgxs_rxd_barrel_d1[`LANE2] == `TERMINATE && xgxs_rxc_barrel_d1[2]);
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| 287 |
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addmask[3] = !(xgxs_rxd_barrel_d1[`LANE3] == `TERMINATE && xgxs_rxc_barrel_d1[3]);
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| 288 |
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addmask[4] = !(xgxs_rxd_barrel_d1[`LANE4] == `TERMINATE && xgxs_rxc_barrel_d1[4]);
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| 289 |
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addmask[5] = !(xgxs_rxd_barrel_d1[`LANE5] == `TERMINATE && xgxs_rxc_barrel_d1[5]);
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| 290 |
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addmask[6] = !(xgxs_rxd_barrel_d1[`LANE6] == `TERMINATE && xgxs_rxc_barrel_d1[6]);
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| 291 |
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addmask[7] = !(xgxs_rxd_barrel_d1[`LANE7] == `TERMINATE && xgxs_rxc_barrel_d1[7]);
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| 292 |
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| 293 |
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datamask[0] = addmask[0];
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| 294 |
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datamask[1] = &addmask[1:0];
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| 295 |
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datamask[2] = &addmask[2:0];
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| 296 |
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datamask[3] = &addmask[3:0];
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| 297 |
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datamask[4] = &addmask[4:0];
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| 298 |
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datamask[5] = &addmask[5:0];
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| 299 |
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datamask[6] = &addmask[6:0];
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| 300 |
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datamask[7] = &addmask[7:0];
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| 301 |
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| 302 |
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| 303 |
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next_crc_rx = crc_rx;
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| 304 |
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crc_clear = 1'b0;
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| 305 |
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`ifdef SIMULATION
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| 306 |
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crc_good = 1'b0;
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| 307 |
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`endif
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| 308 |
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| 309 |
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| 310 |
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next_byte_cnt = curr_byte_cnt;
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| 311 |
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| 312 |
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fragment_error = 1'b0;
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| 313 |
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| 314 |
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next_pause_frame = pause_frame;
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| 315 |
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| 316 |
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case (curr_state)
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| 317 |
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| 318 |
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SM_IDLE: begin
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| 319 |
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next_byte_cnt = 14'b0;
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| 320 |
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crc_clear = 1'b1;
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| 321 |
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next_pause_frame = 1'b0;
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| 322 |
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| 323 |
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| 324 |
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// Detect the start of a frame
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| 325 |
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| 326 |
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if (xgxs_rxd_barrel_d1[`LANE0] == `START && xgxs_rxc_barrel_d1[0] &&
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| 327 |
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xgxs_rxd_barrel_d1[`LANE1] == `PREAMBLE && !xgxs_rxc_barrel_d1[1] &&
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| 328 |
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xgxs_rxd_barrel_d1[`LANE2] == `PREAMBLE && !xgxs_rxc_barrel_d1[2] &&
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| 329 |
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xgxs_rxd_barrel_d1[`LANE3] == `PREAMBLE && !xgxs_rxc_barrel_d1[3] &&
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| 330 |
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xgxs_rxd_barrel_d1[`LANE4] == `PREAMBLE && !xgxs_rxc_barrel_d1[4] &&
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| 331 |
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xgxs_rxd_barrel_d1[`LANE5] == `PREAMBLE && !xgxs_rxc_barrel_d1[5] &&
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| 332 |
|
|
xgxs_rxd_barrel_d1[`LANE6] == `PREAMBLE && !xgxs_rxc_barrel_d1[6] &&
|
| 333 |
|
|
xgxs_rxd_barrel_d1[`LANE7] == `SFD && !xgxs_rxc_barrel_d1[7])
|
| 334 |
|
|
begin
|
| 335 |
|
|
next_state = SM_RX;
|
| 336 |
|
|
end
|
| 337 |
|
|
|
| 338 |
|
|
end
|
| 339 |
|
|
|
| 340 |
|
|
SM_RX: begin
|
| 341 |
|
|
|
| 342 |
|
|
rx_inc_status[`RXSTATUS_VALID] = 1'b1;
|
| 343 |
|
|
|
| 344 |
|
|
if (xgxs_rxd_barrel_d1[`LANE0] == `START && xgxs_rxc_barrel_d1[0] &&
|
| 345 |
|
|
xgxs_rxd_barrel_d1[`LANE7] == `SFD && !xgxs_rxc_barrel_d1[7]) begin
|
| 346 |
|
|
|
| 347 |
|
|
// Fragment received, if we are still at SOP stage don't store
|
| 348 |
|
|
// the frame. If not, write a fake EOP and flag frame as bad.
|
| 349 |
|
|
|
| 350 |
|
|
next_byte_cnt = 14'b0;
|
| 351 |
|
|
crc_clear = 1'b1;
|
| 352 |
|
|
|
| 353 |
|
|
fragment_error = 1'b1;
|
| 354 |
|
|
rx_inc_status[`RXSTATUS_ERR] = 1'b1;
|
| 355 |
|
|
|
| 356 |
|
|
if (curr_byte_cnt == 14'b0) begin
|
| 357 |
|
|
//rxhfifo_wen = 1'b0;
|
| 358 |
|
|
end
|
| 359 |
|
|
else begin
|
| 360 |
|
|
rx_inc_status[`RXSTATUS_EOP] = 1'b1;
|
| 361 |
|
|
end
|
| 362 |
|
|
|
| 363 |
|
|
end
|
| 364 |
|
|
else if (curr_byte_cnt +datamask[0] + datamask[1] + datamask[2] + datamask[3] +
|
| 365 |
|
|
datamask[4] + datamask[5] + datamask[6] + datamask[7] > 14'd1518) begin //6 da + 6 sa +2 typelength, +1500 payload +4 crc
|
| 366 |
|
|
|
| 367 |
|
|
// Frame too long, TERMMINATE must have been corrupted.
|
| 368 |
|
|
// Abort transfer, write a fake EOP, report as fragment.
|
| 369 |
|
|
|
| 370 |
|
|
fragment_error = 1'b1;
|
| 371 |
|
|
rx_inc_status[`RXSTATUS_ERR] = 1'b1;
|
| 372 |
|
|
|
| 373 |
|
|
rx_inc_status[`RXSTATUS_EOP] = 1'b1;
|
| 374 |
|
|
next_state = SM_IDLE;
|
| 375 |
|
|
|
| 376 |
|
|
end
|
| 377 |
|
|
else begin
|
| 378 |
|
|
|
| 379 |
|
|
// Pause frame receive, these frame will be filtered
|
| 380 |
|
|
//- TODO
|
| 381 |
|
|
if (curr_byte_cnt == 14'd0 && xgxs_rxd_barrel_d1[47:0] == `PAUSE_FRAME) begin
|
| 382 |
|
|
|
| 383 |
|
|
//rxhfifo_wen = 1'b0;
|
| 384 |
|
|
next_pause_frame = 1'b1;
|
| 385 |
|
|
end
|
| 386 |
|
|
|
| 387 |
|
|
|
| 388 |
|
|
|
| 389 |
|
|
// Write SOP to status bits during first byte
|
| 390 |
|
|
|
| 391 |
|
|
if (curr_byte_cnt == 14'b0) begin
|
| 392 |
|
|
rx_inc_status[`RXSTATUS_SOP] = 1'b1;
|
| 393 |
|
|
end
|
| 394 |
|
|
|
| 395 |
|
|
next_byte_cnt = curr_byte_cnt +
|
| 396 |
|
|
addmask[0] + addmask[1] + addmask[2] + addmask[3] +
|
| 397 |
|
|
addmask[4] + addmask[5] + addmask[6] + addmask[7];
|
| 398 |
|
|
|
| 399 |
|
|
|
| 400 |
|
|
|
| 401 |
|
|
|
| 402 |
|
|
|
| 403 |
|
|
|
| 404 |
|
|
// Look one cycle ahead for TERMINATE in lanes 0 to 4
|
| 405 |
|
|
if (curr_byte_cnt + datamask[0] + datamask[1] + datamask[2] + datamask[3] +
|
| 406 |
|
|
datamask[4] + datamask[5] + datamask[6] + datamask[7] < 14'd64 && |(xgxs_rxc_barrel_d1 & datamask) ) begin // ethernet min. 64 byte check
|
| 407 |
|
|
|
| 408 |
|
|
next_state = SM_IDLE;
|
| 409 |
|
|
rx_inc_status[`RXSTATUS_ERR] = 1'b1;
|
| 410 |
|
|
rx_inc_status[`RXSTATUS_EOP] = 1'b1;
|
| 411 |
|
|
|
| 412 |
|
|
|
| 413 |
|
|
|
| 414 |
|
|
end
|
| 415 |
|
|
else if (xgxs_rxd_barrel[`LANE4] == `TERMINATE && xgxs_rxc_barrel[4]) begin
|
| 416 |
|
|
|
| 417 |
|
|
rx_inc_status[`RXSTATUS_EOP] = 1'b1;
|
| 418 |
|
|
rx_inc_status[2:0] = 3'd0;
|
| 419 |
|
|
|
| 420 |
|
|
if ( xgxs_rxd_barrel[31:0] != ~reverse_32b(next_crc32_data64_be(reverse_64b(xgxs_rxd_barrel_d1), crc32_d64, 3'b000))) begin
|
| 421 |
|
|
rx_inc_status[`RXSTATUS_ERR] = 1'b1;
|
| 422 |
|
|
`ifdef SIMULATION
|
| 423 |
|
|
crc_good = 1'b0;
|
| 424 |
|
|
`endif
|
| 425 |
|
|
end
|
| 426 |
|
|
`ifdef SIMULATION
|
| 427 |
|
|
else begin
|
| 428 |
|
|
crc_good = 1'b1;
|
| 429 |
|
|
end
|
| 430 |
|
|
`endif
|
| 431 |
|
|
next_state = SM_IDLE;
|
| 432 |
|
|
|
| 433 |
|
|
end
|
| 434 |
|
|
|
| 435 |
|
|
else if (xgxs_rxd_barrel[`LANE3] == `TERMINATE && xgxs_rxc_barrel[3]) begin
|
| 436 |
|
|
|
| 437 |
|
|
rx_inc_status[`RXSTATUS_EOP] = 1'b1;
|
| 438 |
|
|
rx_inc_status[2:0] = 3'd7;
|
| 439 |
|
|
|
| 440 |
|
|
if ( {xgxs_rxd_barrel[23:0], xgxs_rxd_barrel_d1[63:56]} != ~reverse_32b(next_crc32_data64_be(reverse_64b(xgxs_rxd_barrel_d1), crc32_d64, 3'b111))) begin
|
| 441 |
|
|
rx_inc_status[`RXSTATUS_ERR] = 1'b1;
|
| 442 |
|
|
`ifdef SIMULATION
|
| 443 |
|
|
crc_good = 1'b0;
|
| 444 |
|
|
`endif
|
| 445 |
|
|
end
|
| 446 |
|
|
`ifdef SIMULATION
|
| 447 |
|
|
else begin
|
| 448 |
|
|
crc_good = 1'b1;
|
| 449 |
|
|
end
|
| 450 |
|
|
`endif
|
| 451 |
|
|
next_state = SM_IDLE;
|
| 452 |
|
|
|
| 453 |
|
|
end
|
| 454 |
|
|
|
| 455 |
|
|
else if (xgxs_rxd_barrel[`LANE2] == `TERMINATE && xgxs_rxc_barrel[2]) begin
|
| 456 |
|
|
|
| 457 |
|
|
rx_inc_status[`RXSTATUS_EOP] = 1'b1;
|
| 458 |
|
|
rx_inc_status[2:0] = 3'd6;
|
| 459 |
|
|
|
| 460 |
|
|
if ( {xgxs_rxd_barrel[15:0], xgxs_rxd_barrel_d1[63:48]} != ~reverse_32b(next_crc32_data64_be(reverse_64b(xgxs_rxd_barrel_d1), crc32_d64, 3'b110))) begin
|
| 461 |
|
|
rx_inc_status[`RXSTATUS_ERR] = 1'b1;
|
| 462 |
|
|
`ifdef SIMULATION
|
| 463 |
|
|
crc_good = 1'b0;
|
| 464 |
|
|
`endif
|
| 465 |
|
|
end
|
| 466 |
|
|
`ifdef SIMULATION
|
| 467 |
|
|
else begin
|
| 468 |
|
|
crc_good = 1'b1;
|
| 469 |
|
|
end
|
| 470 |
|
|
`endif
|
| 471 |
|
|
next_state = SM_IDLE;
|
| 472 |
|
|
|
| 473 |
|
|
end
|
| 474 |
|
|
|
| 475 |
|
|
else if (xgxs_rxd_barrel[`LANE1] == `TERMINATE && xgxs_rxc_barrel[1]) begin
|
| 476 |
|
|
|
| 477 |
|
|
rx_inc_status[`RXSTATUS_EOP] = 1'b1;
|
| 478 |
|
|
rx_inc_status[2:0] = 3'd5;
|
| 479 |
|
|
|
| 480 |
|
|
if ( {xgxs_rxd_barrel[7:0], xgxs_rxd_barrel_d1[63:40]} != ~reverse_32b(next_crc32_data64_be(reverse_64b(xgxs_rxd_barrel_d1), crc32_d64, 3'b101))) begin
|
| 481 |
|
|
rx_inc_status[`RXSTATUS_ERR] = 1'b1;
|
| 482 |
|
|
`ifdef SIMULATION
|
| 483 |
|
|
crc_good = 1'b0;
|
| 484 |
|
|
`endif
|
| 485 |
|
|
end
|
| 486 |
|
|
`ifdef SIMULATION
|
| 487 |
|
|
else begin
|
| 488 |
|
|
crc_good = 1'b1;
|
| 489 |
|
|
end
|
| 490 |
|
|
`endif
|
| 491 |
|
|
next_state = SM_IDLE;
|
| 492 |
|
|
|
| 493 |
|
|
end
|
| 494 |
|
|
|
| 495 |
|
|
else if (xgxs_rxd_barrel[`LANE0] == `TERMINATE && xgxs_rxc_barrel[0]) begin
|
| 496 |
|
|
|
| 497 |
|
|
rx_inc_status[`RXSTATUS_EOP] = 1'b1;
|
| 498 |
|
|
rx_inc_status[2:0] = 3'd4;
|
| 499 |
|
|
|
| 500 |
|
|
if ( xgxs_rxd_barrel_d1[63:32] != ~reverse_32b(next_crc32_data64_be(reverse_64b(xgxs_rxd_barrel_d1), crc32_d64, 3'b100))) begin
|
| 501 |
|
|
rx_inc_status[`RXSTATUS_ERR] = 1'b1;
|
| 502 |
|
|
`ifdef SIMULATION
|
| 503 |
|
|
crc_good = 1'b0;
|
| 504 |
|
|
`endif
|
| 505 |
|
|
end
|
| 506 |
|
|
`ifdef SIMULATION
|
| 507 |
|
|
else begin
|
| 508 |
|
|
crc_good = 1'b1;
|
| 509 |
|
|
end
|
| 510 |
|
|
`endif
|
| 511 |
|
|
next_state = SM_IDLE;
|
| 512 |
|
|
|
| 513 |
|
|
end
|
| 514 |
|
|
|
| 515 |
|
|
// Look at current cycle for TERMINATE in lanes 5 to 7
|
| 516 |
|
|
|
| 517 |
|
|
else if (xgxs_rxd_barrel_d1[`LANE7] == `TERMINATE &&
|
| 518 |
|
|
xgxs_rxc_barrel_d1[7]) begin
|
| 519 |
|
|
|
| 520 |
|
|
rx_inc_status[`RXSTATUS_EOP] = 1'b1;
|
| 521 |
|
|
rx_inc_status[2:0] = 3'd3;
|
| 522 |
|
|
|
| 523 |
|
|
if ( xgxs_rxd_barrel_d1[55:24] != ~reverse_32b(next_crc32_data64_be(reverse_64b(xgxs_rxd_barrel_d1), crc32_d64, 3'b011))) begin
|
| 524 |
|
|
rx_inc_status[`RXSTATUS_ERR] = 1'b1;
|
| 525 |
|
|
`ifdef SIMULATION
|
| 526 |
|
|
crc_good = 1'b0;
|
| 527 |
|
|
`endif
|
| 528 |
|
|
end
|
| 529 |
|
|
`ifdef SIMULATION
|
| 530 |
|
|
else begin
|
| 531 |
|
|
crc_good = 1'b1;
|
| 532 |
|
|
end
|
| 533 |
|
|
`endif
|
| 534 |
|
|
next_state = SM_IDLE;
|
| 535 |
|
|
|
| 536 |
|
|
end
|
| 537 |
|
|
|
| 538 |
|
|
else if (xgxs_rxd_barrel_d1[`LANE6] == `TERMINATE &&
|
| 539 |
|
|
xgxs_rxc_barrel_d1[6]) begin
|
| 540 |
|
|
|
| 541 |
|
|
rx_inc_status[`RXSTATUS_EOP] = 1'b1;
|
| 542 |
|
|
rx_inc_status[2:0] = 3'd2;
|
| 543 |
|
|
|
| 544 |
|
|
if ( xgxs_rxd_barrel_d1[47:16] != ~reverse_32b(next_crc32_data64_be(reverse_64b(xgxs_rxd_barrel_d1), crc32_d64, 3'b010))) begin
|
| 545 |
|
|
rx_inc_status[`RXSTATUS_ERR] = 1'b1;
|
| 546 |
|
|
`ifdef SIMULATION
|
| 547 |
|
|
crc_good = 1'b0;
|
| 548 |
|
|
`endif
|
| 549 |
|
|
end
|
| 550 |
|
|
`ifdef SIMULATION
|
| 551 |
|
|
else begin
|
| 552 |
|
|
crc_good = 1'b1;
|
| 553 |
|
|
end
|
| 554 |
|
|
`endif
|
| 555 |
|
|
next_state = SM_IDLE;
|
| 556 |
|
|
|
| 557 |
|
|
end
|
| 558 |
|
|
|
| 559 |
|
|
else if (xgxs_rxd_barrel_d1[`LANE5] == `TERMINATE &&
|
| 560 |
|
|
xgxs_rxc_barrel_d1[5]) begin
|
| 561 |
|
|
|
| 562 |
|
|
rx_inc_status[`RXSTATUS_EOP] = 1'b1;
|
| 563 |
|
|
rx_inc_status[2:0] = 3'd1;
|
| 564 |
|
|
if ( xgxs_rxd_barrel_d1[39:8] != ~reverse_32b(next_crc32_data64_be(reverse_64b(xgxs_rxd_barrel_d1), crc32_d64, 3'b001))) begin
|
| 565 |
|
|
rx_inc_status[`RXSTATUS_ERR] = 1'b1;
|
| 566 |
|
|
`ifdef SIMULATION
|
| 567 |
|
|
crc_good = 1'b0;
|
| 568 |
|
|
`endif
|
| 569 |
|
|
end
|
| 570 |
|
|
`ifdef SIMULATION
|
| 571 |
|
|
else begin
|
| 572 |
|
|
crc_good = 1'b1;
|
| 573 |
|
|
end
|
| 574 |
|
|
`endif
|
| 575 |
|
|
|
| 576 |
|
|
next_state = SM_IDLE;
|
| 577 |
|
|
|
| 578 |
|
|
end
|
| 579 |
|
|
else if(|(xgxs_rxc_barrel_d1 & datamask)) begin // no terminate signal, but cmd != 0
|
| 580 |
|
|
`ifdef SIMULATION
|
| 581 |
|
|
crc_good = 1'b0;
|
| 582 |
|
|
`endif
|
| 583 |
|
|
rx_inc_status[`RXSTATUS_ERR] = 1'b1;
|
| 584 |
|
|
rx_inc_status[`RXSTATUS_EOP] = 1'b1;
|
| 585 |
|
|
next_state = SM_IDLE;
|
| 586 |
|
|
|
| 587 |
|
|
|
| 588 |
|
|
end
|
| 589 |
|
|
`ifdef SIMULATION
|
| 590 |
|
|
else begin
|
| 591 |
|
|
crc_good = 1'b0;
|
| 592 |
|
|
end
|
| 593 |
|
|
`endif
|
| 594 |
|
|
|
| 595 |
|
|
end
|
| 596 |
|
|
end
|
| 597 |
|
|
|
| 598 |
|
|
default: begin
|
| 599 |
|
|
next_state = SM_IDLE;
|
| 600 |
|
|
end
|
| 601 |
|
|
|
| 602 |
|
|
endcase
|
| 603 |
|
|
|
| 604 |
|
|
end
|
| 605 |
|
|
|
| 606 |
|
|
|
| 607 |
|
|
endmodule
|
| 608 |
|
|
|
