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[/] [xge_ll_mac/] [trunk/] [rtl/] [tx_control.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  This file is part of the "10GE LL MAC" project              ////
////  http://www.opencores.org/cores/xge_ll_mac/                  ////
////                                                              ////
////  This project is derived from the "10GE MAC" project of      ////
////  A. Tanguay (antanguay@opencores.org) by Andreas Peters      ////
////  for his Diploma Thesis at the University of Heidelberg.     ////
////  The Thesis was supervised by Christian Leber                ////
////                                                              ////
////  Author(s):                                                  ////
////      - Andreas Peters                                        ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2008-2012 AUTHORS. All rights reserved.        ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
//`include "technology.h"
`include "oc_mac.h"
 
`default_nettype none
 
module tx_control(
                // Inputs
                input wire              clk,
                input wire              res_n,
                input wire              tx_start,
                input wire [63:0]        tx_data,
                input wire [7:0] tx_data_valid,
                // Outputs
 
                output reg [63:0]        txdfifo_wdata,
                output reg [7:0] txdfifo_wstatus,
                output reg              tx_ack);
 
 
reg [3:0]        frame_cnt;
 
// Shift register for EOP
reg [63:0]       txdfifo_wdata_prev;
reg [7:0]        txdfifo_wstatus_prev;
reg [2:0]        current_state;
 
parameter [2:0]
                SM_IDLE = 3'd0,
                SM_START = 3'd1,
                SM_TX = 3'd2;
 
// Full status if data fifo is almost full.
// Current packet can complete transfer since data input rate
// matches output rate. But next packet must wait for more headroom.
// 
 
//SM!!
 
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) `else
always @(posedge clk) `endif
begin
        if (res_n == 1'b0) begin
                txdfifo_wdata <= 64'b0;
                txdfifo_wstatus <= 8'b0;
                frame_cnt <= 4'b0;
                current_state <= 3'b0;
                txdfifo_wdata_prev <= 64'b0;
                txdfifo_wstatus_prev <= 8'b0;
                tx_ack <= 1'b0;
 
 
        end
        else begin
 
                txdfifo_wdata <= txdfifo_wdata_prev;
                txdfifo_wdata_prev <= tx_data;
                case (current_state)
 
                SM_IDLE: begin
 
                        txdfifo_wstatus_prev <= 8'b0;
                        txdfifo_wstatus <= txdfifo_wstatus_prev;
                        if(tx_start == 1'b1) begin
                                current_state <= SM_START;
                        end
                        else begin
                                current_state <= SM_IDLE;
                                if (frame_cnt != 4'b0)
                                        frame_cnt <= frame_cnt - 4'b1;
                        end
 
                end
                SM_START: begin
 
                        if (frame_cnt == 4'd0) begin
                                tx_ack <= 1'b1;
                                current_state <= SM_TX;
                                txdfifo_wstatus <= txdfifo_wstatus_prev;
                                frame_cnt <= 4'd9;
                        end
                        else begin
                                tx_ack <= 1'b0;
                                current_state <= SM_START;
                                txdfifo_wstatus_prev <= 8'b0;
                                txdfifo_wstatus <= txdfifo_wstatus_prev;
                                frame_cnt <= frame_cnt - 4'b1;
                        end
                end
                SM_TX: begin
 
                        if(frame_cnt != 4'd0) begin
                                frame_cnt <= frame_cnt - 4'b1;
                        end
                        if(tx_ack == 1'b1) begin
                                txdfifo_wstatus_prev <= `TXSTATUS_START;
                                tx_ack <= 1'b0;
                                txdfifo_wstatus <= txdfifo_wstatus_prev;
                        end
                        else if (tx_data_valid == 8'hFF) begin
                                txdfifo_wstatus <= txdfifo_wstatus_prev;
                                txdfifo_wstatus_prev <= `TXSTATUS_NONE;
                                txdfifo_wstatus <= txdfifo_wstatus_prev;
                                current_state <= SM_TX;
                        end
                        else if (tx_data_valid == 8'b00) begin
                                txdfifo_wstatus <= `TXSTATUS_END;
                                txdfifo_wstatus_prev <= 8'b0;
                                current_state <= SM_IDLE;
                        end
                        else begin
                                case (tx_data_valid)
                                        8'b11111111:    txdfifo_wstatus_prev[2:0]        <= 3'h0; // all lanes with valid data(implementation error, not working)
                                        8'b01111111:    txdfifo_wstatus_prev[2:0]        <= 3'h7;
                                        8'b00111111:    txdfifo_wstatus_prev[2:0]        <= 3'h6;
                                        8'b00011111:    txdfifo_wstatus_prev[2:0]        <= 3'h5;
                                        8'b00001111:    txdfifo_wstatus_prev[2:0]        <= 3'h4;
                                        8'b00000111:    txdfifo_wstatus_prev[2:0]        <= 3'h3;
                                        8'b00000011:    txdfifo_wstatus_prev[2:0]        <= 3'h2;
                                        8'b00000001:    txdfifo_wstatus_prev[2:0]        <= 3'h1;
                                        8'b00000000:    txdfifo_wstatus_prev[2:0]        <= 3'h0; // not defined in OC
                                        default:        txdfifo_wstatus_prev[2:0]        <= 3'h0; // unsure.
                                endcase
 
                                txdfifo_wstatus_prev[`TXSTATUS_EOP] <= 1'b1;
                                txdfifo_wstatus_prev[`TXSTATUS_VALID] <= 1'b1;
                                txdfifo_wstatus_prev[`TXSTATUS_SOP] <= 1'b0;
                                txdfifo_wstatus_prev[5] <= 1'b0;
                                txdfifo_wstatus_prev[3] <= 1'b0;
 
                                txdfifo_wstatus <= txdfifo_wstatus_prev;
                                current_state <= SM_IDLE;
                        end
                end
 
                endcase//- SM 
 
        end
end
 
endmodule
`default_nettype wire

Line No.	Rev	Author	Line
1	2	cleberCAG	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// This file is part of the "10GE LL MAC" project ////`
4			`//// http://www.opencores.org/cores/xge_ll_mac/ ////`
5			`//// ////`
6			`//// This project is derived from the "10GE MAC" project of ////`
7			`//// A. Tanguay (antanguay@opencores.org) by Andreas Peters ////`
8			`//// for his Diploma Thesis at the University of Heidelberg. ////`
9			`//// The Thesis was supervised by Christian Leber ////`
10			`//// ////`
11			`//// Author(s): ////`
12			`//// - Andreas Peters ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2008-2012 AUTHORS. All rights reserved. ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40
41			//`include "technology.h"
42			`include "oc_mac.h"
43
44			`default_nettype none
45
46			`module tx_control(`
47			`// Inputs`
48			`input wire clk,`
49			`input wire res_n,`
50			`input wire tx_start,`
51			`input wire [63:0] tx_data,`
52			`input wire [7:0] tx_data_valid,`
53			`// Outputs`
54
55			`output reg [63:0] txdfifo_wdata,`
56			`output reg [7:0] txdfifo_wstatus,`
57			`output reg tx_ack);`
58
59
60			`reg [3:0] frame_cnt;`
61
62			`// Shift register for EOP`
63			`reg [63:0] txdfifo_wdata_prev;`
64			`reg [7:0] txdfifo_wstatus_prev;`
65			`reg [2:0] current_state;`
66
67			`parameter [2:0]`
68			`SM_IDLE = 3'd0,`
69			`SM_START = 3'd1,`
70			`SM_TX = 3'd2;`
71
72			`// Full status if data fifo is almost full.`
73			`// Current packet can complete transfer since data input rate`
74			`// matches output rate. But next packet must wait for more headroom.`
75			`//`
76
77			`//SM!!`
78
79			`ifdef ASYNC_RES
80			always @(posedge clk or negedge res_n) `else
81			always @(posedge clk) `endif
82			`begin`
83			`if (res_n == 1'b0) begin`
84			`txdfifo_wdata <= 64'b0;`
85			`txdfifo_wstatus <= 8'b0;`
86			`frame_cnt <= 4'b0;`
87			`current_state <= 3'b0;`
88			`txdfifo_wdata_prev <= 64'b0;`
89			`txdfifo_wstatus_prev <= 8'b0;`
90			`tx_ack <= 1'b0;`
91
92
93			`end`
94			`else begin`
95
96			`txdfifo_wdata <= txdfifo_wdata_prev;`
97			`txdfifo_wdata_prev <= tx_data;`
98			`case (current_state)`
99
100			`SM_IDLE: begin`
101
102			`txdfifo_wstatus_prev <= 8'b0;`
103			`txdfifo_wstatus <= txdfifo_wstatus_prev;`
104			`if(tx_start == 1'b1) begin`
105			`current_state <= SM_START;`
106			`end`
107			`else begin`
108			`current_state <= SM_IDLE;`
109			`if (frame_cnt != 4'b0)`
110			`frame_cnt <= frame_cnt - 4'b1;`
111			`end`
112
113			`end`
114			`SM_START: begin`
115
116			`if (frame_cnt == 4'd0) begin`
117			`tx_ack <= 1'b1;`
118			`current_state <= SM_TX;`
119			`txdfifo_wstatus <= txdfifo_wstatus_prev;`
120			`frame_cnt <= 4'd9;`
121			`end`
122			`else begin`
123			`tx_ack <= 1'b0;`
124			`current_state <= SM_START;`
125			`txdfifo_wstatus_prev <= 8'b0;`
126			`txdfifo_wstatus <= txdfifo_wstatus_prev;`
127			`frame_cnt <= frame_cnt - 4'b1;`
128			`end`
129			`end`
130			`SM_TX: begin`
131
132			`if(frame_cnt != 4'd0) begin`
133			`frame_cnt <= frame_cnt - 4'b1;`
134			`end`
135			`if(tx_ack == 1'b1) begin`
136			txdfifo_wstatus_prev <= `TXSTATUS_START;
137			`tx_ack <= 1'b0;`
138			`txdfifo_wstatus <= txdfifo_wstatus_prev;`
139			`end`
140			`else if (tx_data_valid == 8'hFF) begin`
141			`txdfifo_wstatus <= txdfifo_wstatus_prev;`
142			txdfifo_wstatus_prev <= `TXSTATUS_NONE;
143			`txdfifo_wstatus <= txdfifo_wstatus_prev;`
144			`current_state <= SM_TX;`
145			`end`
146			`else if (tx_data_valid == 8'b00) begin`
147			txdfifo_wstatus <= `TXSTATUS_END;
148			`txdfifo_wstatus_prev <= 8'b0;`
149			`current_state <= SM_IDLE;`
150			`end`
151			`else begin`
152			`case (tx_data_valid)`
153			`8'b11111111: txdfifo_wstatus_prev[2:0] <= 3'h0; // all lanes with valid data(implementation error, not working)`
154			`8'b01111111: txdfifo_wstatus_prev[2:0] <= 3'h7;`
155			`8'b00111111: txdfifo_wstatus_prev[2:0] <= 3'h6;`
156			`8'b00011111: txdfifo_wstatus_prev[2:0] <= 3'h5;`
157			`8'b00001111: txdfifo_wstatus_prev[2:0] <= 3'h4;`
158			`8'b00000111: txdfifo_wstatus_prev[2:0] <= 3'h3;`
159			`8'b00000011: txdfifo_wstatus_prev[2:0] <= 3'h2;`
160			`8'b00000001: txdfifo_wstatus_prev[2:0] <= 3'h1;`
161			`8'b00000000: txdfifo_wstatus_prev[2:0] <= 3'h0; // not defined in OC`
162			`default: txdfifo_wstatus_prev[2:0] <= 3'h0; // unsure.`
163			`endcase`
164
165			txdfifo_wstatus_prev[`TXSTATUS_EOP] <= 1'b1;
166			txdfifo_wstatus_prev[`TXSTATUS_VALID] <= 1'b1;
167			txdfifo_wstatus_prev[`TXSTATUS_SOP] <= 1'b0;
168			`txdfifo_wstatus_prev[5] <= 1'b0;`
169			`txdfifo_wstatus_prev[3] <= 1'b0;`
170
171			`txdfifo_wstatus <= txdfifo_wstatus_prev;`
172			`current_state <= SM_IDLE;`
173			`end`
174			`end`
175
176			`endcase//- SM`
177
178			`end`
179			`end`
180
181			`endmodule`
182			`default_nettype wire

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[/] [xge_ll_mac/] [trunk/] [rtl/] [tx_control.v] - Blame information for rev 2