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///////////////////////////////////////////////////////////////////////
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// File: CRC32_D8.v
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// Date: Fri Feb 8 19:26:59 2008
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//
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// Copyright (C) 1999-2003 Easics NV.
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// This source file may be used and distributed without restriction
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// provided that this copyright statement is not removed from the file
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// and that any derivative work contains the original copyright notice
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// and the associated disclaimer.
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//
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// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
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// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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//
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// Purpose: Verilog module containing a synthesizable CRC function
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// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
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// * data width: 8
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//
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// Info: tools@easics.be
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// http://www.easics.com
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///////////////////////////////////////////////////////////////////////
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//module CRC32_D8;
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// polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
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// data width: 8
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// convention: the first serial data bit is D[7]
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function [31:0] nextCRC32_D8;
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input [7:0] Data;
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input [31:0] CRC;
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reg [7:0] D;
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reg [31:0] C;
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reg [31:0] NewCRC;
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begin
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D = Data;
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C = CRC;
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NewCRC[0] = D[6] ^ D[0] ^ C[24] ^ C[30];
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NewCRC[1] = D[7] ^ D[6] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ C[30] ^
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C[31];
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NewCRC[2] = D[7] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^
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C[26] ^ C[30] ^ C[31];
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NewCRC[3] = D[7] ^ D[3] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^ C[27] ^
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C[31];
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NewCRC[4] = D[6] ^ D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^
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C[27] ^ C[28] ^ C[30];
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NewCRC[5] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[24] ^
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C[25] ^ C[27] ^ C[28] ^ C[29] ^ C[30] ^ C[31];
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NewCRC[6] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^
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C[28] ^ C[29] ^ C[30] ^ C[31];
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NewCRC[7] = D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^
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C[27] ^ C[29] ^ C[31];
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NewCRC[8] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[0] ^ C[24] ^ C[25] ^
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C[27] ^ C[28];
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NewCRC[9] = D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[1] ^ C[25] ^ C[26] ^
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C[28] ^ C[29];
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NewCRC[10] = D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[2] ^ C[24] ^ C[26] ^
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C[27] ^ C[29];
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NewCRC[11] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[3] ^ C[24] ^ C[25] ^
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C[27] ^ C[28];
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NewCRC[12] = D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[4] ^ C[24] ^
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C[25] ^ C[26] ^ C[28] ^ C[29] ^ C[30];
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NewCRC[13] = D[7] ^ D[6] ^ D[5] ^ D[3] ^ D[2] ^ D[1] ^ C[5] ^ C[25] ^
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C[26] ^ C[27] ^ C[29] ^ C[30] ^ C[31];
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NewCRC[14] = D[7] ^ D[6] ^ D[4] ^ D[3] ^ D[2] ^ C[6] ^ C[26] ^ C[27] ^
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C[28] ^ C[30] ^ C[31];
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NewCRC[15] = D[7] ^ D[5] ^ D[4] ^ D[3] ^ C[7] ^ C[27] ^ C[28] ^
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C[29] ^ C[31];
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NewCRC[16] = D[5] ^ D[4] ^ D[0] ^ C[8] ^ C[24] ^ C[28] ^ C[29];
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NewCRC[17] = D[6] ^ D[5] ^ D[1] ^ C[9] ^ C[25] ^ C[29] ^ C[30];
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NewCRC[18] = D[7] ^ D[6] ^ D[2] ^ C[10] ^ C[26] ^ C[30] ^ C[31];
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NewCRC[19] = D[7] ^ D[3] ^ C[11] ^ C[27] ^ C[31];
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NewCRC[20] = D[4] ^ C[12] ^ C[28];
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NewCRC[21] = D[5] ^ C[13] ^ C[29];
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NewCRC[22] = D[0] ^ C[14] ^ C[24];
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NewCRC[23] = D[6] ^ D[1] ^ D[0] ^ C[15] ^ C[24] ^ C[25] ^ C[30];
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NewCRC[24] = D[7] ^ D[2] ^ D[1] ^ C[16] ^ C[25] ^ C[26] ^ C[31];
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NewCRC[25] = D[3] ^ D[2] ^ C[17] ^ C[26] ^ C[27];
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NewCRC[26] = D[6] ^ D[4] ^ D[3] ^ D[0] ^ C[18] ^ C[24] ^ C[27] ^
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C[28] ^ C[30];
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NewCRC[27] = D[7] ^ D[5] ^ D[4] ^ D[1] ^ C[19] ^ C[25] ^ C[28] ^
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C[29] ^ C[31];
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NewCRC[28] = D[6] ^ D[5] ^ D[2] ^ C[20] ^ C[26] ^ C[29] ^ C[30];
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NewCRC[29] = D[7] ^ D[6] ^ D[3] ^ C[21] ^ C[27] ^ C[30] ^ C[31];
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NewCRC[30] = D[7] ^ D[4] ^ C[22] ^ C[28] ^ C[31];
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NewCRC[31] = D[5] ^ C[23] ^ C[29];
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nextCRC32_D8 = NewCRC;
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end
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endfunction
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//endmodule
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