OpenCores
URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [tags/] [initial/] [rtl/] [verilog/] [fault_sm.v] - Blame information for rev 7

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 antanguay 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  File name "fault_sm.v"                                      ////
4 
////                                                              ////
5 
////  This file is part of the "10GE MAC" project                 ////
6 
////  http://www.opencores.org/cores/xge_mac/                     ////
7 
////                                                              ////
8 
////  Author(s):                                                  ////
9 
////      - A. Tanguay (antanguay@opencores.org)                  ////
10 
////                                                              ////
11 
//////////////////////////////////////////////////////////////////////
12 
////                                                              ////
13 
//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
14 
////                                                              ////
15 
//// This source file may be used and distributed without         ////
16 
//// restriction provided that this copyright statement is not    ////
17 
//// removed from the file and that any derivative work contains  ////
18 
//// the original copyright notice and the associated disclaimer. ////
19 
////                                                              ////
20 
//// This source file is free software; you can redistribute it   ////
21 
//// and/or modify it under the terms of the GNU Lesser General   ////
22 
//// Public License as published by the Free Software Foundation; ////
23 
//// either version 2.1 of the License, or (at your option) any   ////
24 
//// later version.                                               ////
25 
////                                                              ////
26 
//// This source is distributed in the hope that it will be       ////
27 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
28 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
29 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
30 
//// details.                                                     ////
31 
////                                                              ////
32 
//// You should have received a copy of the GNU Lesser General    ////
33 
//// Public License along with this source; if not, download it   ////
34 
//// from http://www.opencores.org/lgpl.shtml                     ////
35 
////                                                              ////
36 
//////////////////////////////////////////////////////////////////////
37 
 
38 
 
39 
`include "defines.v"
40 
 
41 
module fault_sm(/*AUTOARG*/
42 
  // Outputs
43 
  status_local_fault_crx, status_remote_fault_crx,
44 
  // Inputs
45 
  clk_xgmii_rx, reset_xgmii_rx_n, local_fault_msg_det,
46 
  remote_fault_msg_det
47 
  );
48 
 
49 
input         clk_xgmii_rx;
50 
input         reset_xgmii_rx_n;
51 
 
52 
input  [1:0]  local_fault_msg_det;
53 
input  [1:0]  remote_fault_msg_det;
54 
 
55 
output        status_local_fault_crx;
56 
output        status_remote_fault_crx;
57 
 
58 
/*AUTOREG*/
59 
// Beginning of automatic regs (for this module's undeclared outputs)
60 
reg                     status_local_fault_crx;
61 
reg                     status_remote_fault_crx;
62 
// End of automatics
63 
 
64 
reg    [1:0]  curr_state;
65 
 
66 
reg    [7:0]  col_cnt;
67 
reg    [1:0]  fault_sequence;
68 
reg    [1:0]  last_seq_type;
69 
reg    [1:0]  link_fault;
70 
reg    [2:0]  seq_cnt;
71 
reg    [1:0]  seq_type;
72 
 
73 
reg    [1:0]  seq_add;
74 
 
75 
/*AUTOWIRE*/
76 
// Beginning of automatic wires (for undeclared instantiated-module outputs)
77 
// End of automatics
78 
 
79 
 
80 
parameter [1:0]
81 
             SM_INIT       = 2'd0,
82 
             SM_COUNT      = 2'd1,
83 
             SM_FAULT      = 2'd2,
84 
             SM_NEW_FAULT  = 2'd3;
85 
 
86 
 
87 
always @(/*AS*/local_fault_msg_det or remote_fault_msg_det) begin
88 
 
89 
    //---
90 
    // Fault indication. Indicate remote or local fault
91 
 
92 
    fault_sequence = local_fault_msg_det | remote_fault_msg_det;
93 
 
94 
 
95 
    //---
96 
    // Sequence type, local, remote, or ok
97 
 
98 
    if (|local_fault_msg_det) begin
99 
        seq_type = `LINK_FAULT_LOCAL;
100 
    end
101 
    else if (|remote_fault_msg_det) begin
102 
        seq_type = `LINK_FAULT_REMOTE;
103 
    end
104 
    else begin
105 
        seq_type = `LINK_FAULT_OK;
106 
    end
107 
 
108 
 
109 
    //---
110 
    // Adder for number of faults, if detected in lower 4 lanes and
111 
    // upper 4 lanes, add 2. That's because we process 64-bit at a time
112 
    // instead of typically 32-bit xgmii.
113 
 
114 
    if (|remote_fault_msg_det) begin
115 
        seq_add = remote_fault_msg_det[1] + remote_fault_msg_det[0];
116 
    end
117 
    else begin
118 
        seq_add = local_fault_msg_det[1] + local_fault_msg_det[0];
119 
    end
120 
 
121 
end
122 
 
123 
always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin
124 
 
125 
    if (reset_xgmii_rx_n == 1'b0) begin
126 
 
127 
 
128 
        status_local_fault_crx <= 1'b0;
129 
        status_remote_fault_crx <= 1'b0;
130 
 
131 
    end
132 
    else begin
133 
 
134 
        //---
135 
        // Status signal to generate local/remote fault interrupts
136 
 
137 
        status_local_fault_crx <= curr_state == SM_FAULT &&
138 
                                  link_fault == `LINK_FAULT_LOCAL;
139 
 
140 
        status_remote_fault_crx <= curr_state == SM_FAULT &&
141 
                                   link_fault == `LINK_FAULT_REMOTE;
142 
 
143 
    end
144 
 
145 
end
146 
 
147 
always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin
148 
 
149 
    if (reset_xgmii_rx_n == 1'b0) begin
150 
 
151 
        curr_state <= SM_INIT;
152 
 
153 
        col_cnt <= 8'b0;
154 
        last_seq_type <= `LINK_FAULT_OK;
155 
        link_fault <= `LINK_FAULT_OK;
156 
        seq_cnt <= 3'b0;
157 
 
158 
    end
159 
    else begin
160 
 
161 
        case (curr_state)
162 
 
163 
          SM_INIT:
164 
            begin
165 
 
166 
                last_seq_type <= seq_type;
167 
 
168 
                if (|fault_sequence) begin
169 
 
170 
                    // If a fault is detected, capture the type of
171 
                    // fault and start column counter. We need 4 fault
172 
                    // messages in 128 columns to accept the fault.
173 
 
174 
                    if (fault_sequence[0]) begin
175 
                        col_cnt <= 8'd2;
176 
                    end
177 
                    else begin
178 
                        col_cnt <= 8'd1;
179 
                    end
180 
                    seq_cnt <= {1'b0, seq_add};
181 
                    curr_state <= SM_COUNT;
182 
 
183 
                end
184 
                else begin
185 
 
186 
                    // If no faults, stay in INIT and clear counters
187 
 
188 
                    col_cnt <= 8'b0;
189 
                    seq_cnt <= 3'b0;
190 
 
191 
                end
192 
            end
193 
 
194 
          SM_COUNT:
195 
            begin
196 
 
197 
                col_cnt <= col_cnt + 8'd2;
198 
                seq_cnt <= seq_cnt + {1'b0, seq_add};
199 
 
200 
                if (!fault_sequence[0] && col_cnt >= 8'd127) begin
201 
 
202 
                    // No new fault in lower lanes and almost
203 
                    // reached the 128 columns count, abort fault.
204 
 
205 
                    curr_state <= SM_INIT;
206 
 
207 
                end
208 
                else if (col_cnt > 8'd127) begin
209 
 
210 
                    // Reached the 128 columns count, abort fault.
211 
 
212 
                    curr_state <= SM_INIT;
213 
 
214 
                end
215 
                else if (|fault_sequence) begin
216 
 
217 
                    // If fault type has changed, move to NEW_FAULT.
218 
                    // If not, after detecting 4 fault messages move to
219 
                    // FAULT state.
220 
 
221 
                    if (seq_type != last_seq_type) begin
222 
                        curr_state <= SM_NEW_FAULT;
223 
                    end
224 
                    else begin
225 
                        if ((seq_cnt + {1'b0, seq_add}) > 3'd3) begin
226 
                            col_cnt <= 8'b0;
227 
                            link_fault <= seq_type;
228 
                            curr_state <= SM_FAULT;
229 
                        end
230 
                    end
231 
 
232 
                end
233 
            end
234 
 
235 
          SM_FAULT:
236 
            begin
237 
 
238 
                col_cnt <= col_cnt + 8'd2;
239 
 
240 
                if (!fault_sequence[0] && col_cnt >= 8'd127) begin
241 
 
242 
                    // No new fault in lower lanes and almost
243 
                    // reached the 128 columns count, abort fault.
244 
 
245 
                    curr_state <= SM_INIT;
246 
 
247 
                end
248 
                else if (col_cnt > 8'd127) begin
249 
 
250 
                    // Reached the 128 columns count, abort fault.
251 
 
252 
                    curr_state <= SM_INIT;
253 
 
254 
                end
255 
                else if (|fault_sequence) begin
256 
 
257 
                    // Clear the column count each time we see a fault,
258 
                    // if fault changes, go no next state.
259 
 
260 
                    col_cnt <= 8'd0;
261 
 
262 
                    if (seq_type != last_seq_type) begin
263 
                        curr_state <= SM_NEW_FAULT;
264 
                    end
265 
                end
266 
 
267 
            end
268 
 
269 
          SM_NEW_FAULT:
270 
            begin
271 
 
272 
                // Capture new fault type. Start counters.
273 
 
274 
                col_cnt <= 8'b0;
275 
                last_seq_type <= seq_type;
276 
 
277 
                seq_cnt <= {1'b0, seq_add};
278 
                curr_state <= SM_COUNT;
279 
 
280 
            end
281 
 
282 
        endcase
283 
 
284 
    end
285 
 
286 
end
287 
 
288 
endmodule
289 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.