OpenCores
URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [tags/] [initial/] [rtl/] [verilog/] [generic_fifo.v] - Blame information for rev 12

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 antanguay
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  File name "generic_fifo.v"                                  ////
4
////                                                              ////
5
////  This file is part of the "10GE MAC" project                 ////
6
////  http://www.opencores.org/cores/xge_mac/                     ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - A. Tanguay (antanguay@opencores.org)                  ////
10
////                                                              ////
11
//////////////////////////////////////////////////////////////////////
12
////                                                              ////
13
//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
14
////                                                              ////
15
//// This source file may be used and distributed without         ////
16
//// restriction provided that this copyright statement is not    ////
17
//// removed from the file and that any derivative work contains  ////
18
//// the original copyright notice and the associated disclaimer. ////
19
////                                                              ////
20
//// This source file is free software; you can redistribute it   ////
21
//// and/or modify it under the terms of the GNU Lesser General   ////
22
//// Public License as published by the Free Software Foundation; ////
23
//// either version 2.1 of the License, or (at your option) any   ////
24
//// later version.                                               ////
25
////                                                              ////
26
//// This source is distributed in the hope that it will be       ////
27
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
28
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
29
//// PURPOSE.  See the GNU Lesser General Public License for more ////
30
//// details.                                                     ////
31
////                                                              ////
32
//// You should have received a copy of the GNU Lesser General    ////
33
//// Public License along with this source; if not, download it   ////
34
//// from http://www.opencores.org/lgpl.shtml                     ////
35
////                                                              ////
36
//////////////////////////////////////////////////////////////////////
37
 
38
 
39
module generic_fifo(
40
 
41
    wclk,
42
    wrst_n,
43
    wen,
44
    wdata,
45
    wfull,
46
    walmost_full,
47
 
48
    rclk,
49
    rrst_n,
50
    ren,
51
    rdata,
52
    rempty,
53
    ralmost_empty
54
);
55
 
56
//---
57
// Parameters
58
 
59
parameter DWIDTH = 32;
60
parameter AWIDTH = 3;
61
parameter RAM_DEPTH = (1 << AWIDTH);
62
parameter SYNC_WRITE = 1;
63
parameter SYNC_READ = 1;
64
parameter REGISTER_READ = 0;
65
parameter EARLY_READ = 0;
66
parameter CLOCK_CROSSING = 1;
67
parameter ALMOST_EMPTY_THRESH = 1;
68
parameter ALMOST_FULL_THRESH = RAM_DEPTH-2;
69
parameter MEM_TYPE = `MEM_AUTO_SMALL;
70
 
71
//---
72
// Ports
73
 
74
input          wclk;
75
input          wrst_n;
76
input          wen;
77
input  [DWIDTH-1:0] wdata;
78
output         wfull;
79
output         walmost_full;
80
 
81
input          rclk;
82
input          rrst_n;
83
input          ren;
84
output [DWIDTH-1:0] rdata;
85
output         rempty;
86
output         ralmost_empty;
87
 
88
// Wires
89
 
90
wire             mem_wen;
91
wire [AWIDTH:0]  mem_waddr;
92
 
93
wire             mem_ren;
94
wire [AWIDTH:0]  mem_raddr;
95
 
96
 
97
generic_fifo_ctrl #(.AWIDTH (AWIDTH),
98
                    .RAM_DEPTH (RAM_DEPTH),
99
                    .EARLY_READ (EARLY_READ),
100
                    .CLOCK_CROSSING (CLOCK_CROSSING),
101
                    .ALMOST_EMPTY_THRESH (ALMOST_EMPTY_THRESH),
102
                    .ALMOST_FULL_THRESH (ALMOST_FULL_THRESH)
103
                    )
104
  ctrl0(.wclk (wclk),
105
        .wrst_n (wrst_n),
106
        .wen (wen),
107
        .wfull (wfull),
108
        .walmost_full (walmost_full),
109
 
110
        .mem_wen (mem_wen),
111
        .mem_waddr (mem_waddr),
112
 
113
        .rclk (rclk),
114
        .rrst_n (rrst_n),
115
        .ren (ren),
116
        .rempty (rempty),
117
        .ralmost_empty (ralmost_empty),
118
 
119
        .mem_ren (mem_ren),
120
        .mem_raddr (mem_raddr)
121
        );
122
 
123
 
124
generate
125
    if (MEM_TYPE == `MEM_AUTO_SMALL) begin
126
 
127
        generic_mem_small #(.DWIDTH (DWIDTH),
128
                            .AWIDTH (AWIDTH),
129
                            .RAM_DEPTH (RAM_DEPTH),
130
                            .SYNC_WRITE (SYNC_WRITE),
131
                            .SYNC_READ (SYNC_READ),
132
                            .REGISTER_READ (REGISTER_READ)
133
                            )
134
          mem0(.wclk (wclk),
135
               .wrst_n (wrst_n),
136
               .wen (mem_wen),
137
               .waddr (mem_waddr),
138
               .wdata (wdata),
139
 
140
               .rclk (rclk),
141
               .rrst_n (rrst_n),
142
               .ren (mem_ren),
143
               .roen (ren),
144
               .raddr (mem_raddr),
145
               .rdata (rdata)
146
               );
147
 
148
    end
149
 
150
    if (MEM_TYPE == `MEM_AUTO_MEDIUM) begin
151
 
152
        generic_mem_medium #(.DWIDTH (DWIDTH),
153
                             .AWIDTH (AWIDTH),
154
                             .RAM_DEPTH (RAM_DEPTH),
155
                             .SYNC_WRITE (SYNC_WRITE),
156
                             .SYNC_READ (SYNC_READ),
157
                             .REGISTER_READ (REGISTER_READ)
158
                             )
159
          mem0(.wclk (wclk),
160
               .wrst_n (wrst_n),
161
               .wen (mem_wen),
162
               .waddr (mem_waddr),
163
               .wdata (wdata),
164
 
165
               .rclk (rclk),
166
               .rrst_n (rrst_n),
167
               .ren (mem_ren),
168
               .raddr (mem_raddr),
169
               .rdata (rdata)
170
               );
171
 
172
    end
173
 
174
endgenerate
175
 
176
endmodule
177
 
178
 
179
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.