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[/] [xge_mac/] [tags/] [initial/] [tbench/] [verilog/] [tb_xge_mac.v] - Blame information for rev 7

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "tb_xge_mac.v"                                    ////
////                                                              ////
////  This file is part of the "10GE MAC" project                 ////
////  http://www.opencores.org/cores/xge_mac/                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - A. Tanguay (antanguay@opencores.org)                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
`include "timescale.v"
`include "defines.v"
 
module tb;
 
 
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
// End of automatics
 
reg [7:0]     tx_buffer[0:10000];
integer       tx_length;
 
reg           clk_156m25;
reg           clk_xgmii_rx;
reg           clk_xgmii_tx;
 
reg           reset_156m25_n;
reg           reset_xgmii_rx_n;
reg           reset_xgmii_tx_n;
 
reg           pkt_rx_ren;
 
reg  [63:0]   pkt_tx_data;
reg           pkt_tx_val;
reg           pkt_tx_sop;
reg  [7:0]    pkt_tx_eop;
 
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire                    pkt_rx_avail;           // From dut of xge_mac.v
wire [63:0]             pkt_rx_data;            // From dut of xge_mac.v
wire [7:0]              pkt_rx_eop;             // From dut of xge_mac.v
wire                    pkt_rx_err;             // From dut of xge_mac.v
wire                    pkt_rx_sop;             // From dut of xge_mac.v
wire                    pkt_rx_val;             // From dut of xge_mac.v
wire                    pkt_tx_full;            // From dut of xge_mac.v
wire                    wb_ack_o;               // From dut of xge_mac.v
wire [31:0]             wb_dat_o;               // From dut of xge_mac.v
wire                    wb_int_o;               // From dut of xge_mac.v
wire [7:0]              xgmii_txc;              // From dut of xge_mac.v
wire [63:0]             xgmii_txd;              // From dut of xge_mac.v
// End of automatics
 
wire  [7:0]   wb_adr_i;
wire  [31:0]  wb_dat_i;
 
wire [7:0]              xgmii_rxc;
wire [63:0]             xgmii_rxd;
 
 
xge_mac dut(/*AUTOINST*/
            // Outputs
            .pkt_rx_avail               (pkt_rx_avail),
            .pkt_rx_data                (pkt_rx_data[63:0]),
            .pkt_rx_eop                 (pkt_rx_eop[7:0]),
            .pkt_rx_err                 (pkt_rx_err),
            .pkt_rx_sop                 (pkt_rx_sop),
            .pkt_rx_val                 (pkt_rx_val),
            .pkt_tx_full                (pkt_tx_full),
            .wb_ack_o                   (wb_ack_o),
            .wb_dat_o                   (wb_dat_o[31:0]),
            .wb_int_o                   (wb_int_o),
            .xgmii_txc                  (xgmii_txc[7:0]),
            .xgmii_txd                  (xgmii_txd[63:0]),
            // Inputs
            .clk_156m25                 (clk_156m25),
            .clk_xgmii_rx               (clk_xgmii_rx),
            .clk_xgmii_tx               (clk_xgmii_tx),
            .pkt_rx_ren                 (pkt_rx_ren),
            .pkt_tx_data                (pkt_tx_data[63:0]),
            .pkt_tx_eop                 (pkt_tx_eop[7:0]),
            .pkt_tx_sop                 (pkt_tx_sop),
            .pkt_tx_val                 (pkt_tx_val),
            .reset_156m25_n             (reset_156m25_n),
            .reset_xgmii_rx_n           (reset_xgmii_rx_n),
            .reset_xgmii_tx_n           (reset_xgmii_tx_n),
            .wb_adr_i                   (wb_adr_i[7:0]),
            .wb_clk_i                   (wb_clk_i),
            .wb_cyc_i                   (wb_cyc_i),
            .wb_dat_i                   (wb_dat_i[31:0]),
            .wb_rst_i                   (wb_rst_i),
            .wb_stb_i                   (wb_stb_i),
            .wb_we_i                    (wb_we_i),
            .xgmii_rxc                  (xgmii_rxc[7:0]),
            .xgmii_rxd                  (xgmii_rxd[63:0]));
 
 
//---
// Unused for this testbench
 
assign wb_adr_i = 8'b0;
assign wb_clk_i = 1'b0;
assign wb_cyc_i = 1'b0;
assign wb_dat_i = 32'b0;
assign wb_rst_i = 1'b1;
assign wb_stb_i = 1'b0;
assign wb_we_i = 1'b0;
 
 
//---
// XGMII Loopback
// This test is done with loopback on XGMII
 
assign xgmii_rxc = xgmii_txc;
assign xgmii_rxd = xgmii_txd;
 
 
//---
// Clock generation
 
initial begin
    clk_156m25 = 1'b0;
    clk_xgmii_rx = 1'b0;
    clk_xgmii_tx = 1'b0;
    forever begin
        WaitPS(3200);
        clk_156m25 = ~clk_156m25;
        clk_xgmii_rx = ~clk_xgmii_rx;
        clk_xgmii_tx = ~clk_xgmii_tx;
    end
end
 
 
//---
// Reset Generation
 
initial begin
    reset_156m25_n = 1'b0;
    reset_xgmii_rx_n = 1'b0;
    reset_xgmii_tx_n = 1'b0;
    WaitNS(20);
    reset_156m25_n = 1'b1;
    reset_xgmii_rx_n = 1'b1;
    reset_xgmii_tx_n = 1'b1;
end
 
 
//---
// Init signals
 
initial begin
 
    for (tx_length = 0; tx_length <= 1000; tx_length = tx_length + 1) begin
        tx_buffer[tx_length] = 0;
    end
 
    pkt_rx_ren = 1'b0;
 
    pkt_tx_data = 64'b0;
    pkt_tx_val = 1'b0;
    pkt_tx_sop = 1'b0;
    pkt_tx_eop = 8'b0;
 
end
 
task WaitNS;
  input [31:0] delay;
    begin
        #(1000*delay);
    end
endtask
 
task WaitPS;
  input [31:0] delay;
    begin
        #(delay);
    end
endtask
 
 
//---
// Task to send a single packet
 
task TxPacket;
  integer        i;
    begin
 
        $display("Transmit packet with length: %d", tx_length);
 
        @(posedge clk_156m25);
        WaitNS(1);
        pkt_tx_val = 1'b1;
 
        for (i = 0; i < tx_length; i = i + 8) begin
 
            pkt_tx_sop = 1'b0;
            pkt_tx_eop = 8'b0;
 
            if (i == 0) pkt_tx_sop = 1'b1;
            if (i + 8 >= tx_length) pkt_tx_eop[tx_length-i-1] = 1'b1;
 
            pkt_tx_data[`LANE0] = tx_buffer[i];
            pkt_tx_data[`LANE1] = tx_buffer[i+1];
            pkt_tx_data[`LANE2] = tx_buffer[i+2];
            pkt_tx_data[`LANE3] = tx_buffer[i+3];
            pkt_tx_data[`LANE4] = tx_buffer[i+4];
            pkt_tx_data[`LANE5] = tx_buffer[i+5];
            pkt_tx_data[`LANE6] = tx_buffer[i+6];
            pkt_tx_data[`LANE7] = tx_buffer[i+7];
 
            @(posedge clk_156m25);
            WaitNS(1);
 
        end
 
        pkt_tx_val = 1'b0;
        pkt_tx_eop = 8'b0;
 
    end
 
endtask
 
 
//---
// Task to read a single packet from command file and transmit
 
task CmdTxPacket;
  input [31:0] file;
  integer count;
  integer data;
  integer i;
    begin
 
        count = $fscanf(file, "%2d", tx_length);
 
        if (count == 1) begin
 
            for (i = 0; i < tx_length; i = i + 1) begin
 
                count = $fscanf(file, "%2X", data);
                if (count) begin
                    tx_buffer[i] = data;
                end
 
            end
 
            TxPacket();
 
        end
    end
 
endtask
 
 
//---
// Task to read commands from file and stop when complete
 
task ProcessCmdFile;
  integer    file_cmd;
  integer  count;
  reg [8*8-1:0] str;
    begin
 
        file_cmd = $fopen("../../tbench/verilog/packets_tx.txt", "r");
        if (!file_cmd) $stop;
 
        while (!$feof(file_cmd)) begin
 
            count = $fscanf(file_cmd, "%s", str);
            if (count != 1) $stop;
 
            $display("CMD %s", str);
 
            case (str)
 
              "SEND_PKT":
                begin
                    CmdTxPacket(file_cmd);
                end
 
            endcase
 
        end
 
        $fclose(file_cmd);
 
        WaitNS(2000);
        $stop;
 
    end
endtask
 
initial begin
    WaitNS(2000);
    ProcessCmdFile();
end
 
 
//---
// Task to read a single packet from receive interface and display
 
task RxPacket;
  reg done;
    begin
 
        done = 0;
 
        pkt_rx_ren <= 1'b1;
        @(posedge clk_156m25);
 
        while (!done) begin
 
            if (pkt_rx_val) begin
 
                if (pkt_rx_sop) begin
                    $display("\n\n------------------------");
                end
 
                $display("%x", pkt_rx_data);
 
                if (pkt_rx_eop) begin
                    done <= 1;
                    pkt_rx_ren <= 1'b0;
                end
 
                if (pkt_rx_eop) begin
                    $display("------------------------\n\n");
                end
 
            end
 
            @(posedge clk_156m25);
 
        end
 
    end
endtask
 
initial begin
 
    forever begin
 
        if (pkt_rx_avail) begin
            RxPacket();
        end
 
        @(posedge clk_156m25);
 
    end
 
end
 
endmodule
 

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[/] [xge_mac/] [tags/] [initial/] [tbench/] [verilog/] [tb_xge_mac.v] - Blame information for rev 7

Line No.	Rev	Author	Line
1	2	antanguay	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "tb_xge_mac.v" ////`
4			`//// ////`
5			`//// This file is part of the "10GE MAC" project ////`
6			`//// http://www.opencores.org/cores/xge_mac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - A. Tanguay (antanguay@opencores.org) ////`
10			`//// ////`
11			`//////////////////////////////////////////////////////////////////////`
12			`//// ////`
13			`//// Copyright (C) 2008 AUTHORS. All rights reserved. ////`
14			`//// ////`
15			`//// This source file may be used and distributed without ////`
16			`//// restriction provided that this copyright statement is not ////`
17			`//// removed from the file and that any derivative work contains ////`
18			`//// the original copyright notice and the associated disclaimer. ////`
19			`//// ////`
20			`//// This source file is free software; you can redistribute it ////`
21			`//// and/or modify it under the terms of the GNU Lesser General ////`
22			`//// Public License as published by the Free Software Foundation; ////`
23			`//// either version 2.1 of the License, or (at your option) any ////`
24			`//// later version. ////`
25			`//// ////`
26			`//// This source is distributed in the hope that it will be ////`
27			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
28			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
29			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
30			`//// details. ////`
31			`//// ////`
32			`//// You should have received a copy of the GNU Lesser General ////`
33			`//// Public License along with this source; if not, download it ////`
34			`//// from http://www.opencores.org/lgpl.shtml ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37
38
39			`include "timescale.v"
40			`include "defines.v"
41
42			`module tb;`
43
44
45			`/AUTOREG/`
46			`// Beginning of automatic regs (for this module's undeclared outputs)`
47			`// End of automatics`
48
49			`reg [7:0] tx_buffer[0:10000];`
50			`integer tx_length;`
51
52			`reg clk_156m25;`
53			`reg clk_xgmii_rx;`
54			`reg clk_xgmii_tx;`
55
56			`reg reset_156m25_n;`
57			`reg reset_xgmii_rx_n;`
58			`reg reset_xgmii_tx_n;`
59
60			`reg pkt_rx_ren;`
61
62			`reg [63:0] pkt_tx_data;`
63			`reg pkt_tx_val;`
64			`reg pkt_tx_sop;`
65			`reg [7:0] pkt_tx_eop;`
66
67			`/AUTOWIRE/`
68			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
69			`wire pkt_rx_avail; // From dut of xge_mac.v`
70			`wire [63:0] pkt_rx_data; // From dut of xge_mac.v`
71			`wire [7:0] pkt_rx_eop; // From dut of xge_mac.v`
72			`wire pkt_rx_err; // From dut of xge_mac.v`
73			`wire pkt_rx_sop; // From dut of xge_mac.v`
74			`wire pkt_rx_val; // From dut of xge_mac.v`
75			`wire pkt_tx_full; // From dut of xge_mac.v`
76			`wire wb_ack_o; // From dut of xge_mac.v`
77			`wire [31:0] wb_dat_o; // From dut of xge_mac.v`
78			`wire wb_int_o; // From dut of xge_mac.v`
79			`wire [7:0] xgmii_txc; // From dut of xge_mac.v`
80			`wire [63:0] xgmii_txd; // From dut of xge_mac.v`
81			`// End of automatics`
82
83			`wire [7:0] wb_adr_i;`
84			`wire [31:0] wb_dat_i;`
85
86			`wire [7:0] xgmii_rxc;`
87			`wire [63:0] xgmii_rxd;`
88
89
90			`xge_mac dut(/AUTOINST/`
91			`// Outputs`
92			`.pkt_rx_avail (pkt_rx_avail),`
93			`.pkt_rx_data (pkt_rx_data[63:0]),`
94			`.pkt_rx_eop (pkt_rx_eop[7:0]),`
95			`.pkt_rx_err (pkt_rx_err),`
96			`.pkt_rx_sop (pkt_rx_sop),`
97			`.pkt_rx_val (pkt_rx_val),`
98			`.pkt_tx_full (pkt_tx_full),`
99			`.wb_ack_o (wb_ack_o),`
100			`.wb_dat_o (wb_dat_o[31:0]),`
101			`.wb_int_o (wb_int_o),`
102			`.xgmii_txc (xgmii_txc[7:0]),`
103			`.xgmii_txd (xgmii_txd[63:0]),`
104			`// Inputs`
105			`.clk_156m25 (clk_156m25),`
106			`.clk_xgmii_rx (clk_xgmii_rx),`
107			`.clk_xgmii_tx (clk_xgmii_tx),`
108			`.pkt_rx_ren (pkt_rx_ren),`
109			`.pkt_tx_data (pkt_tx_data[63:0]),`
110			`.pkt_tx_eop (pkt_tx_eop[7:0]),`
111			`.pkt_tx_sop (pkt_tx_sop),`
112			`.pkt_tx_val (pkt_tx_val),`
113			`.reset_156m25_n (reset_156m25_n),`
114			`.reset_xgmii_rx_n (reset_xgmii_rx_n),`
115			`.reset_xgmii_tx_n (reset_xgmii_tx_n),`
116			`.wb_adr_i (wb_adr_i[7:0]),`
117			`.wb_clk_i (wb_clk_i),`
118			`.wb_cyc_i (wb_cyc_i),`
119			`.wb_dat_i (wb_dat_i[31:0]),`
120			`.wb_rst_i (wb_rst_i),`
121			`.wb_stb_i (wb_stb_i),`
122			`.wb_we_i (wb_we_i),`
123			`.xgmii_rxc (xgmii_rxc[7:0]),`
124			`.xgmii_rxd (xgmii_rxd[63:0]));`
125
126
127			`//---`
128			`// Unused for this testbench`
129
130			`assign wb_adr_i = 8'b0;`
131			`assign wb_clk_i = 1'b0;`
132			`assign wb_cyc_i = 1'b0;`
133			`assign wb_dat_i = 32'b0;`
134			`assign wb_rst_i = 1'b1;`
135			`assign wb_stb_i = 1'b0;`
136			`assign wb_we_i = 1'b0;`
137
138
139			`//---`
140			`// XGMII Loopback`
141			`// This test is done with loopback on XGMII`
142
143			`assign xgmii_rxc = xgmii_txc;`
144			`assign xgmii_rxd = xgmii_txd;`
145
146
147			`//---`
148			`// Clock generation`
149
150			`initial begin`
151			`clk_156m25 = 1'b0;`
152			`clk_xgmii_rx = 1'b0;`
153			`clk_xgmii_tx = 1'b0;`
154			`forever begin`
155			`WaitPS(3200);`
156			`clk_156m25 = ~clk_156m25;`
157			`clk_xgmii_rx = ~clk_xgmii_rx;`
158			`clk_xgmii_tx = ~clk_xgmii_tx;`
159			`end`
160			`end`
161
162
163			`//---`
164			`// Reset Generation`
165
166			`initial begin`
167			`reset_156m25_n = 1'b0;`
168			`reset_xgmii_rx_n = 1'b0;`
169			`reset_xgmii_tx_n = 1'b0;`
170			`WaitNS(20);`
171			`reset_156m25_n = 1'b1;`
172			`reset_xgmii_rx_n = 1'b1;`
173			`reset_xgmii_tx_n = 1'b1;`
174			`end`
175
176
177			`//---`
178			`// Init signals`
179
180			`initial begin`
181
182			`for (tx_length = 0; tx_length <= 1000; tx_length = tx_length + 1) begin`
183			`tx_buffer[tx_length] = 0;`
184			`end`
185
186			`pkt_rx_ren = 1'b0;`
187
188			`pkt_tx_data = 64'b0;`
189			`pkt_tx_val = 1'b0;`
190			`pkt_tx_sop = 1'b0;`
191			`pkt_tx_eop = 8'b0;`
192
193			`end`
194
195			`task WaitNS;`
196			`input [31:0] delay;`
197			`begin`
198			`#(1000*delay);`
199			`end`
200			`endtask`
201
202			`task WaitPS;`
203			`input [31:0] delay;`
204			`begin`
205			`#(delay);`
206			`end`
207			`endtask`
208
209
210			`//---`
211			`// Task to send a single packet`
212
213			`task TxPacket;`
214			`integer i;`
215			`begin`
216
217			`$display("Transmit packet with length: %d", tx_length);`
218
219			`@(posedge clk_156m25);`
220			`WaitNS(1);`
221			`pkt_tx_val = 1'b1;`
222
223			`for (i = 0; i < tx_length; i = i + 8) begin`
224
225			`pkt_tx_sop = 1'b0;`
226			`pkt_tx_eop = 8'b0;`
227
228			`if (i == 0) pkt_tx_sop = 1'b1;`
229			`if (i + 8 >= tx_length) pkt_tx_eop[tx_length-i-1] = 1'b1;`
230
231			pkt_tx_data[`LANE0] = tx_buffer[i];
232			pkt_tx_data[`LANE1] = tx_buffer[i+1];
233			pkt_tx_data[`LANE2] = tx_buffer[i+2];
234			pkt_tx_data[`LANE3] = tx_buffer[i+3];
235			pkt_tx_data[`LANE4] = tx_buffer[i+4];
236			pkt_tx_data[`LANE5] = tx_buffer[i+5];
237			pkt_tx_data[`LANE6] = tx_buffer[i+6];
238			pkt_tx_data[`LANE7] = tx_buffer[i+7];
239
240			`@(posedge clk_156m25);`
241			`WaitNS(1);`
242
243			`end`
244
245			`pkt_tx_val = 1'b0;`
246			`pkt_tx_eop = 8'b0;`
247
248			`end`
249
250			`endtask`
251
252
253			`//---`
254			`// Task to read a single packet from command file and transmit`
255
256			`task CmdTxPacket;`
257			`input [31:0] file;`
258			`integer count;`
259			`integer data;`
260			`integer i;`
261			`begin`
262
263			`count = $fscanf(file, "%2d", tx_length);`
264
265			`if (count == 1) begin`
266
267			`for (i = 0; i < tx_length; i = i + 1) begin`
268
269			`count = $fscanf(file, "%2X", data);`
270			`if (count) begin`
271			`tx_buffer[i] = data;`
272			`end`
273
274			`end`
275
276			`TxPacket();`
277
278			`end`
279			`end`
280
281			`endtask`
282
283
284			`//---`
285			`// Task to read commands from file and stop when complete`
286
287			`task ProcessCmdFile;`
288			`integer file_cmd;`
289			`integer count;`
290			`reg [8*8-1:0] str;`
291			`begin`
292
293			`file_cmd = $fopen("../../tbench/verilog/packets_tx.txt", "r");`
294			`if (!file_cmd) $stop;`
295
296			`while (!$feof(file_cmd)) begin`
297
298			`count = $fscanf(file_cmd, "%s", str);`
299			`if (count != 1) $stop;`
300
301			`$display("CMD %s", str);`
302
303			`case (str)`
304
305			`"SEND_PKT":`
306			`begin`
307			`CmdTxPacket(file_cmd);`
308			`end`
309
310			`endcase`
311
312			`end`
313
314			`$fclose(file_cmd);`
315
316			`WaitNS(2000);`
317			`$stop;`
318
319			`end`
320			`endtask`
321
322			`initial begin`
323			`WaitNS(2000);`
324			`ProcessCmdFile();`
325			`end`
326
327
328			`//---`
329			`// Task to read a single packet from receive interface and display`
330
331			`task RxPacket;`
332			`reg done;`
333			`begin`
334
335			`done = 0;`
336
337			`pkt_rx_ren <= 1'b1;`
338			`@(posedge clk_156m25);`
339
340			`while (!done) begin`
341
342			`if (pkt_rx_val) begin`
343
344			`if (pkt_rx_sop) begin`
345			`$display("\n\n------------------------");`
346			`end`
347
348			`$display("%x", pkt_rx_data);`
349
350			`if (pkt_rx_eop) begin`
351			`done <= 1;`
352			`pkt_rx_ren <= 1'b0;`
353			`end`
354
355			`if (pkt_rx_eop) begin`
356			`$display("------------------------\n\n");`
357			`end`
358
359			`end`
360
361			`@(posedge clk_156m25);`
362
363			`end`
364
365			`end`
366			`endtask`
367
368			`initial begin`
369
370			`forever begin`
371
372			`if (pkt_rx_avail) begin`
373			`RxPacket();`
374			`end`
375
376			`@(posedge clk_156m25);`
377
378			`end`
379
380			`end`
381
382			`endmodule`
383