OpenCores
URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [fault_sm.v] - Blame information for rev 24

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 antanguay
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  File name "fault_sm.v"                                      ////
4
////                                                              ////
5
////  This file is part of the "10GE MAC" project                 ////
6
////  http://www.opencores.org/cores/xge_mac/                     ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - A. Tanguay (antanguay@opencores.org)                  ////
10
////                                                              ////
11
//////////////////////////////////////////////////////////////////////
12
////                                                              ////
13
//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
14
////                                                              ////
15
//// This source file may be used and distributed without         ////
16
//// restriction provided that this copyright statement is not    ////
17
//// removed from the file and that any derivative work contains  ////
18
//// the original copyright notice and the associated disclaimer. ////
19
////                                                              ////
20
//// This source file is free software; you can redistribute it   ////
21
//// and/or modify it under the terms of the GNU Lesser General   ////
22
//// Public License as published by the Free Software Foundation; ////
23
//// either version 2.1 of the License, or (at your option) any   ////
24
//// later version.                                               ////
25
////                                                              ////
26
//// This source is distributed in the hope that it will be       ////
27
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
28
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
29
//// PURPOSE.  See the GNU Lesser General Public License for more ////
30
//// details.                                                     ////
31
////                                                              ////
32
//// You should have received a copy of the GNU Lesser General    ////
33
//// Public License along with this source; if not, download it   ////
34
//// from http://www.opencores.org/lgpl.shtml                     ////
35
////                                                              ////
36
//////////////////////////////////////////////////////////////////////
37
 
38
 
39
`include "defines.v"
40
 
41
module fault_sm(/*AUTOARG*/
42
  // Outputs
43 12 antanguay
  status_local_fault_crx, status_remote_fault_crx,
44 2 antanguay
  // Inputs
45 12 antanguay
  clk_xgmii_rx, reset_xgmii_rx_n, local_fault_msg_det,
46 2 antanguay
  remote_fault_msg_det
47
  );
48
 
49
input         clk_xgmii_rx;
50
input         reset_xgmii_rx_n;
51
 
52
input  [1:0]  local_fault_msg_det;
53
input  [1:0]  remote_fault_msg_det;
54
 
55
output        status_local_fault_crx;
56
output        status_remote_fault_crx;
57
 
58
/*AUTOREG*/
59
// Beginning of automatic regs (for this module's undeclared outputs)
60
reg                     status_local_fault_crx;
61
reg                     status_remote_fault_crx;
62
// End of automatics
63
 
64
reg    [1:0]  curr_state;
65
 
66
reg    [7:0]  col_cnt;
67
reg    [1:0]  fault_sequence;
68
reg    [1:0]  last_seq_type;
69
reg    [1:0]  link_fault;
70
reg    [2:0]  seq_cnt;
71
reg    [1:0]  seq_type;
72
 
73
reg    [1:0]  seq_add;
74
 
75
/*AUTOWIRE*/
76
 
77
 
78
parameter [1:0]
79
             SM_INIT       = 2'd0,
80
             SM_COUNT      = 2'd1,
81
             SM_FAULT      = 2'd2,
82
             SM_NEW_FAULT  = 2'd3;
83
 
84
 
85
always @(/*AS*/local_fault_msg_det or remote_fault_msg_det) begin
86
 
87
    //---
88
    // Fault indication. Indicate remote or local fault
89
 
90
    fault_sequence = local_fault_msg_det | remote_fault_msg_det;
91
 
92
 
93
    //---
94
    // Sequence type, local, remote, or ok
95
 
96
    if (|local_fault_msg_det) begin
97
        seq_type = `LINK_FAULT_LOCAL;
98
    end
99
    else if (|remote_fault_msg_det) begin
100
        seq_type = `LINK_FAULT_REMOTE;
101
    end
102
    else begin
103
        seq_type = `LINK_FAULT_OK;
104
    end
105
 
106
 
107
    //---
108
    // Adder for number of faults, if detected in lower 4 lanes and
109
    // upper 4 lanes, add 2. That's because we process 64-bit at a time
110
    // instead of typically 32-bit xgmii.
111
 
112
    if (|remote_fault_msg_det) begin
113
        seq_add = remote_fault_msg_det[1] + remote_fault_msg_det[0];
114
    end
115
    else begin
116
        seq_add = local_fault_msg_det[1] + local_fault_msg_det[0];
117
    end
118
 
119
end
120
 
121
always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin
122
 
123
    if (reset_xgmii_rx_n == 1'b0) begin
124
 
125
 
126
        status_local_fault_crx <= 1'b0;
127
        status_remote_fault_crx <= 1'b0;
128
 
129
    end
130
    else begin
131
 
132
        //---
133
        // Status signal to generate local/remote fault interrupts
134
 
135
        status_local_fault_crx <= curr_state == SM_FAULT &&
136
                                  link_fault == `LINK_FAULT_LOCAL;
137
 
138
        status_remote_fault_crx <= curr_state == SM_FAULT &&
139
                                   link_fault == `LINK_FAULT_REMOTE;
140
 
141
    end
142
 
143
end
144
 
145
always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin
146
 
147
    if (reset_xgmii_rx_n == 1'b0) begin
148
 
149
        curr_state <= SM_INIT;
150
 
151
        col_cnt <= 8'b0;
152
        last_seq_type <= `LINK_FAULT_OK;
153
        link_fault <= `LINK_FAULT_OK;
154
        seq_cnt <= 3'b0;
155
 
156
    end
157
    else begin
158
 
159
        case (curr_state)
160
 
161
          SM_INIT:
162
            begin
163
 
164
                last_seq_type <= seq_type;
165
 
166
                if (|fault_sequence) begin
167
 
168
                    // If a fault is detected, capture the type of
169
                    // fault and start column counter. We need 4 fault
170
                    // messages in 128 columns to accept the fault.
171
 
172
                    if (fault_sequence[0]) begin
173
                        col_cnt <= 8'd2;
174
                    end
175
                    else begin
176
                        col_cnt <= 8'd1;
177
                    end
178
                    seq_cnt <= {1'b0, seq_add};
179
                    curr_state <= SM_COUNT;
180
 
181
                end
182
                else begin
183
 
184
                    // If no faults, stay in INIT and clear counters
185
 
186
                    col_cnt <= 8'b0;
187
                    seq_cnt <= 3'b0;
188
 
189
                end
190
            end
191
 
192
          SM_COUNT:
193
            begin
194
 
195
                col_cnt <= col_cnt + 8'd2;
196
                seq_cnt <= seq_cnt + {1'b0, seq_add};
197
 
198
                if (!fault_sequence[0] && col_cnt >= 8'd127) begin
199
 
200
                    // No new fault in lower lanes and almost
201
                    // reached the 128 columns count, abort fault. 
202
 
203
                    curr_state <= SM_INIT;
204
 
205
                end
206
                else if (col_cnt > 8'd127) begin
207
 
208
                    // Reached the 128 columns count, abort fault.
209
 
210
                    curr_state <= SM_INIT;
211
 
212
                end
213
                else if (|fault_sequence) begin
214
 
215
                    // If fault type has changed, move to NEW_FAULT.
216
                    // If not, after detecting 4 fault messages move to
217
                    // FAULT state.
218
 
219
                    if (seq_type != last_seq_type) begin
220
                        curr_state <= SM_NEW_FAULT;
221
                    end
222
                    else begin
223
                        if ((seq_cnt + {1'b0, seq_add}) > 3'd3) begin
224
                            col_cnt <= 8'b0;
225
                            link_fault <= seq_type;
226
                            curr_state <= SM_FAULT;
227
                        end
228
                    end
229
 
230
                end
231
            end
232
 
233
          SM_FAULT:
234
            begin
235
 
236
                col_cnt <= col_cnt + 8'd2;
237
 
238
                if (!fault_sequence[0] && col_cnt >= 8'd127) begin
239
 
240
                    // No new fault in lower lanes and almost
241
                    // reached the 128 columns count, abort fault. 
242
 
243
                    curr_state <= SM_INIT;
244
 
245
                end
246
                else if (col_cnt > 8'd127) begin
247
 
248
                    // Reached the 128 columns count, abort fault.
249
 
250
                    curr_state <= SM_INIT;
251
 
252
                end
253
                else if (|fault_sequence) begin
254
 
255
                    // Clear the column count each time we see a fault,
256
                    // if fault changes, go no next state.
257
 
258
                    col_cnt <= 8'd0;
259
 
260
                    if (seq_type != last_seq_type) begin
261
                        curr_state <= SM_NEW_FAULT;
262
                    end
263
                end
264
 
265
            end
266
 
267
          SM_NEW_FAULT:
268
            begin
269
 
270
                // Capture new fault type. Start counters.
271
 
272
                col_cnt <= 8'b0;
273
                last_seq_type <= seq_type;
274
 
275
                seq_cnt <= {1'b0, seq_add};
276
                curr_state <= SM_COUNT;
277
 
278
            end
279
 
280
        endcase
281
 
282
    end
283
 
284
end
285
 
286
endmodule
287
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.