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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [generic_mem_medium.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "generic_mem_medium.v"                            ////
////                                                              ////
////  This file is part of the "10GE MAC" project                 ////
////  http://www.opencores.org/cores/xge_mac/                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - A. Tanguay (antanguay@opencores.org)                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
/* synthesis ramstyle = "M4K" */
 
module generic_mem_medium(
 
    wclk,
    wrst_n,
    wen,
    waddr,
    wdata,
 
    rclk,
    rrst_n,
    ren,
    roen,
    raddr,
    rdata
);
 
//---
// Parameters
 
parameter DWIDTH = 32;
parameter AWIDTH = 3;
parameter RAM_DEPTH = (1 << AWIDTH);
parameter SYNC_WRITE = 1;
parameter SYNC_READ = 1;
parameter REGISTER_READ = 0;
 
//---
// Ports
 
input               wclk;
input               wrst_n;
input               wen;
input  [AWIDTH:0]   waddr;
input  [DWIDTH-1:0] wdata;
 
input               rclk;
input               rrst_n;
input               ren;
input               roen;
input  [AWIDTH:0]   raddr;
output [DWIDTH-1:0] rdata;
 
// Registered outputs
reg    [DWIDTH-1:0] rdata;
 
 
//---
// Local declarations
 
// Registers
 
reg  [DWIDTH-1:0] mem_rdata;
 
 
// Memory
 
reg  [DWIDTH-1:0] mem [0:RAM_DEPTH-1];
 
// Variables
 
integer         i;
 
 
//---
// Memory Write
 
generate
    if (SYNC_WRITE) begin
 
        // Generate synchronous write
        always @(posedge wclk)
        begin
            if (wen) begin
                mem[waddr[AWIDTH-1:0]] <= wdata;
            end
        end
    end
    else begin
 
        // Generate asynchronous write
        always @(wen, waddr, wdata)
        begin
            if (wen) begin
                mem[waddr[AWIDTH-1:0]] = wdata;
            end
        end
    end
endgenerate
 
//---
// Memory Read
 
generate
    if (SYNC_READ) begin
 
        // Generate registered memory read
        always @(posedge rclk or negedge rrst_n)
        begin
            if (!rrst_n) begin
                mem_rdata <= {(DWIDTH){1'b0}};
            end else if (ren) begin
                mem_rdata <= mem[raddr[AWIDTH-1:0]];
            end
        end
    end
    else begin
 
        // Generate unregisters memory read
        always @(raddr, rclk)
        begin
            mem_rdata = mem[raddr[AWIDTH-1:0]];
        end
    end
endgenerate
 
generate
    if (REGISTER_READ) begin
 
        // Generate registered output
        always @(posedge rclk or negedge rrst_n)
        begin
            if (!rrst_n) begin
                rdata <= {(DWIDTH){1'b0}};
            end else if (roen) begin
                rdata <= mem_rdata;
            end
        end
 
    end
    else begin
 
        // Generate unregisters output
        always @(mem_rdata)
        begin
            rdata = mem_rdata;
        end
 
    end
endgenerate
 
endmodule
 
 
 

Line No.	Rev	Author	Line
1	2	antanguay	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "generic_mem_medium.v" ////`
4			`//// ////`
5			`//// This file is part of the "10GE MAC" project ////`
6			`//// http://www.opencores.org/cores/xge_mac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - A. Tanguay (antanguay@opencores.org) ////`
10			`//// ////`
11			`//////////////////////////////////////////////////////////////////////`
12			`//// ////`
13			`//// Copyright (C) 2008 AUTHORS. All rights reserved. ////`
14			`//// ////`
15			`//// This source file may be used and distributed without ////`
16			`//// restriction provided that this copyright statement is not ////`
17			`//// removed from the file and that any derivative work contains ////`
18			`//// the original copyright notice and the associated disclaimer. ////`
19			`//// ////`
20			`//// This source file is free software; you can redistribute it ////`
21			`//// and/or modify it under the terms of the GNU Lesser General ////`
22			`//// Public License as published by the Free Software Foundation; ////`
23			`//// either version 2.1 of the License, or (at your option) any ////`
24			`//// later version. ////`
25			`//// ////`
26			`//// This source is distributed in the hope that it will be ////`
27			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
28			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
29			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
30			`//// details. ////`
31			`//// ////`
32			`//// You should have received a copy of the GNU Lesser General ////`
33			`//// Public License along with this source; if not, download it ////`
34			`//// from http://www.opencores.org/lgpl.shtml ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37
38			`/* synthesis ramstyle = "M4K" */`
39
40			`module generic_mem_medium(`
41
42			`wclk,`
43			`wrst_n,`
44			`wen,`
45			`waddr,`
46			`wdata,`
47
48			`rclk,`
49			`rrst_n,`
50			`ren,`
51			`roen,`
52			`raddr,`
53			`rdata`
54			`);`
55
56			`//---`
57			`// Parameters`
58
59			`parameter DWIDTH = 32;`
60			`parameter AWIDTH = 3;`
61			`parameter RAM_DEPTH = (1 << AWIDTH);`
62			`parameter SYNC_WRITE = 1;`
63			`parameter SYNC_READ = 1;`
64			`parameter REGISTER_READ = 0;`
65
66			`//---`
67			`// Ports`
68
69			`input wclk;`
70			`input wrst_n;`
71			`input wen;`
72			`input [AWIDTH:0] waddr;`
73			`input [DWIDTH-1:0] wdata;`
74
75			`input rclk;`
76			`input rrst_n;`
77			`input ren;`
78			`input roen;`
79			`input [AWIDTH:0] raddr;`
80			`output [DWIDTH-1:0] rdata;`
81
82			`// Registered outputs`
83			`reg [DWIDTH-1:0] rdata;`
84
85
86			`//---`
87			`// Local declarations`
88
89			`// Registers`
90
91			`reg [DWIDTH-1:0] mem_rdata;`
92
93
94			`// Memory`
95
96			`reg [DWIDTH-1:0] mem [0:RAM_DEPTH-1];`
97
98			`// Variables`
99
100			`integer i;`
101
102
103			`//---`
104			`// Memory Write`
105
106			`generate`
107			`if (SYNC_WRITE) begin`
108
109			`// Generate synchronous write`
110			`always @(posedge wclk)`
111			`begin`
112			`if (wen) begin`
113			`mem[waddr[AWIDTH-1:0]] <= wdata;`
114			`end`
115			`end`
116			`end`
117			`else begin`
118
119			`// Generate asynchronous write`
120			`always @(wen, waddr, wdata)`
121			`begin`
122			`if (wen) begin`
123			`mem[waddr[AWIDTH-1:0]] = wdata;`
124			`end`
125			`end`
126			`end`
127			`endgenerate`
128
129			`//---`
130			`// Memory Read`
131
132			`generate`
133			`if (SYNC_READ) begin`
134
135			`// Generate registered memory read`
136			`always @(posedge rclk or negedge rrst_n)`
137			`begin`
138			`if (!rrst_n) begin`
139			`mem_rdata <= {(DWIDTH){1'b0}};`
140			`end else if (ren) begin`
141			`mem_rdata <= mem[raddr[AWIDTH-1:0]];`
142			`end`
143			`end`
144			`end`
145			`else begin`
146
147			`// Generate unregisters memory read`
148			`always @(raddr, rclk)`
149			`begin`
150			`mem_rdata = mem[raddr[AWIDTH-1:0]];`
151			`end`
152			`end`
153			`endgenerate`
154
155			`generate`
156			`if (REGISTER_READ) begin`
157
158			`// Generate registered output`
159			`always @(posedge rclk or negedge rrst_n)`
160			`begin`
161			`if (!rrst_n) begin`
162			`rdata <= {(DWIDTH){1'b0}};`
163			`end else if (roen) begin`
164			`rdata <= mem_rdata;`
165			`end`
166			`end`
167
168			`end`
169			`else begin`
170
171			`// Generate unregisters output`
172			`always @(mem_rdata)`
173			`begin`
174			`rdata = mem_rdata;`
175			`end`
176
177			`end`
178			`endgenerate`
179
180			`endmodule`
181
182
183

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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [generic_mem_medium.v] - Blame information for rev 12