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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [meta_sync_single.v] - Blame information for rev 24

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "meta_sync_single.v"                              ////
////                                                              ////
////  This file is part of the "10GE MAC" project                 ////
////  http://www.opencores.org/cores/xge_mac/                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - A. Tanguay (antanguay@opencores.org)                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
module meta_sync_single(/*AUTOARG*/
  // Outputs
  out,
  // Inputs
  clk, reset_n, in
  );
 
parameter EDGE_DETECT = 0;
 
input   clk;
input   reset_n;
 
input   in;
 
output  out;
 
reg     out;
 
 
 
generate
 
    if (EDGE_DETECT) begin
 
      reg   meta;
      reg   edg1;
      reg   edg2;
 
        always @(posedge clk or negedge reset_n) begin
 
            if (reset_n == 1'b0) begin
                meta <= 1'b0;
                edg1 <= 1'b0;
                edg2 <= 1'b0;
                out <= 1'b0;
            end
            else begin
                meta <= in;
                edg1 <= meta;
                edg2 <= edg1;
                out <= edg1 ^ edg2;
            end
        end
 
    end
    else begin
 
      reg   meta;
 
        always @(posedge clk or negedge reset_n) begin
 
            if (reset_n == 1'b0) begin
                meta <= 1'b0;
                out <= 1'b0;
            end
            else begin
                meta <= in;
                out <= meta;
            end
        end
 
    end
 
endgenerate
 
endmodule
 

Line No.	Rev	Author	Line
1	2	antanguay	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "meta_sync_single.v" ////`
4			`//// ////`
5			`//// This file is part of the "10GE MAC" project ////`
6			`//// http://www.opencores.org/cores/xge_mac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - A. Tanguay (antanguay@opencores.org) ////`
10			`//// ////`
11			`//////////////////////////////////////////////////////////////////////`
12			`//// ////`
13			`//// Copyright (C) 2008 AUTHORS. All rights reserved. ////`
14			`//// ////`
15			`//// This source file may be used and distributed without ////`
16			`//// restriction provided that this copyright statement is not ////`
17			`//// removed from the file and that any derivative work contains ////`
18			`//// the original copyright notice and the associated disclaimer. ////`
19			`//// ////`
20			`//// This source file is free software; you can redistribute it ////`
21			`//// and/or modify it under the terms of the GNU Lesser General ////`
22			`//// Public License as published by the Free Software Foundation; ////`
23			`//// either version 2.1 of the License, or (at your option) any ////`
24			`//// later version. ////`
25			`//// ////`
26			`//// This source is distributed in the hope that it will be ////`
27			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
28			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
29			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
30			`//// details. ////`
31			`//// ////`
32			`//// You should have received a copy of the GNU Lesser General ////`
33			`//// Public License along with this source; if not, download it ////`
34			`//// from http://www.opencores.org/lgpl.shtml ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37
38
39			`module meta_sync_single(/AUTOARG/`
40			`// Outputs`
41			`out,`
42			`// Inputs`
43			`clk, reset_n, in`
44			`);`
45
46			`parameter EDGE_DETECT = 0;`
47
48			`input clk;`
49			`input reset_n;`
50
51			`input in;`
52
53			`output out;`
54
55			`reg out;`
56
57
58
59			`generate`
60
61			`if (EDGE_DETECT) begin`
62
63			`reg meta;`
64			`reg edg1;`
65			`reg edg2;`
66
67			`always @(posedge clk or negedge reset_n) begin`
68
69			`if (reset_n == 1'b0) begin`
70			`meta <= 1'b0;`
71			`edg1 <= 1'b0;`
72			`edg2 <= 1'b0;`
73			`out <= 1'b0;`
74			`end`
75			`else begin`
76			`meta <= in;`
77			`edg1 <= meta;`
78			`edg2 <= edg1;`
79			`out <= edg1 ^ edg2;`
80			`end`
81			`end`
82
83			`end`
84			`else begin`
85
86			`reg meta;`
87
88			`always @(posedge clk or negedge reset_n) begin`
89
90			`if (reset_n == 1'b0) begin`
91			`meta <= 1'b0;`
92			`out <= 1'b0;`
93			`end`
94			`else begin`
95			`meta <= in;`
96			`out <= meta;`
97			`end`
98			`end`
99
100			`end`
101
102			`endgenerate`
103
104			`endmodule`
105

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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [meta_sync_single.v] - Blame information for rev 24