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//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "wishbone.v" ////
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//// ////
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//// This file is part of the "10GE MAC" project ////
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//// http://www.opencores.org/cores/xge_mac/ ////
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//// ////
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//// Author(s): ////
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//// - A. Tanguay (antanguay@opencores.org) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module stats(/*AUTOARG*/
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// Outputs
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stats_tx_pkts, stats_tx_octets, stats_rx_pkts, stats_rx_octets,
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// Inputs
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wb_rst_i, wb_clk_i, txsfifo_wen, txsfifo_wdata, rxsfifo_wen,
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rxsfifo_wdata, reset_xgmii_tx_n, reset_xgmii_rx_n, clk_xgmii_tx,
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clk_xgmii_rx, clear_stats_tx_pkts, clear_stats_tx_octets,
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clear_stats_rx_pkts, clear_stats_rx_octets
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);
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input clear_stats_rx_octets; // To stats_sm0 of stats_sm.v
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input clear_stats_rx_pkts; // To stats_sm0 of stats_sm.v
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input clear_stats_tx_octets; // To stats_sm0 of stats_sm.v
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input clear_stats_tx_pkts; // To stats_sm0 of stats_sm.v
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input clk_xgmii_rx; // To rx_stats_fifo0 of rx_stats_fifo.v
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input clk_xgmii_tx; // To tx_stats_fifo0 of tx_stats_fifo.v
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input reset_xgmii_rx_n; // To rx_stats_fifo0 of rx_stats_fifo.v
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input reset_xgmii_tx_n; // To tx_stats_fifo0 of tx_stats_fifo.v
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input [13:0] rxsfifo_wdata; // To rx_stats_fifo0 of rx_stats_fifo.v
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input rxsfifo_wen; // To rx_stats_fifo0 of rx_stats_fifo.v
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input [13:0] txsfifo_wdata; // To tx_stats_fifo0 of tx_stats_fifo.v
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input txsfifo_wen; // To tx_stats_fifo0 of tx_stats_fifo.v
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input wb_clk_i; // To tx_stats_fifo0 of tx_stats_fifo.v, ...
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input wb_rst_i; // To tx_stats_fifo0 of tx_stats_fifo.v, ...
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// End of automatics
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output [31:0] stats_rx_octets; // From stats_sm0 of stats_sm.v
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output [31:0] stats_rx_pkts; // From stats_sm0 of stats_sm.v
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output [31:0] stats_tx_octets; // From stats_sm0 of stats_sm.v
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output [31:0] stats_tx_pkts; // From stats_sm0 of stats_sm.v
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [13:0] rxsfifo_rdata; // From rx_stats_fifo0 of rx_stats_fifo.v
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wire rxsfifo_rempty; // From rx_stats_fifo0 of rx_stats_fifo.v
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wire [13:0] txsfifo_rdata; // From tx_stats_fifo0 of tx_stats_fifo.v
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wire txsfifo_rempty; // From tx_stats_fifo0 of tx_stats_fifo.v
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// End of automatics
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tx_stats_fifo tx_stats_fifo0(/*AUTOINST*/
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// Outputs
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.txsfifo_rdata (txsfifo_rdata[13:0]),
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.txsfifo_rempty (txsfifo_rempty),
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// Inputs
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.clk_xgmii_tx (clk_xgmii_tx),
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.reset_xgmii_tx_n (reset_xgmii_tx_n),
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.wb_clk_i (wb_clk_i),
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.wb_rst_i (wb_rst_i),
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.txsfifo_wdata (txsfifo_wdata[13:0]),
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.txsfifo_wen (txsfifo_wen));
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rx_stats_fifo rx_stats_fifo0(/*AUTOINST*/
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// Outputs
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.rxsfifo_rdata (rxsfifo_rdata[13:0]),
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.rxsfifo_rempty (rxsfifo_rempty),
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// Inputs
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.clk_xgmii_rx (clk_xgmii_rx),
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.reset_xgmii_rx_n (reset_xgmii_rx_n),
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.wb_clk_i (wb_clk_i),
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.wb_rst_i (wb_rst_i),
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.rxsfifo_wdata (rxsfifo_wdata[13:0]),
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.rxsfifo_wen (rxsfifo_wen));
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stats_sm stats_sm0(/*AUTOINST*/
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// Outputs
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.stats_tx_octets (stats_tx_octets[31:0]),
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.stats_tx_pkts (stats_tx_pkts[31:0]),
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.stats_rx_octets (stats_rx_octets[31:0]),
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.stats_rx_pkts (stats_rx_pkts[31:0]),
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// Inputs
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.wb_clk_i (wb_clk_i),
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.wb_rst_i (wb_rst_i),
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.txsfifo_rdata (txsfifo_rdata[13:0]),
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.txsfifo_rempty (txsfifo_rempty),
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.rxsfifo_rdata (rxsfifo_rdata[13:0]),
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.rxsfifo_rempty (rxsfifo_rempty),
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.clear_stats_tx_octets(clear_stats_tx_octets),
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.clear_stats_tx_pkts (clear_stats_tx_pkts),
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.clear_stats_rx_octets(clear_stats_rx_octets),
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.clear_stats_rx_pkts (clear_stats_rx_pkts));
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endmodule
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