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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [sync_clk_core.v] - Blame information for rev 12

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1 2 antanguay
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  File name "sync_clk_core.v"                                 ////
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////                                                              ////
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////  This file is part of the "10GE MAC" project                 ////
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////  http://www.opencores.org/cores/xge_mac/                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - A. Tanguay (antanguay@opencores.org)                  ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module sync_clk_core(/*AUTOARG*/
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  // Inputs
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  clk_xgmii_tx, reset_xgmii_tx_n
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  );
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input         clk_xgmii_tx;
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input         reset_xgmii_tx_n;
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//input         ctrl_tx_disable_padding;
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//output        ctrl_tx_disable_padding_ccr;
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/*AUTOREG*/
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/*AUTOWIRE*/
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//wire  [0:0]             sig_out;
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//assign {ctrl_tx_disable_padding_ccr} = sig_out;
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//meta_sync #(.DWIDTH (1)) meta_sync0 (
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//                      // Outputs
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//                      .out              (sig_out),
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//                      // Inputs
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//                      .clk              (clk_xgmii_tx),
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//                      .reset_n          (reset_xgmii_tx_n),
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//                      .in               ({
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//                                          ctrl_tx_disable_padding
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//                                         }));
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endmodule
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