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1 2 antanguay
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  File name "xge_mac.v"                                       ////
4
////                                                              ////
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////  This file is part of the "10GE MAC" project                 ////
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////  http://www.opencores.org/cores/xge_mac/                     ////
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////                                                              ////
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////  Author(s):                                                  ////
9
////      - A. Tanguay (antanguay@opencores.org)                  ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
37
 
38
 
39
`include "defines.v"
40
 
41
module xge_mac(/*AUTOARG*/
42
  // Outputs
43 12 antanguay
  xgmii_txd, xgmii_txc, wb_int_o, wb_dat_o, wb_ack_o, pkt_tx_full,
44
  pkt_rx_val, pkt_rx_sop, pkt_rx_mod, pkt_rx_err, pkt_rx_eop,
45
  pkt_rx_data, pkt_rx_avail,
46 2 antanguay
  // Inputs
47 12 antanguay
  xgmii_rxd, xgmii_rxc, wb_we_i, wb_stb_i, wb_rst_i, wb_dat_i,
48
  wb_cyc_i, wb_clk_i, wb_adr_i, reset_xgmii_tx_n, reset_xgmii_rx_n,
49
  reset_156m25_n, pkt_tx_val, pkt_tx_sop, pkt_tx_mod, pkt_tx_eop,
50 6 antanguay
  pkt_tx_data, pkt_rx_ren, clk_xgmii_tx, clk_xgmii_rx, clk_156m25
51 2 antanguay
  );
52
 
53
/*AUTOINPUT*/
54
// Beginning of automatic inputs (from unused autoinst inputs)
55
input                   clk_156m25;             // To rx_dq0 of rx_dequeue.v, ...
56
input                   clk_xgmii_rx;           // To rx_eq0 of rx_enqueue.v, ...
57
input                   clk_xgmii_tx;           // To tx_dq0 of tx_dequeue.v, ...
58
input                   pkt_rx_ren;             // To rx_dq0 of rx_dequeue.v
59
input [63:0]            pkt_tx_data;            // To tx_eq0 of tx_enqueue.v
60 6 antanguay
input                   pkt_tx_eop;             // To tx_eq0 of tx_enqueue.v
61
input [2:0]             pkt_tx_mod;             // To tx_eq0 of tx_enqueue.v
62 2 antanguay
input                   pkt_tx_sop;             // To tx_eq0 of tx_enqueue.v
63
input                   pkt_tx_val;             // To tx_eq0 of tx_enqueue.v
64
input                   reset_156m25_n;         // To rx_dq0 of rx_dequeue.v, ...
65
input                   reset_xgmii_rx_n;       // To rx_eq0 of rx_enqueue.v, ...
66
input                   reset_xgmii_tx_n;       // To tx_dq0 of tx_dequeue.v, ...
67
input [7:0]             wb_adr_i;               // To wishbone_if0 of wishbone_if.v
68
input                   wb_clk_i;               // To sync_clk_wb0 of sync_clk_wb.v, ...
69
input                   wb_cyc_i;               // To wishbone_if0 of wishbone_if.v
70
input [31:0]            wb_dat_i;               // To wishbone_if0 of wishbone_if.v
71
input                   wb_rst_i;               // To sync_clk_wb0 of sync_clk_wb.v, ...
72
input                   wb_stb_i;               // To wishbone_if0 of wishbone_if.v
73
input                   wb_we_i;                // To wishbone_if0 of wishbone_if.v
74
input [7:0]             xgmii_rxc;              // To rx_eq0 of rx_enqueue.v
75
input [63:0]            xgmii_rxd;              // To rx_eq0 of rx_enqueue.v
76
// End of automatics
77
 
78
/*AUTOOUTPUT*/
79
// Beginning of automatic outputs (from unused autoinst outputs)
80
output                  pkt_rx_avail;           // From rx_dq0 of rx_dequeue.v
81
output [63:0]           pkt_rx_data;            // From rx_dq0 of rx_dequeue.v
82 6 antanguay
output                  pkt_rx_eop;             // From rx_dq0 of rx_dequeue.v
83 2 antanguay
output                  pkt_rx_err;             // From rx_dq0 of rx_dequeue.v
84 6 antanguay
output [2:0]            pkt_rx_mod;             // From rx_dq0 of rx_dequeue.v
85 2 antanguay
output                  pkt_rx_sop;             // From rx_dq0 of rx_dequeue.v
86
output                  pkt_rx_val;             // From rx_dq0 of rx_dequeue.v
87
output                  pkt_tx_full;            // From tx_eq0 of tx_enqueue.v
88
output                  wb_ack_o;               // From wishbone_if0 of wishbone_if.v
89
output [31:0]           wb_dat_o;               // From wishbone_if0 of wishbone_if.v
90
output                  wb_int_o;               // From wishbone_if0 of wishbone_if.v
91
output [7:0]            xgmii_txc;              // From tx_dq0 of tx_dequeue.v
92
output [63:0]           xgmii_txd;              // From tx_dq0 of tx_dequeue.v
93
// End of automatics
94
 
95
/*AUTOWIRE*/
96
// Beginning of automatic wires (for undeclared instantiated-module outputs)
97
wire                    ctrl_tx_enable;         // From wishbone_if0 of wishbone_if.v
98
wire                    ctrl_tx_enable_ctx;     // From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v
99
wire [1:0]              local_fault_msg_det;    // From rx_eq0 of rx_enqueue.v
100
wire [1:0]              remote_fault_msg_det;   // From rx_eq0 of rx_enqueue.v
101
wire                    rxdfifo_ralmost_empty;  // From rx_data_fifo0 of rx_data_fifo.v
102
wire [63:0]             rxdfifo_rdata;          // From rx_data_fifo0 of rx_data_fifo.v
103
wire                    rxdfifo_rempty;         // From rx_data_fifo0 of rx_data_fifo.v
104
wire                    rxdfifo_ren;            // From rx_dq0 of rx_dequeue.v
105
wire [7:0]              rxdfifo_rstatus;        // From rx_data_fifo0 of rx_data_fifo.v
106
wire [63:0]             rxdfifo_wdata;          // From rx_eq0 of rx_enqueue.v
107
wire                    rxdfifo_wen;            // From rx_eq0 of rx_enqueue.v
108
wire                    rxdfifo_wfull;          // From rx_data_fifo0 of rx_data_fifo.v
109
wire [7:0]              rxdfifo_wstatus;        // From rx_eq0 of rx_enqueue.v
110
wire                    rxhfifo_ralmost_empty;  // From rx_hold_fifo0 of rx_hold_fifo.v
111
wire [63:0]             rxhfifo_rdata;          // From rx_hold_fifo0 of rx_hold_fifo.v
112
wire                    rxhfifo_rempty;         // From rx_hold_fifo0 of rx_hold_fifo.v
113
wire                    rxhfifo_ren;            // From rx_eq0 of rx_enqueue.v
114
wire [7:0]              rxhfifo_rstatus;        // From rx_hold_fifo0 of rx_hold_fifo.v
115
wire [63:0]             rxhfifo_wdata;          // From rx_eq0 of rx_enqueue.v
116
wire                    rxhfifo_wen;            // From rx_eq0 of rx_enqueue.v
117
wire [7:0]              rxhfifo_wstatus;        // From rx_eq0 of rx_enqueue.v
118
wire                    status_crc_error;       // From sync_clk_wb0 of sync_clk_wb.v
119
wire                    status_crc_error_tog;   // From rx_eq0 of rx_enqueue.v
120
wire                    status_fragment_error;  // From sync_clk_wb0 of sync_clk_wb.v
121
wire                    status_fragment_error_tog;// From rx_eq0 of rx_enqueue.v
122
wire                    status_local_fault;     // From sync_clk_wb0 of sync_clk_wb.v
123
wire                    status_local_fault_crx; // From fault_sm0 of fault_sm.v
124
wire                    status_local_fault_ctx; // From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v
125
wire                    status_pause_frame_rx;  // From sync_clk_wb0 of sync_clk_wb.v
126
wire                    status_pause_frame_rx_tog;// From rx_eq0 of rx_enqueue.v
127
wire                    status_remote_fault;    // From sync_clk_wb0 of sync_clk_wb.v
128
wire                    status_remote_fault_crx;// From fault_sm0 of fault_sm.v
129
wire                    status_remote_fault_ctx;// From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v
130
wire                    status_rxdfifo_ovflow;  // From sync_clk_wb0 of sync_clk_wb.v
131
wire                    status_rxdfifo_ovflow_tog;// From rx_eq0 of rx_enqueue.v
132
wire                    status_rxdfifo_udflow;  // From sync_clk_wb0 of sync_clk_wb.v
133
wire                    status_rxdfifo_udflow_tog;// From rx_dq0 of rx_dequeue.v
134
wire                    status_txdfifo_ovflow;  // From sync_clk_wb0 of sync_clk_wb.v
135
wire                    status_txdfifo_ovflow_tog;// From tx_eq0 of tx_enqueue.v
136
wire                    status_txdfifo_udflow;  // From sync_clk_wb0 of sync_clk_wb.v
137
wire                    status_txdfifo_udflow_tog;// From tx_dq0 of tx_dequeue.v
138
wire                    txdfifo_ralmost_empty;  // From tx_data_fifo0 of tx_data_fifo.v
139
wire [63:0]             txdfifo_rdata;          // From tx_data_fifo0 of tx_data_fifo.v
140
wire                    txdfifo_rempty;         // From tx_data_fifo0 of tx_data_fifo.v
141
wire                    txdfifo_ren;            // From tx_dq0 of tx_dequeue.v
142
wire [7:0]              txdfifo_rstatus;        // From tx_data_fifo0 of tx_data_fifo.v
143
wire                    txdfifo_walmost_full;   // From tx_data_fifo0 of tx_data_fifo.v
144
wire [63:0]             txdfifo_wdata;          // From tx_eq0 of tx_enqueue.v
145
wire                    txdfifo_wen;            // From tx_eq0 of tx_enqueue.v
146
wire                    txdfifo_wfull;          // From tx_data_fifo0 of tx_data_fifo.v
147
wire [7:0]              txdfifo_wstatus;        // From tx_eq0 of tx_enqueue.v
148
wire                    txhfifo_ralmost_empty;  // From tx_hold_fifo0 of tx_hold_fifo.v
149
wire [63:0]             txhfifo_rdata;          // From tx_hold_fifo0 of tx_hold_fifo.v
150
wire                    txhfifo_rempty;         // From tx_hold_fifo0 of tx_hold_fifo.v
151
wire                    txhfifo_ren;            // From tx_dq0 of tx_dequeue.v
152
wire [7:0]              txhfifo_rstatus;        // From tx_hold_fifo0 of tx_hold_fifo.v
153
wire                    txhfifo_walmost_full;   // From tx_hold_fifo0 of tx_hold_fifo.v
154
wire [63:0]             txhfifo_wdata;          // From tx_dq0 of tx_dequeue.v
155
wire                    txhfifo_wen;            // From tx_dq0 of tx_dequeue.v
156
wire                    txhfifo_wfull;          // From tx_hold_fifo0 of tx_hold_fifo.v
157
wire [7:0]              txhfifo_wstatus;        // From tx_dq0 of tx_dequeue.v
158
// End of automatics
159
 
160
rx_enqueue rx_eq0(/*AUTOINST*/
161
                  // Outputs
162
                  .rxdfifo_wdata        (rxdfifo_wdata[63:0]),
163
                  .rxdfifo_wstatus      (rxdfifo_wstatus[7:0]),
164
                  .rxdfifo_wen          (rxdfifo_wen),
165
                  .rxhfifo_ren          (rxhfifo_ren),
166
                  .rxhfifo_wdata        (rxhfifo_wdata[63:0]),
167
                  .rxhfifo_wstatus      (rxhfifo_wstatus[7:0]),
168
                  .rxhfifo_wen          (rxhfifo_wen),
169
                  .local_fault_msg_det  (local_fault_msg_det[1:0]),
170
                  .remote_fault_msg_det (remote_fault_msg_det[1:0]),
171
                  .status_crc_error_tog (status_crc_error_tog),
172
                  .status_fragment_error_tog(status_fragment_error_tog),
173
                  .status_rxdfifo_ovflow_tog(status_rxdfifo_ovflow_tog),
174
                  .status_pause_frame_rx_tog(status_pause_frame_rx_tog),
175
                  // Inputs
176
                  .clk_xgmii_rx         (clk_xgmii_rx),
177
                  .reset_xgmii_rx_n     (reset_xgmii_rx_n),
178
                  .xgmii_rxd            (xgmii_rxd[63:0]),
179
                  .xgmii_rxc            (xgmii_rxc[7:0]),
180
                  .rxdfifo_wfull        (rxdfifo_wfull),
181
                  .rxhfifo_rdata        (rxhfifo_rdata[63:0]),
182
                  .rxhfifo_rstatus      (rxhfifo_rstatus[7:0]),
183
                  .rxhfifo_rempty       (rxhfifo_rempty),
184
                  .rxhfifo_ralmost_empty(rxhfifo_ralmost_empty));
185
 
186
rx_dequeue rx_dq0(/*AUTOINST*/
187
                  // Outputs
188
                  .rxdfifo_ren          (rxdfifo_ren),
189
                  .pkt_rx_data          (pkt_rx_data[63:0]),
190
                  .pkt_rx_val           (pkt_rx_val),
191
                  .pkt_rx_sop           (pkt_rx_sop),
192 6 antanguay
                  .pkt_rx_eop           (pkt_rx_eop),
193 2 antanguay
                  .pkt_rx_err           (pkt_rx_err),
194 6 antanguay
                  .pkt_rx_mod           (pkt_rx_mod[2:0]),
195 2 antanguay
                  .pkt_rx_avail         (pkt_rx_avail),
196
                  .status_rxdfifo_udflow_tog(status_rxdfifo_udflow_tog),
197
                  // Inputs
198
                  .clk_156m25           (clk_156m25),
199
                  .reset_156m25_n       (reset_156m25_n),
200
                  .rxdfifo_rdata        (rxdfifo_rdata[63:0]),
201
                  .rxdfifo_rstatus      (rxdfifo_rstatus[7:0]),
202
                  .rxdfifo_rempty       (rxdfifo_rempty),
203
                  .rxdfifo_ralmost_empty(rxdfifo_ralmost_empty),
204
                  .pkt_rx_ren           (pkt_rx_ren));
205 20 antanguay
 
206 2 antanguay
rx_data_fifo rx_data_fifo0(/*AUTOINST*/
207
                           // Outputs
208 12 antanguay
                           .rxdfifo_wfull       (rxdfifo_wfull),
209
                           .rxdfifo_rdata       (rxdfifo_rdata[63:0]),
210
                           .rxdfifo_rstatus     (rxdfifo_rstatus[7:0]),
211
                           .rxdfifo_rempty      (rxdfifo_rempty),
212 2 antanguay
                           .rxdfifo_ralmost_empty(rxdfifo_ralmost_empty),
213
                           // Inputs
214 12 antanguay
                           .clk_xgmii_rx        (clk_xgmii_rx),
215
                           .clk_156m25          (clk_156m25),
216
                           .reset_xgmii_rx_n    (reset_xgmii_rx_n),
217
                           .reset_156m25_n      (reset_156m25_n),
218
                           .rxdfifo_wdata       (rxdfifo_wdata[63:0]),
219
                           .rxdfifo_wstatus     (rxdfifo_wstatus[7:0]),
220
                           .rxdfifo_wen         (rxdfifo_wen),
221
                           .rxdfifo_ren         (rxdfifo_ren));
222 2 antanguay
 
223
rx_hold_fifo rx_hold_fifo0(/*AUTOINST*/
224
                           // Outputs
225 12 antanguay
                           .rxhfifo_rdata       (rxhfifo_rdata[63:0]),
226
                           .rxhfifo_rstatus     (rxhfifo_rstatus[7:0]),
227
                           .rxhfifo_rempty      (rxhfifo_rempty),
228 2 antanguay
                           .rxhfifo_ralmost_empty(rxhfifo_ralmost_empty),
229
                           // Inputs
230 12 antanguay
                           .clk_xgmii_rx        (clk_xgmii_rx),
231
                           .reset_xgmii_rx_n    (reset_xgmii_rx_n),
232
                           .rxhfifo_wdata       (rxhfifo_wdata[63:0]),
233
                           .rxhfifo_wstatus     (rxhfifo_wstatus[7:0]),
234
                           .rxhfifo_wen         (rxhfifo_wen),
235
                           .rxhfifo_ren         (rxhfifo_ren));
236 2 antanguay
 
237
tx_enqueue tx_eq0 (/*AUTOINST*/
238
                   // Outputs
239
                   .pkt_tx_full         (pkt_tx_full),
240
                   .txdfifo_wdata       (txdfifo_wdata[63:0]),
241
                   .txdfifo_wstatus     (txdfifo_wstatus[7:0]),
242
                   .txdfifo_wen         (txdfifo_wen),
243
                   .status_txdfifo_ovflow_tog(status_txdfifo_ovflow_tog),
244
                   // Inputs
245
                   .clk_156m25          (clk_156m25),
246
                   .reset_156m25_n      (reset_156m25_n),
247
                   .pkt_tx_data         (pkt_tx_data[63:0]),
248
                   .pkt_tx_val          (pkt_tx_val),
249
                   .pkt_tx_sop          (pkt_tx_sop),
250 6 antanguay
                   .pkt_tx_eop          (pkt_tx_eop),
251
                   .pkt_tx_mod          (pkt_tx_mod[2:0]),
252 2 antanguay
                   .txdfifo_wfull       (txdfifo_wfull),
253
                   .txdfifo_walmost_full(txdfifo_walmost_full));
254
 
255
tx_dequeue tx_dq0(/*AUTOINST*/
256
                  // Outputs
257
                  .txdfifo_ren          (txdfifo_ren),
258
                  .txhfifo_ren          (txhfifo_ren),
259
                  .txhfifo_wdata        (txhfifo_wdata[63:0]),
260
                  .txhfifo_wstatus      (txhfifo_wstatus[7:0]),
261
                  .txhfifo_wen          (txhfifo_wen),
262
                  .xgmii_txd            (xgmii_txd[63:0]),
263
                  .xgmii_txc            (xgmii_txc[7:0]),
264
                  .status_txdfifo_udflow_tog(status_txdfifo_udflow_tog),
265
                  // Inputs
266
                  .clk_xgmii_tx         (clk_xgmii_tx),
267
                  .reset_xgmii_tx_n     (reset_xgmii_tx_n),
268
                  .ctrl_tx_enable_ctx   (ctrl_tx_enable_ctx),
269
                  .status_local_fault_ctx(status_local_fault_ctx),
270
                  .status_remote_fault_ctx(status_remote_fault_ctx),
271
                  .txdfifo_rdata        (txdfifo_rdata[63:0]),
272
                  .txdfifo_rstatus      (txdfifo_rstatus[7:0]),
273
                  .txdfifo_rempty       (txdfifo_rempty),
274
                  .txdfifo_ralmost_empty(txdfifo_ralmost_empty),
275
                  .txhfifo_rdata        (txhfifo_rdata[63:0]),
276
                  .txhfifo_rstatus      (txhfifo_rstatus[7:0]),
277
                  .txhfifo_rempty       (txhfifo_rempty),
278
                  .txhfifo_ralmost_empty(txhfifo_ralmost_empty),
279
                  .txhfifo_wfull        (txhfifo_wfull),
280
                  .txhfifo_walmost_full (txhfifo_walmost_full));
281
 
282
tx_data_fifo tx_data_fifo0(/*AUTOINST*/
283
                           // Outputs
284 12 antanguay
                           .txdfifo_wfull       (txdfifo_wfull),
285 2 antanguay
                           .txdfifo_walmost_full(txdfifo_walmost_full),
286 12 antanguay
                           .txdfifo_rdata       (txdfifo_rdata[63:0]),
287
                           .txdfifo_rstatus     (txdfifo_rstatus[7:0]),
288
                           .txdfifo_rempty      (txdfifo_rempty),
289 2 antanguay
                           .txdfifo_ralmost_empty(txdfifo_ralmost_empty),
290
                           // Inputs
291 12 antanguay
                           .clk_xgmii_tx        (clk_xgmii_tx),
292
                           .clk_156m25          (clk_156m25),
293
                           .reset_xgmii_tx_n    (reset_xgmii_tx_n),
294
                           .reset_156m25_n      (reset_156m25_n),
295
                           .txdfifo_wdata       (txdfifo_wdata[63:0]),
296
                           .txdfifo_wstatus     (txdfifo_wstatus[7:0]),
297
                           .txdfifo_wen         (txdfifo_wen),
298
                           .txdfifo_ren         (txdfifo_ren));
299 2 antanguay
 
300
tx_hold_fifo tx_hold_fifo0(/*AUTOINST*/
301
                           // Outputs
302 12 antanguay
                           .txhfifo_wfull       (txhfifo_wfull),
303 2 antanguay
                           .txhfifo_walmost_full(txhfifo_walmost_full),
304 12 antanguay
                           .txhfifo_rdata       (txhfifo_rdata[63:0]),
305
                           .txhfifo_rstatus     (txhfifo_rstatus[7:0]),
306
                           .txhfifo_rempty      (txhfifo_rempty),
307 2 antanguay
                           .txhfifo_ralmost_empty(txhfifo_ralmost_empty),
308
                           // Inputs
309 12 antanguay
                           .clk_xgmii_tx        (clk_xgmii_tx),
310
                           .reset_xgmii_tx_n    (reset_xgmii_tx_n),
311
                           .txhfifo_wdata       (txhfifo_wdata[63:0]),
312
                           .txhfifo_wstatus     (txhfifo_wstatus[7:0]),
313
                           .txhfifo_wen         (txhfifo_wen),
314
                           .txhfifo_ren         (txhfifo_ren));
315 2 antanguay
 
316
fault_sm fault_sm0(/*AUTOINST*/
317
                   // Outputs
318
                   .status_local_fault_crx(status_local_fault_crx),
319
                   .status_remote_fault_crx(status_remote_fault_crx),
320
                   // Inputs
321
                   .clk_xgmii_rx        (clk_xgmii_rx),
322
                   .reset_xgmii_rx_n    (reset_xgmii_rx_n),
323
                   .local_fault_msg_det (local_fault_msg_det[1:0]),
324
                   .remote_fault_msg_det(remote_fault_msg_det[1:0]));
325
 
326
sync_clk_wb sync_clk_wb0(/*AUTOINST*/
327
                         // Outputs
328 12 antanguay
                         .status_crc_error      (status_crc_error),
329
                         .status_fragment_error (status_fragment_error),
330
                         .status_txdfifo_ovflow (status_txdfifo_ovflow),
331
                         .status_txdfifo_udflow (status_txdfifo_udflow),
332
                         .status_rxdfifo_ovflow (status_rxdfifo_ovflow),
333
                         .status_rxdfifo_udflow (status_rxdfifo_udflow),
334
                         .status_pause_frame_rx (status_pause_frame_rx),
335
                         .status_local_fault    (status_local_fault),
336
                         .status_remote_fault   (status_remote_fault),
337 2 antanguay
                         // Inputs
338 12 antanguay
                         .wb_clk_i              (wb_clk_i),
339
                         .wb_rst_i              (wb_rst_i),
340
                         .status_crc_error_tog  (status_crc_error_tog),
341 2 antanguay
                         .status_fragment_error_tog(status_fragment_error_tog),
342
                         .status_txdfifo_ovflow_tog(status_txdfifo_ovflow_tog),
343
                         .status_txdfifo_udflow_tog(status_txdfifo_udflow_tog),
344
                         .status_rxdfifo_ovflow_tog(status_rxdfifo_ovflow_tog),
345
                         .status_rxdfifo_udflow_tog(status_rxdfifo_udflow_tog),
346
                         .status_pause_frame_rx_tog(status_pause_frame_rx_tog),
347
                         .status_local_fault_crx(status_local_fault_crx),
348
                         .status_remote_fault_crx(status_remote_fault_crx));
349
 
350
sync_clk_xgmii_tx sync_clk_xgmii_tx0(/*AUTOINST*/
351
                                     // Outputs
352
                                     .ctrl_tx_enable_ctx(ctrl_tx_enable_ctx),
353
                                     .status_local_fault_ctx(status_local_fault_ctx),
354
                                     .status_remote_fault_ctx(status_remote_fault_ctx),
355
                                     // Inputs
356 12 antanguay
                                     .clk_xgmii_tx      (clk_xgmii_tx),
357
                                     .reset_xgmii_tx_n  (reset_xgmii_tx_n),
358
                                     .ctrl_tx_enable    (ctrl_tx_enable),
359 2 antanguay
                                     .status_local_fault_crx(status_local_fault_crx),
360
                                     .status_remote_fault_crx(status_remote_fault_crx));
361
 
362 20 antanguay
//sync_clk_core sync_clk_core0(/*AUTOINST*/
363
//                             // Inputs
364
//                             .clk_xgmii_tx      (clk_xgmii_tx),
365
//                             .reset_xgmii_tx_n  (reset_xgmii_tx_n));
366 2 antanguay
 
367
wishbone_if wishbone_if0(/*AUTOINST*/
368
                         // Outputs
369 12 antanguay
                         .wb_dat_o              (wb_dat_o[31:0]),
370
                         .wb_ack_o              (wb_ack_o),
371
                         .wb_int_o              (wb_int_o),
372
                         .ctrl_tx_enable        (ctrl_tx_enable),
373 2 antanguay
                         // Inputs
374 12 antanguay
                         .wb_clk_i              (wb_clk_i),
375
                         .wb_rst_i              (wb_rst_i),
376
                         .wb_adr_i              (wb_adr_i[7:0]),
377
                         .wb_dat_i              (wb_dat_i[31:0]),
378
                         .wb_we_i               (wb_we_i),
379
                         .wb_stb_i              (wb_stb_i),
380
                         .wb_cyc_i              (wb_cyc_i),
381
                         .status_crc_error      (status_crc_error),
382
                         .status_fragment_error (status_fragment_error),
383
                         .status_txdfifo_ovflow (status_txdfifo_ovflow),
384
                         .status_txdfifo_udflow (status_txdfifo_udflow),
385
                         .status_rxdfifo_ovflow (status_rxdfifo_ovflow),
386
                         .status_rxdfifo_udflow (status_rxdfifo_udflow),
387
                         .status_pause_frame_rx (status_pause_frame_rx),
388
                         .status_local_fault    (status_local_fault),
389
                         .status_remote_fault   (status_remote_fault));
390 2 antanguay
 
391
endmodule

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