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[/] [xge_mac/] [trunk/] [sim/] [proto_systemverilog/] [irunScript] - Blame information for rev 22

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Line No. Rev Author Line
1 22 antanguay
irun -timescale 1ps/1ps -override_timescale ../../rtl/verilog/*.v +incdir+../../rtl/include ../../testbench/verilog/tb_xge_mac.sv

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