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[/] [xge_mac/] [trunk/] [sim/] [proto_systemverilog/] [runsim] - Blame information for rev 26

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vcs +vcs+lic+wait -sverilog -R -l vcs.log \
-override_timescale=1ps/1ps \
../../rtl/verilog/*.v \
+incdir+../../rtl/include \
../../testbench/verilog/tb_xge_mac.sv

Line No.	Rev	Author	Line
1	22	antanguay	`vcs +vcs+lic+wait -sverilog -R -l vcs.log \`
2			`-override_timescale=1ps/1ps \`
3			`../../rtl/verilog/*.v \`
4			`+incdir+../../rtl/include \`
5			`../../testbench/verilog/tb_xge_mac.sv`

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Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [sim/] [proto_systemverilog/] [runsim] - Blame information for rev 26