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Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [sim/] [verilog/] [sim.do] - Blame information for rev 12

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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/fault_sm.v
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/generic_mem_small.v
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/generic_mem_medium.v
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/generic_fifo_ctrl.v
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/generic_fifo.v
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/meta_sync.v
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/meta_sync_single.v
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/rx_hold_fifo.v
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/rx_data_fifo.v
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/rx_dequeue.v
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/rx_enqueue.v
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/sync_clk_core.v
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/sync_clk_wb.v
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/sync_clk_xgmii_tx.v
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_hold_fifo.v
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_data_fifo.v
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_dequeue.v
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_enqueue.v
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/wishbone_if.v
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/xge_mac.v
 
 
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../tbench/verilog/tb_xge_mac.v
 
 
 
vsim -voptargs="+acc" work.tb
 
add wave sim:/tb/*
 
add wave -divider
 
add wave sim:/tb/dut/*
 
add wave -divider
 
add wave sim:/tb/dut/rx_eq0/*
 
add wave -divider
 
add wave sim:/tb/dut/rx_data_fifo0/*
 
add wave -divider
 
add wave sim:/tb/dut/rx_dq0/*
 
add wave -divider
add wave -divider
add wave -divider
 
add wave sim:/tb/dut/tx_eq0/*
 
add wave -divider
 
add wave sim:/tb/dut/tx_data_fifo0/*
 
add wave -divider
 
add wave sim:/tb/dut/tx_dq0/*
 
add wave -divider
 
add wave sim:/tb/dut/fault_sm0/*
 
add wave -divider
 
add wave sim:/tb/dut/wishbone_if0/*
 
#run 1000ns

Line No.	Rev	Author	Line
1	2	antanguay
2
3	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/fault_sm.v`
4	2	antanguay
5	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/generic_mem_small.v`
6	2	antanguay
7	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/generic_mem_medium.v`
8	2	antanguay
9	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/generic_fifo_ctrl.v`
10	2	antanguay
11	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/generic_fifo.v`
12	2	antanguay
13	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/meta_sync.v`
14	2	antanguay
15	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/meta_sync_single.v`
16	2	antanguay
17	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/rx_hold_fifo.v`
18	2	antanguay
19	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/rx_data_fifo.v`
20	2	antanguay
21	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/rx_dequeue.v`
22	2	antanguay
23	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/rx_enqueue.v`
24	2	antanguay
25	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/sync_clk_core.v`
26	2	antanguay
27	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/sync_clk_wb.v`
28	2	antanguay
29	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/sync_clk_xgmii_tx.v`
30	2	antanguay
31	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_hold_fifo.v`
32	2	antanguay
33	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_data_fifo.v`
34	2	antanguay
35	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_dequeue.v`
36	2	antanguay
37	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_enqueue.v`
38	2	antanguay
39	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/wishbone_if.v`
40	2	antanguay
41	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/xge_mac.v`
42	2	antanguay
43
44
45	5	antanguay	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../tbench/verilog/tb_xge_mac.v`
46
47
48
49	2	antanguay	`vsim -voptargs="+acc" work.tb`
50
51			`add wave sim:/tb/*`
52
53			`add wave -divider`
54
55			`add wave sim:/tb/dut/*`
56
57			`add wave -divider`
58
59			`add wave sim:/tb/dut/rx_eq0/*`
60
61			`add wave -divider`
62
63			`add wave sim:/tb/dut/rx_data_fifo0/*`
64
65			`add wave -divider`
66
67			`add wave sim:/tb/dut/rx_dq0/*`
68
69			`add wave -divider`
70			`add wave -divider`
71			`add wave -divider`
72
73			`add wave sim:/tb/dut/tx_eq0/*`
74
75			`add wave -divider`
76
77			`add wave sim:/tb/dut/tx_data_fifo0/*`
78
79			`add wave -divider`
80
81			`add wave sim:/tb/dut/tx_dq0/*`
82
83			`add wave -divider`
84
85			`add wave sim:/tb/dut/fault_sm0/*`
86
87			`add wave -divider`
88
89			`add wave sim:/tb/dut/wishbone_if0/*`
90
91			`#run 1000ns`

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Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [sim/] [verilog/] [sim.do] - Blame information for rev 12