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antanguay |
/**
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* Interface file for 10 GE MAC Core.
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* Takes all clocks as input and all clocks are created from single clock source in testbench
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* @file: macCoreInterface.sv
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* @author: Pratik Mahajan
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* @par Contact: pratik@e-pigeonpost.com
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* @par Company: UCSC extension (Systemverilog for advanced verification SV1896) course
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*
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* @version: $LastChangedRevision$
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* @par Last Changed Date:
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* $LastChangedDate$
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* @par Last Changed By
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* $LastChangedBy$
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*/
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/**
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* 10GE MAC Core interface.
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* @param clkWishboneInterface : clock for wishbone interface 30 - 156 MHz -- input to interface logic
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* @param clkTxRxInterface : clock for simple Tx-Rx interface 156.25 MHz -- input to interface logic
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* @param clkXGMIIInterfaceRx : clock for XGMII physical layer Rx interface 156.25 MHz -- input to interface logic
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* @param clkXGMIIInterfaceTx : clock for XGMII physical later Tx interface 156.25 MHz -- input to interface logic
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*/
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interface macCoreInterface (input bit clkWishboneInterface,
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input bit clkTxRxInterface,
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input bit clkXGMIIInterfaceRx,
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input bit clkXGMIIInterfaceTx
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);
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// Reset signals used in design
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bit rstWishboneInterface; ///< Wishbone interface reset signal -- de-assertion synchronous to clkWishboneInterface
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bit rstTxRxInterface_n; ///< Simple Tx-Rx interface reset signal -- de-assertion synchronous to clkTxRxInterface ACTIVE LOW
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bit rstXGMIIInterfaceRx_n; ///< XGMII physical layer Rx interface reset signal -- de-assertion synchronous to clkXGMIIInterfaceRx ACTIVE LOW
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bit rstXGMIIInterfaceTx_n; ///< XGMII physical later Tx interface reset signal -- de-assertion synchronous to clkXGMIIInterfaceTx ACTIVE LOW
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// Packet receive interface signals
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bit receiveReadEnable; ///< Input to Core (outoput of test) asserted when packet is available in receive FIFO
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bit receiveAvailable; ///< Output from Core indicates packet is available for reading in receive FIFO
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bit [63:0] receivedData; ///< Output from Core represents a packet data in little endian format
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bit receiveEndOfPacket; ///< Output from Core asserted when last word of packet is read form receive FIFO
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bit receiveValid; ///< Output from Core asserted a cycle after readEnable represents a valid data on bus
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bit receiveStartOfPacket; ///< Output from Core represents first word of packet is on the bus
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bit [2:0] receivePacketLengthModulus; ///< Output from Core updated with End of packet to represent valid bytes during last word
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bit receiveError; ///< Output from Core represents current packet is bad mainly due to CRC errors
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// Packet transmit interface signals
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bit [63:0] transmitData; ///< Input to Core represents packet data to be transmitted in Little-Endian format
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bit transmitValid; ///< Input to Core asserted for each valid data transfer to MAC Core
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bit transmitStartOfPacket; ///< Input to Core must be asserted during first word of packet to Core
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bit transmitEndOfPacket; ///< Input to Core must be asserted during last word of packet to Core
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bit [2:0] transmitPacketLengthModulus;///< Input to Core should be valid during End Of Packet during last word and represents valid bytes
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bit transmitFIFOFull; ///< Output from Core represents transmit FIFO is about to be full
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// XGMII receive interface signals
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bit [7:0] xgmiiReceiveControl; ///< Input to Core - each bit corresponds to type of byte of frame; 0 - byte is data, 1 - byte is control char
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bit [63:0] xgmiiReceiveData; ///< Input to Core - represents data on XGMII interface to be received by Core (can be broken in 32 bits)
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// XGMII transmit interface signals
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bit [7:0] xgmiiTransmitControl; ///< Output from Core - each bit corresponds to type of byte of frame; 0 - byte is data, 1 - byte is control char
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bit [63:0] xgmiiTransmitData; ///< Output from Core - represents data on XGMII interface to be transmitted by Core (can be broken in 32 bits)
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// Wishbone interface signals -- won't be used for current specification requirements
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bit [7:0] wishboneInputAddress;
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bit wishboneCycle;
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bit [31:0] wishboneInputData;
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bit wishboneStrobe;
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bit wishboneWriteEnable;
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bit wishboneAck;
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bit [31:0] wishboneOutputData;
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bit wishboneInterrupt;
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// Put XGMII interface in loopback mode --- do it in testbench if you can just connect them to each other
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/* always_comb begin
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xgmiiReceiveControl = xgmiiTransmitControl;
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xgmiiReceiveData = xgmiiTransmitData;
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end
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*/
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/**
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* Clocking block mainly for testcase
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* Resets are used as outputs in clocking block -- to make sure they are de-asserted on clock edges
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* may need specific testcase to test asynchronous resets
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* @param clkTxRxInterface: clock to be used for clocking block
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*/
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clocking clockingTxRx @(posedge clkTxRxInterface);
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// Using default delays
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default output #1000;
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// receive interface direction
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input receiveAvailable;
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input receivedData;
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input receiveEndOfPacket;
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input receiveValid;
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input receiveStartOfPacket;
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input receivePacketLengthModulus;
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input receiveError;
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output receiveReadEnable;
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// transmit interface direction
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output transmitData;
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output transmitValid;
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output transmitStartOfPacket;
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output transmitEndOfPacket;
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output transmitPacketLengthModulus;
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input transmitFIFOFull;
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output rstTxRxInterface_n;
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output rstWishboneInterface; // not necessary but doesn't matter as we need to take care of it
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endclocking // clockingTxRx
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clocking clockingXGMIIRx @(posedge clkXGMIIInterfaceRx);
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output xgmiiReceiveControl;
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output xgmiiReceiveData;
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output rstXGMIIInterfaceRx_n;
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endclocking // clockingXGMIIRx
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clocking clockingXGMIITx @(posedge clkXGMIIInterfaceTx);
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input xgmiiTransmitControl;
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input xgmiiTransmitData;
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output rstXGMIIInterfaceTx_n;
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endclocking // clockingXGMIITx
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// Avoiding modports for 10GE MAC Core and Wishbone as functionality is not really required at this point of time
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// However for complete environment it can be extended to include all interfaces
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modport TESTMOD (clocking clockingTxRx, clocking clockingXGMIIRx, clocking clockingXGMIITx);
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endinterface // macCoreInterface
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