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antanguay |
/**
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* Testbench file for verification environment of 10GE MAC Core.
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* @file: testbench.sv
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* @author: Pratik Mahajan
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* @par Contact: pratik@e-pigeonpost.com
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* @par Company: UCSC (SV 1896 Systemverilog for Advanced verification course)
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*
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* @version: $LastChangedRevision$
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* @par Last Changed Date:
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* $LastChangedDate$
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* @par Last Changed By:
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* $LastChangedBy$
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*/
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/**
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* top block (module) mainly to instantiate all programs/modules and to generate clocks.
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* Clocks are generated as per specification requirements:
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* Wishbone interface clock: 30 - 156MHz
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* Simple Tx-Rx interface clock: 156.25 MHz
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* XGMII Rx interface clock: 156.25 MHz
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* XGMII Tx interface clock: 156.25 MHz
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*
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* This clock generator will create Wishbone interface clock at 78.125 MHz (cause it has
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* clock time of half of 156.25)
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* @param: clkWishboneInterface (wishbone interface clock or main clock, will be used to generate all other clocks)
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* @param: clkSimpleTxRxInterface
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* @param: clkXGMIIInterfaceRx
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* @param: clkXGMIIInterfaceTx
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*/
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module top ();
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bit clkWishboneInterface;
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bit clkSimpleTxRxInterface;
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bit clkXGMIIInterfaceRx;
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bit clkXGMIIInterfaceTx;
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initial begin
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clkWishboneInterface = 0;
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clkSimpleTxRxInterface = 0;
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clkXGMIIInterfaceRx = 0;
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clkXGMIIInterfaceTx = 0;
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end
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initial forever #1600 clkWishboneInterface = ~clkWishboneInterface;
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// Creating all other clocks from wishbone clock to make it look better and easily
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// portable (arguable) However wishbone interface clock looses flexibility of having
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// any value to create 30-156MHz range
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// Following block can be modified to have each clock generated independently
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// and having more flexibility.
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always @(posedge clkWishboneInterface) begin
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// initial forever #3200 begin
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clkSimpleTxRxInterface = ~clkSimpleTxRxInterface;
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clkXGMIIInterfaceRx = ~clkXGMIIInterfaceRx;
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clkXGMIIInterfaceTx = ~clkXGMIIInterfaceTx;
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end
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initial begin
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$dumpfile ("toTest.dump");
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$dumpvars (0, top);
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end
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// Instantiation of Interface
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macCoreInterface instInterface ( .clkWishboneInterface (clkWishboneInterface),
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.clkTxRxInterface (clkSimpleTxRxInterface),
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.clkXGMIIInterfaceRx (clkXGMIIInterfaceRx),
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.clkXGMIIInterfaceTx (clkXGMIIInterfaceTx)
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);
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// Instantiation of MAC DUT
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xge_mac instMAC ( // Simple Tx-Rx interface signals
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.clk_156m25 (instInterface.clkTxRxInterface),
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.pkt_rx_ren (instInterface.receiveReadEnable),
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.pkt_rx_avail (instInterface.receiveAvailable),
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.pkt_rx_data (instInterface.receivedData),
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.pkt_rx_eop (instInterface.receiveEndOfPacket),
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.pkt_rx_err (instInterface.receiveError),
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.pkt_rx_mod (instInterface.receivePacketLengthModulus),
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.pkt_rx_sop (instInterface.receiveStartOfPacket),
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.pkt_rx_val (instInterface.receiveValid),
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.pkt_tx_data (instInterface.transmitData),
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.pkt_tx_eop (instInterface.transmitEndOfPacket),
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.pkt_tx_mod (instInterface.transmitPacketLengthModulus),
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.pkt_tx_sop (instInterface.transmitStartOfPacket),
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.pkt_tx_full (instInterface.transmitFIFOFull),
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.pkt_tx_val (instInterface.transmitValid),
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.reset_156m25_n (instInterface.rstTxRxInterface_n),
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// XGMII interface signals
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.clk_xgmii_rx (instInterface.clkXGMIIInterfaceRx),
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.reset_xgmii_rx_n (instInterface.rstXGMIIInterfaceRx_n),
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.xgmii_rxc (instInterface.xgmiiTransmitControl),
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.xgmii_rxd (instInterface.xgmiiTransmitData),
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.clk_xgmii_tx (instInterface.clkXGMIIInterfaceTx),
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.reset_xgmii_tx_n (instInterface.rstXGMIIInterfaceTx_n),
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.xgmii_txc (instInterface.xgmiiTransmitControl),
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.xgmii_txd (instInterface.xgmiiTransmitData),
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// Wishbone interface signals
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.wb_clk_i (instInterface.clkWishboneInterface),
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.wb_rst_i (instInterface.rstWishboneInterface),
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.wb_adr_i (instInterface.wishboneInputAddress),
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.wb_cyc_i (instInterface.wishboneCycle),
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.wb_dat_i (instInterface.wishboneInputData),
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.wb_stb_i (instInterface.wishboneStrobe),
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.wb_we_i (instInterface.wishboneWriteEnable),
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.wb_ack_o (instInterface.wishboneAck),
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.wb_dat_o (instInterface.wishboneOutputData),
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.wb_int_o (instInterface.wishboneInterrupt)
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);
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// Testcase instatiation
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testcase instTest ( .driverTestInterface (instInterface.TESTMOD ),
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.monitorTestInterface (instInterface.TESTMOD )
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);
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endmodule // top
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