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[/] [xge_mac/] [trunk/] [tbench/] [systemc/] [sc_main.cpp] - Blame information for rev 7

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// $Id: sc_main.cpp,v 1.3 2008-06-07 02:59:55 antanguay Exp $ -*- SystemC -*-
// DESCRIPTION: Verilator Example: Top level main for invoking SystemC model
//
// Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// General Public License or the Perl Artistic License.
//====================================================================
 
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "sc_main.cpp"                                     ////
////                                                              ////
////  This file is part of the "10GE MAC" project                 ////
////  http://www.opencores.org/cores/xge_mac/                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - A. Tanguay (antanguay@opencores.org)                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
#include <stdio.h>
#include <iostream>
#include <sys/times.h>
#include <sys/stat.h>
 
#include "systemc.h"            // SystemC global header
#include "SpTraceVcd.h"
 
#include "crc.h"
 
#include "Vxge_mac.h"           // Top level header, generated from verilog
 
#include "sc_testbench.h"
#include "sc_testcases.h"
 
 
int sc_main(int argc, char* argv[]) {
 
    chksum_crc32gentab();
 
    Verilated::randReset(2);
    Verilated::debug(0); // We compiled with it on for testing, turn it back off
 
    // General logfile
    ios::sync_with_stdio();
 
    cout << ("Defining Clocks\n");
 
    sc_clock clk_156m25 ("clk_156m25", 10, 0.5, 3, true);
    sc_clock clk_wb ("clk_wb", 29, 0.5, 3, true);
    sc_clock clk_xgmii ("clk_xgmii", 10, 0.5, 3, true);
 
    sc_signal<bool> pkt_rx_ren;
    sc_signal<sc_bv<64> > pkt_tx_data;
    sc_signal<bool> pkt_tx_eop;
    sc_signal<unsigned int> pkt_tx_mod;
    sc_signal<bool> pkt_tx_sop;
    sc_signal<bool> pkt_tx_val;
    sc_signal<bool> reset_156m25_n;
    sc_signal<bool> reset_xgmii_n;
    sc_signal<unsigned int> wb_adr_i;
    sc_signal<bool> wb_cyc_i;
    sc_signal<unsigned int > wb_dat_i;
    sc_signal<bool> wb_rst_i;
    sc_signal<bool> wb_stb_i;
    sc_signal<bool> wb_we_i;
    sc_signal<unsigned int> xgmii_rxc;
    sc_signal<sc_bv<64> > xgmii_rxd;
 
    sc_signal<bool> pkt_rx_avail;
    sc_signal<sc_bv<64> > pkt_rx_data;
    sc_signal<bool> pkt_rx_eop;
    sc_signal<unsigned int> pkt_rx_mod;
    sc_signal<bool> pkt_rx_sop;
    sc_signal<bool> pkt_rx_val;
    sc_signal<bool> pkt_rx_err;
    sc_signal<bool> pkt_tx_full;
    sc_signal<bool> wb_ack_o;
    sc_signal<unsigned int> wb_dat_o;
    sc_signal<bool> wb_int_o;
    sc_signal<unsigned int> xgmii_txc;
    sc_signal<sc_bv<64> > xgmii_txd;
 
    //==========
    // Part under test
 
    Vxge_mac* top = new Vxge_mac("top");
 
    top->clk_156m25 (clk_156m25);
    top->clk_xgmii_rx (clk_xgmii);
    top->clk_xgmii_tx (clk_xgmii);
 
    top->pkt_rx_ren (pkt_rx_ren);
    top->pkt_tx_data (pkt_tx_data);
    top->pkt_tx_eop (pkt_tx_eop);
    top->pkt_tx_mod (pkt_tx_mod);
    top->pkt_tx_sop (pkt_tx_sop);
    top->pkt_tx_val (pkt_tx_val);
    top->reset_156m25_n (reset_156m25_n);
    top->reset_xgmii_rx_n (reset_xgmii_n);
    top->reset_xgmii_tx_n (reset_xgmii_n);
    top->wb_adr_i (wb_adr_i);
    top->wb_clk_i (clk_wb);
    top->wb_cyc_i (wb_cyc_i);
    top->wb_dat_i (wb_dat_i);
    top->wb_rst_i (wb_rst_i);
    top->wb_stb_i (wb_stb_i);
    top->wb_we_i (wb_we_i);
    top->xgmii_rxc (xgmii_rxc);
    top->xgmii_rxd (xgmii_rxd);
 
    top->pkt_rx_avail (pkt_rx_avail);
    top->pkt_rx_data (pkt_rx_data);
    top->pkt_rx_eop (pkt_rx_eop);
    top->pkt_rx_mod (pkt_rx_mod);
    top->pkt_rx_err (pkt_rx_err);
    top->pkt_rx_sop (pkt_rx_sop);
    top->pkt_rx_val (pkt_rx_val);
    top->pkt_tx_full (pkt_tx_full);
    top->wb_ack_o (wb_ack_o);
    top->wb_dat_o (wb_dat_o);
    top->wb_int_o (wb_int_o);
    top->xgmii_txc (xgmii_txc);
    top->xgmii_txd (xgmii_txd);
 
    //==========
    // Testbench
 
    testbench* tb = new testbench("tb");
 
    tb->clk_156m25 (clk_156m25);
    tb->clk_xgmii (clk_xgmii);
    tb->wb_clk_i (clk_wb);
 
    tb->reset_156m25_n (reset_156m25_n);
    tb->reset_xgmii_n (reset_xgmii_n);
    tb->wb_rst_i (wb_rst_i);
 
    tb->wb_ack_o (wb_ack_o);
    tb->wb_dat_o (wb_dat_o);
    tb->wb_int_o (wb_int_o);
 
    tb->wb_adr_i (wb_adr_i);
    tb->wb_cyc_i (wb_cyc_i);
    tb->wb_dat_i (wb_dat_i);
    tb->wb_stb_i (wb_stb_i);
    tb->wb_we_i (wb_we_i);
 
    tb->xgmii_rxc (xgmii_rxc);
    tb->xgmii_rxd (xgmii_rxd);
 
    tb->xgmii_txc (xgmii_txc);
    tb->xgmii_txd (xgmii_txd);
 
    tb->pkt_tx_data (pkt_tx_data);
    tb->pkt_tx_eop (pkt_tx_eop);
    tb->pkt_tx_mod (pkt_tx_mod);
    tb->pkt_tx_sop (pkt_tx_sop);
    tb->pkt_tx_val (pkt_tx_val);
 
    tb->pkt_tx_full (pkt_tx_full);
 
    tb->pkt_rx_avail (pkt_rx_avail);
    tb->pkt_rx_data (pkt_rx_data);
    tb->pkt_rx_eop (pkt_rx_eop);
    tb->pkt_rx_mod (pkt_rx_mod);
    tb->pkt_rx_err (pkt_rx_err);
    tb->pkt_rx_sop (pkt_rx_sop);
    tb->pkt_rx_val (pkt_rx_val);
 
    tb->pkt_rx_ren (pkt_rx_ren);
 
    //==========
    // Testcases
    testcases* tc = new testcases("tc");
 
    tc->connect_testbench(tb);
 
 
#if WAVES
    // Before any evaluation, need to know to calculate those signals only used for tracing
    Verilated::traceEverOn(true);
#endif
 
    // You must do one evaluation before enabling waves, in order to allow
    // SystemC to interconnect everything for testing.
    cout <<("Test initialization...\n");
 
    sc_start(1);
 
    reset_156m25_n = 0;
    wb_rst_i = 1;
    reset_xgmii_n = 0;
 
    sc_start(1);
 
#if WAVES
    cout << "Enabling waves...\n";
    SpTraceFile* tfp = new SpTraceFile;
    top->trace (tfp, 99);
    tfp->open ("vl_dump.vcd");
#endif
 
    //==========
    // Start of Test
 
    cout <<("Test beginning...\n");
 
    reset_156m25_n = 0;
    wb_rst_i = 1;
    reset_xgmii_n = 0;
 
    while (!tc->done) {
 
#if WAVES
        tfp->flush();
#endif
        if (VL_TIME_Q() > 10) {
            reset_156m25_n = 1;
            wb_rst_i = 0;
            reset_xgmii_n = 1;
        }
 
        sc_start(1);
    }
 
    top->final();
 
#if WAVES
    tfp->close();
#endif
 
    cout << "*-* All Finished *-*\n";
 
    return(0);
}
 
 

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[/] [xge_mac/] [trunk/] [tbench/] [systemc/] [sc_main.cpp] - Blame information for rev 7

Line No.	Rev	Author	Line
1	6	antanguay	`// $Id: sc_main.cpp,v 1.3 2008-06-07 02:59:55 antanguay Exp $ -- SystemC --`
2	4	antanguay	`// DESCRIPTION: Verilator Example: Top level main for invoking SystemC model`
3			`//`
4			`// Copyright 2003-2008 by Wilson Snyder. This program is free software; you can`
5			`// redistribute it and/or modify it under the terms of either the GNU`
6			`// General Public License or the Perl Artistic License.`
7			`//====================================================================`
8
9	2	antanguay	`//////////////////////////////////////////////////////////////////////`
10			`//// ////`
11			`//// File name "sc_main.cpp" ////`
12			`//// ////`
13			`//// This file is part of the "10GE MAC" project ////`
14			`//// http://www.opencores.org/cores/xge_mac/ ////`
15			`//// ////`
16			`//// Author(s): ////`
17			`//// - A. Tanguay (antanguay@opencores.org) ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20			`//// ////`
21			`//// Copyright (C) 2008 AUTHORS. All rights reserved. ////`
22			`//// ////`
23			`//// This source file may be used and distributed without ////`
24			`//// restriction provided that this copyright statement is not ////`
25			`//// removed from the file and that any derivative work contains ////`
26			`//// the original copyright notice and the associated disclaimer. ////`
27			`//// ////`
28			`//// This source file is free software; you can redistribute it ////`
29			`//// and/or modify it under the terms of the GNU Lesser General ////`
30			`//// Public License as published by the Free Software Foundation; ////`
31			`//// either version 2.1 of the License, or (at your option) any ////`
32			`//// later version. ////`
33			`//// ////`
34			`//// This source is distributed in the hope that it will be ////`
35			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
36			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
37			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
38			`//// details. ////`
39			`//// ////`
40			`//// You should have received a copy of the GNU Lesser General ////`
41			`//// Public License along with this source; if not, download it ////`
42			`//// from http://www.opencores.org/lgpl.shtml ////`
43			`//// ////`
44			`//////////////////////////////////////////////////////////////////////`
45
46			`#include <stdio.h>`
47			`#include <iostream>`
48			`#include <sys/times.h>`
49			`#include <sys/stat.h>`
50
51			`#include "systemc.h" // SystemC global header`
52			`#include "SpTraceVcd.h"`
53
54			`#include "crc.h"`
55
56			`#include "Vxge_mac.h" // Top level header, generated from verilog`
57
58			`#include "sc_testbench.h"`
59			`#include "sc_testcases.h"`
60
61
62			`int sc_main(int argc, char* argv[]) {`
63
64			`chksum_crc32gentab();`
65
66			`Verilated::randReset(2);`
67			`Verilated::debug(0); // We compiled with it on for testing, turn it back off`
68
69			`// General logfile`
70			`ios::sync_with_stdio();`
71
72			`cout << ("Defining Clocks\n");`
73
74			`sc_clock clk_156m25 ("clk_156m25", 10, 0.5, 3, true);`
75			`sc_clock clk_wb ("clk_wb", 29, 0.5, 3, true);`
76			`sc_clock clk_xgmii ("clk_xgmii", 10, 0.5, 3, true);`
77
78			`sc_signal<bool> pkt_rx_ren;`
79			`sc_signal<sc_bv<64> > pkt_tx_data;`
80	6	antanguay	`sc_signal<bool> pkt_tx_eop;`
81			`sc_signal<unsigned int> pkt_tx_mod;`
82	2	antanguay	`sc_signal<bool> pkt_tx_sop;`
83			`sc_signal<bool> pkt_tx_val;`
84			`sc_signal<bool> reset_156m25_n;`
85			`sc_signal<bool> reset_xgmii_n;`
86			`sc_signal<unsigned int> wb_adr_i;`
87			`sc_signal<bool> wb_cyc_i;`
88			`sc_signal<unsigned int > wb_dat_i;`
89			`sc_signal<bool> wb_rst_i;`
90			`sc_signal<bool> wb_stb_i;`
91			`sc_signal<bool> wb_we_i;`
92			`sc_signal<unsigned int> xgmii_rxc;`
93			`sc_signal<sc_bv<64> > xgmii_rxd;`
94
95			`sc_signal<bool> pkt_rx_avail;`
96			`sc_signal<sc_bv<64> > pkt_rx_data;`
97	6	antanguay	`sc_signal<bool> pkt_rx_eop;`
98			`sc_signal<unsigned int> pkt_rx_mod;`
99	2	antanguay	`sc_signal<bool> pkt_rx_sop;`
100			`sc_signal<bool> pkt_rx_val;`
101			`sc_signal<bool> pkt_rx_err;`
102			`sc_signal<bool> pkt_tx_full;`
103			`sc_signal<bool> wb_ack_o;`
104			`sc_signal<unsigned int> wb_dat_o;`
105			`sc_signal<bool> wb_int_o;`
106			`sc_signal<unsigned int> xgmii_txc;`
107			`sc_signal<sc_bv<64> > xgmii_txd;`
108
109			`//==========`
110			`// Part under test`
111
112			`Vxge_mac* top = new Vxge_mac("top");`
113
114			`top->clk_156m25 (clk_156m25);`
115			`top->clk_xgmii_rx (clk_xgmii);`
116			`top->clk_xgmii_tx (clk_xgmii);`
117
118			`top->pkt_rx_ren (pkt_rx_ren);`
119			`top->pkt_tx_data (pkt_tx_data);`
120			`top->pkt_tx_eop (pkt_tx_eop);`
121	6	antanguay	`top->pkt_tx_mod (pkt_tx_mod);`
122	2	antanguay	`top->pkt_tx_sop (pkt_tx_sop);`
123			`top->pkt_tx_val (pkt_tx_val);`
124			`top->reset_156m25_n (reset_156m25_n);`
125			`top->reset_xgmii_rx_n (reset_xgmii_n);`
126			`top->reset_xgmii_tx_n (reset_xgmii_n);`
127			`top->wb_adr_i (wb_adr_i);`
128			`top->wb_clk_i (clk_wb);`
129			`top->wb_cyc_i (wb_cyc_i);`
130			`top->wb_dat_i (wb_dat_i);`
131			`top->wb_rst_i (wb_rst_i);`
132			`top->wb_stb_i (wb_stb_i);`
133			`top->wb_we_i (wb_we_i);`
134			`top->xgmii_rxc (xgmii_rxc);`
135			`top->xgmii_rxd (xgmii_rxd);`
136
137			`top->pkt_rx_avail (pkt_rx_avail);`
138			`top->pkt_rx_data (pkt_rx_data);`
139			`top->pkt_rx_eop (pkt_rx_eop);`
140	6	antanguay	`top->pkt_rx_mod (pkt_rx_mod);`
141	2	antanguay	`top->pkt_rx_err (pkt_rx_err);`
142			`top->pkt_rx_sop (pkt_rx_sop);`
143			`top->pkt_rx_val (pkt_rx_val);`
144			`top->pkt_tx_full (pkt_tx_full);`
145			`top->wb_ack_o (wb_ack_o);`
146			`top->wb_dat_o (wb_dat_o);`
147			`top->wb_int_o (wb_int_o);`
148			`top->xgmii_txc (xgmii_txc);`
149			`top->xgmii_txd (xgmii_txd);`
150
151			`//==========`
152			`// Testbench`
153
154			`testbench* tb = new testbench("tb");`
155
156			`tb->clk_156m25 (clk_156m25);`
157			`tb->clk_xgmii (clk_xgmii);`
158			`tb->wb_clk_i (clk_wb);`
159
160			`tb->reset_156m25_n (reset_156m25_n);`
161			`tb->reset_xgmii_n (reset_xgmii_n);`
162			`tb->wb_rst_i (wb_rst_i);`
163
164			`tb->wb_ack_o (wb_ack_o);`
165			`tb->wb_dat_o (wb_dat_o);`
166			`tb->wb_int_o (wb_int_o);`
167
168			`tb->wb_adr_i (wb_adr_i);`
169			`tb->wb_cyc_i (wb_cyc_i);`
170			`tb->wb_dat_i (wb_dat_i);`
171			`tb->wb_stb_i (wb_stb_i);`
172			`tb->wb_we_i (wb_we_i);`
173
174			`tb->xgmii_rxc (xgmii_rxc);`
175			`tb->xgmii_rxd (xgmii_rxd);`
176
177			`tb->xgmii_txc (xgmii_txc);`
178			`tb->xgmii_txd (xgmii_txd);`
179
180			`tb->pkt_tx_data (pkt_tx_data);`
181			`tb->pkt_tx_eop (pkt_tx_eop);`
182	6	antanguay	`tb->pkt_tx_mod (pkt_tx_mod);`
183	2	antanguay	`tb->pkt_tx_sop (pkt_tx_sop);`
184			`tb->pkt_tx_val (pkt_tx_val);`
185
186			`tb->pkt_tx_full (pkt_tx_full);`
187
188			`tb->pkt_rx_avail (pkt_rx_avail);`
189			`tb->pkt_rx_data (pkt_rx_data);`
190			`tb->pkt_rx_eop (pkt_rx_eop);`
191	6	antanguay	`tb->pkt_rx_mod (pkt_rx_mod);`
192	2	antanguay	`tb->pkt_rx_err (pkt_rx_err);`
193			`tb->pkt_rx_sop (pkt_rx_sop);`
194			`tb->pkt_rx_val (pkt_rx_val);`
195
196			`tb->pkt_rx_ren (pkt_rx_ren);`
197
198			`//==========`
199			`// Testcases`
200			`testcases* tc = new testcases("tc");`
201
202			`tc->connect_testbench(tb);`
203
204
205			`#if WAVES`
206			`// Before any evaluation, need to know to calculate those signals only used for tracing`
207			`Verilated::traceEverOn(true);`
208			`#endif`
209
210			`// You must do one evaluation before enabling waves, in order to allow`
211			`// SystemC to interconnect everything for testing.`
212			`cout <<("Test initialization...\n");`
213
214			`sc_start(1);`
215
216			`reset_156m25_n = 0;`
217			`wb_rst_i = 1;`
218			`reset_xgmii_n = 0;`
219
220			`sc_start(1);`
221
222			`#if WAVES`
223			`cout << "Enabling waves...\n";`
224			`SpTraceFile* tfp = new SpTraceFile;`
225			`top->trace (tfp, 99);`
226			`tfp->open ("vl_dump.vcd");`
227			`#endif`
228
229			`//==========`
230			`// Start of Test`
231
232			`cout <<("Test beginning...\n");`
233
234			`reset_156m25_n = 0;`
235			`wb_rst_i = 1;`
236			`reset_xgmii_n = 0;`
237
238			`while (!tc->done) {`
239
240			`#if WAVES`
241			`tfp->flush();`
242			`#endif`
243			`if (VL_TIME_Q() > 10) {`
244			`reset_156m25_n = 1;`
245			`wb_rst_i = 0;`
246			`reset_xgmii_n = 1;`
247			`}`
248
249			`sc_start(1);`
250			`}`
251
252			`top->final();`
253
254			`#if WAVES`
255			`tfp->close();`
256			`#endif`
257
258			`cout << "- All Finished -\n";`
259
260			`return(0);`
261			`}`
262
263