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[/] [xilinx_virtex_fp_library/] [trunk/] [GeneralPrecMAFMappedConversions/] [shifter.v] - Blame information for rev 16

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:00:33 10/15/2013 
// Design Name: 
// Module Name:    shifter 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
 
module shifter #(       parameter                INPUT_SIZE = 13,
                                                parameter                SHIFT_SIZE = 4,
                                                parameter                OUTPUT_SIZE = 24, //>INPUT_SIZE
                                                parameter                DIRECTION = 1,
                                                parameter                PIPELINE = 1,
                                                parameter [7:0]          POSITION = 8'b00000000)
                                        (a, arith, shft, shifted_a);
 
        input [INPUT_SIZE-1:0]   a;
        input                    arith;
        input [SHIFT_SIZE-1:0]   shft;
        output [OUTPUT_SIZE-1:0] shifted_a;
 
 
 
        wire [OUTPUT_SIZE-1:0]   a_temp_d[SHIFT_SIZE:0];
        wire [OUTPUT_SIZE-1:0]   a_temp_q[SHIFT_SIZE:0];
 
        assign a_temp_q[0][OUTPUT_SIZE-1 : OUTPUT_SIZE-INPUT_SIZE] = a;
        assign a_temp_q[0][OUTPUT_SIZE-1-INPUT_SIZE : 0] = arith;
 
        generate
        begin : GENERATING
                genvar i;
                for (i = 0; i <= SHIFT_SIZE - 1; i = i + 1)
                begin : BARREL_SHIFTER_GENERATION
                        if (DIRECTION == 1)
                        begin : LEFT
                                genvar j;
                                for (j = 0; j <= OUTPUT_SIZE - 1; j = j + 1)
                                begin : MUX_GEN_L
                                        if (j < 2 ** i)
                                        begin : ZERO_INS_L
                                                assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : arith;
                                        end
 
                                        if (j >= 2 ** i)
                                        begin : BIT_INS_L
                                                assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : a_temp_q[i][j-2**i];
                                        end
                                end
                        end
 
                        if (DIRECTION == 0)
                        begin : RIGHT
                                genvar j;
                                for (j = 0; j <= OUTPUT_SIZE - 1; j = j + 1)
                                begin : MUX_GEN_R
                                        if (OUTPUT_SIZE - 1 < 2 ** i + j)
                                        begin : ZERO_INS_R
                                                assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : arith;
                                        end
 
                                        if (OUTPUT_SIZE - 1 >= 2 ** i + j)
                                        begin : BIT_INS_R
                                                assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : a_temp_q[i][j+2**i];
                                        end
                                end
                        end
 
                        if (PIPELINE != 0)
                        begin : PIPELINE_INSERTION
                                if (POSITION[i] == 1'b1)
                                begin : LATCH
                                        d_ff #(OUTPUT_SIZE) D_INS(.clk(clk), .rst(rst), .d(a_temp_d[i]), .q(a_temp_q[i + 1]));
                                end
 
                                if (POSITION[i] == 1'b0)
                                begin : NO_LATCH
                                        assign a_temp_q[i + 1] = a_temp_d[i];
                                end
                        end
 
                        if (PIPELINE == 0)
                        begin : NO_PIPELINE
                                assign a_temp_q[i + 1] = a_temp_d[i];
                        end
                end
        end
        endgenerate
 
        assign shifted_a = a_temp_q[SHIFT_SIZE];
 
endmodule

Line No.	Rev	Author	Line
1	16	constantin	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company:`
4			`// Engineer:`
5			`//`
6			`// Create Date: 18:00:33 10/15/2013`
7			`// Design Name:`
8			`// Module Name: shifter`
9			`// Project Name:`
10			`// Target Devices:`
11			`// Tool versions:`
12			`// Description:`
13			`//`
14			`// Dependencies:`
15			`//`
16			`// Revision:`
17			`// Revision 0.01 - File Created`
18			`// Additional Comments:`
19			`//`
20			`//////////////////////////////////////////////////////////////////////////////////`
21
22			`module shifter #( parameter INPUT_SIZE = 13,`
23			`parameter SHIFT_SIZE = 4,`
24			`parameter OUTPUT_SIZE = 24, //>INPUT_SIZE`
25			`parameter DIRECTION = 1,`
26			`parameter PIPELINE = 1,`
27			`parameter [7:0] POSITION = 8'b00000000)`
28			`(a, arith, shft, shifted_a);`
29
30			`input [INPUT_SIZE-1:0] a;`
31			`input arith;`
32			`input [SHIFT_SIZE-1:0] shft;`
33			`output [OUTPUT_SIZE-1:0] shifted_a;`
34
35
36
37			`wire [OUTPUT_SIZE-1:0] a_temp_d[SHIFT_SIZE:0];`
38			`wire [OUTPUT_SIZE-1:0] a_temp_q[SHIFT_SIZE:0];`
39
40			`assign a_temp_q[0][OUTPUT_SIZE-1 : OUTPUT_SIZE-INPUT_SIZE] = a;`
41			`assign a_temp_q[0][OUTPUT_SIZE-1-INPUT_SIZE : 0] = arith;`
42
43			`generate`
44			`begin : GENERATING`
45			`genvar i;`
46			`for (i = 0; i <= SHIFT_SIZE - 1; i = i + 1)`
47			`begin : BARREL_SHIFTER_GENERATION`
48			`if (DIRECTION == 1)`
49			`begin : LEFT`
50			`genvar j;`
51			`for (j = 0; j <= OUTPUT_SIZE - 1; j = j + 1)`
52			`begin : MUX_GEN_L`
53			`if (j < 2 ** i)`
54			`begin : ZERO_INS_L`
55			`assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : arith;`
56			`end`
57
58			`if (j >= 2 ** i)`
59			`begin : BIT_INS_L`
60			`assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : a_temp_q[i][j-2**i];`
61			`end`
62			`end`
63			`end`
64
65			`if (DIRECTION == 0)`
66			`begin : RIGHT`
67			`genvar j;`
68			`for (j = 0; j <= OUTPUT_SIZE - 1; j = j + 1)`
69			`begin : MUX_GEN_R`
70			`if (OUTPUT_SIZE - 1 < 2 ** i + j)`
71			`begin : ZERO_INS_R`
72			`assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : arith;`
73			`end`
74
75			`if (OUTPUT_SIZE - 1 >= 2 ** i + j)`
76			`begin : BIT_INS_R`
77			`assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : a_temp_q[i][j+2**i];`
78			`end`
79			`end`
80			`end`
81
82			`if (PIPELINE != 0)`
83			`begin : PIPELINE_INSERTION`
84			`if (POSITION[i] == 1'b1)`
85			`begin : LATCH`
86			`d_ff #(OUTPUT_SIZE) D_INS(.clk(clk), .rst(rst), .d(a_temp_d[i]), .q(a_temp_q[i + 1]));`
87			`end`
88
89			`if (POSITION[i] == 1'b0)`
90			`begin : NO_LATCH`
91			`assign a_temp_q[i + 1] = a_temp_d[i];`
92			`end`
93			`end`
94
95			`if (PIPELINE == 0)`
96			`begin : NO_PIPELINE`
97			`assign a_temp_q[i + 1] = a_temp_d[i];`
98			`end`
99			`end`
100			`end`
101			`endgenerate`
102
103			`assign shifted_a = a_temp_q[SHIFT_SIZE];`
104
105			`endmodule`

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[/] [xilinx_virtex_fp_library/] [trunk/] [GeneralPrecMAFMappedConversions/] [shifter.v] - Blame information for rev 16