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#-- Synopsys, Inc.
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#-- Version 9.6.2
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#-- Project file D:\netlist\xmw2-comdec\prj\Synplify\xmw2-comdec.prj
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#-- Written on Fri Jul 24 11:02:47 2009
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#add_file options
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add_file -vhdl -lib xil_lib "../../lib/xil_lib/DP_RAM_XILINX_256.vhd"
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add_file -vhdl -lib xil_lib "../../lib/xil_lib/DP_RAM_XILINX_512.vhd"
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add_file -vhdl -lib xil_lib "../../lib/xil_lib/DP_RAM_XILINX_MASK.vhd"
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add_file -vhdl -lib xil_lib "../../lib/xil_lib/xil_comp.vhd"
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add_file -vhdl -lib dzx "../../lib/dzx/attributes_pkg.vhd"
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add_file -vhdl -lib dzx "../../lib/dzx/bit_arith_pkg.vhd"
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add_file -vhdl -lib dzx "../../lib/dzx/bit_arith_pkg_body.vhd"
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add_file -vhdl -lib dzx "../../lib/dzx/bit_utils_pkg.vhd"
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add_file -vhdl -lib dzx "../../lib/dzx/bit_utils_pkg_body.vhd"
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add_file -vhdl -lib work "../../src/reg_temp.vhd"
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add_file -vhdl -lib work "../../src/tech_package.vhd"
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add_file -vhdl -lib work "../../src/mux_ram.vhd"
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add_file -vhdl -lib work "../../src/sync_ram_register.vhd"
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add_file -vhdl -lib work "../../src/location_equal.vhd"
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add_file -vhdl -lib work "../../src/ff_finish_decoding.vhd"
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add_file -vhdl -lib work "../../src/out_register.vhd"
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add_file -vhdl -lib work "../../src/decode_mt_2.vhd"
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add_file -vhdl -lib work "../../src/decode4_16_inv.vhd"
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add_file -vhdl -lib work "../../src/decomp_assem_9.vhd"
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add_file -vhdl -lib work "../../src/decode_miss_2.vhd"
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add_file -vhdl -lib work "../../src/length_selection_2.vhd"
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add_file -vhdl -lib work "../../src/max_pbc_length_2.vhd"
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add_file -vhdl -lib work "../../src/mask_bit.vhd"
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add_file -vhdl -lib work "../../src/mask_word.vhd"
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add_file -vhdl -lib work "../../src/full_match_d.vhd"
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add_file -vhdl -lib work "../../src/miss_type_coder.vhd"
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add_file -vhdl -lib work "../../src/decomp_decode_4.vhd"
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add_file -vhdl -lib work "../../src/latch6.vhd"
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add_file -vhdl -lib work "../../src/latch7.vhd"
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add_file -vhdl -lib work "../../src/latch133.vhd"
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add_file -vhdl -lib work "../../src/pointer_first.vhd"
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add_file -vhdl -lib work "../../src/pointer_1.vhd"
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add_file -vhdl -lib work "../../src/pointer_2.vhd"
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add_file -vhdl -lib work "../../src/pointer_3.vhd"
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add_file -vhdl -lib work "../../src/pointer_4.vhd"
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add_file -vhdl -lib work "../../src/pointer_5.vhd"
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add_file -vhdl -lib work "../../src/pointer_6.vhd"
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add_file -vhdl -lib work "../../src/pointer_7.vhd"
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add_file -vhdl -lib work "../../src/pointer_8.vhd"
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add_file -vhdl -lib work "../../src/pointer_9.vhd"
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add_file -vhdl -lib work "../../src/pointer_10.vhd"
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add_file -vhdl -lib work "../../src/pointer_11.vhd"
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add_file -vhdl -lib work "../../src/pointer_12.vhd"
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add_file -vhdl -lib work "../../src/pointer_13.vhd"
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add_file -vhdl -lib work "../../src/pointer_14.vhd"
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add_file -vhdl -lib work "../../src/pointer_15.vhd"
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add_file -vhdl -lib work "../../src/pointer_array.vhd"
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add_file -vhdl -lib work "../../src/buffer_counter_write_9bits.vhd"
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add_file -vhdl -lib work "../../src/buffer_counter_read_9bits.vhd"
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add_file -vhdl -lib work "../../src/crc_unit_c_32.vhd"
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add_file -vhdl -lib work "../../src/crc_unit_d_32.vhd"
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add_file -vhdl -lib work "../../src/cam_bit_first.vhd"
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add_file -vhdl -lib work "../../src/input_counter_9bits.vhd"
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add_file -vhdl -lib work "../../src/cam_byte_first.vhd"
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add_file -vhdl -lib work "../../src/cam_bit.vhd"
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add_file -vhdl -lib work "../../src/cam_byte.vhd"
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add_file -vhdl -lib work "../../src/cam_word_first.vhd"
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add_file -vhdl -lib work "../../src/cam_word_zero.vhd"
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add_file -vhdl -lib work "../../src/cam_array_zero.vhd"
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add_file -vhdl -lib work "../../src/lc_assembler.vhd"
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add_file -vhdl -lib work "../../src/mc_mux_3d.vhd"
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add_file -vhdl -lib work "../../src/mc_mux_3c.vhd"
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add_file -vhdl -lib work "../../src/mg_logic_2.vhd"
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add_file -vhdl -lib work "../../src/mld_decode.vhd"
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add_file -vhdl -lib work "../../src/mld_dprop_5.vhd"
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add_file -vhdl -lib work "../../src/ob_assem.vhd"
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add_file -vhdl -lib work "../../src/PIPELINE_R1_D.vhd"
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add_file -vhdl -lib work "../../src/shift_literal.vhd"
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add_file -vhdl -lib work "../../src/oda_cell_2_d.vhd"
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add_file -vhdl -lib work "../../src/oda_cell_2_d_1.vhd"
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add_file -vhdl -lib work "../../src/oda_cell_2.vhd"
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add_file -vhdl -lib work "../../src/oda_register_d.vhd"
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add_file -vhdl -lib work "../../src/oda_register.vhd"
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add_file -vhdl -lib work "../../src/PIPELINE_R2_D.vhd"
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add_file -vhdl -lib work "../../src/rli_counter_d.vhd"
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add_file -vhdl -lib work "../../src/rli_counter_c.vhd"
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add_file -vhdl -lib work "../../src/RLI_DR.vhd"
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add_file -vhdl -lib work "../../src/RLI_DCU.vhd"
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add_file -vhdl -lib work "../../src/mt_coder.vhd"
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add_file -vhdl -lib work "../../src/ob_assembler.vhd"
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add_file -vhdl -lib work "../../src/ov_latch.vhd"
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add_file -vhdl -lib work "../../src/pc_generate.vhd"
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add_file -vhdl -lib work "../../src/nfl_counters2.vhd"
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add_file -vhdl -lib work "../../src/mld_dprop.vhd"
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add_file -vhdl -lib work "../../src/mld_logic_3_1_2.vhd"
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add_file -vhdl -lib work "../../src/mld_logic_3_2_2.vhd"
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add_file -vhdl -lib work "../../src/cm_assembler.vhd"
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add_file -vhdl -lib work "../../src/cml_assembler.vhd"
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add_file -vhdl -lib work "../../src/csm_c_2.vhd"
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add_file -vhdl -lib work "../../src/csm_d.vhd"
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add_file -vhdl -lib work "../../src/latch98.vhd"
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add_file -vhdl -lib work "../../src/PIPELINE_R0.vhd"
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add_file -vhdl -lib work "../../src/PIPELINE_R1.vhd"
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add_file -vhdl -lib work "../../src/PIPELINE_R4.vhd"
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add_file -vhdl -lib work "../../src/ff_v3_delay.vhd"
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add_file -vhdl -lib work "../../src/bsl_tc_2_c.vhd"
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add_file -vhdl -lib work "../../src/bsl_tc_2_d.vhd"
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add_file -vhdl -lib work "../../src/c_bs_counter_c.vhd"
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add_file -vhdl -lib work "../../src/c_bs_counter_d.vhd"
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add_file -vhdl -lib work "../../src/encode16_4.vhd"
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add_file -vhdl -lib work "../../src/CODING_BUFFER_CU.vhd"
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add_file -vhdl -lib work "../../src/decode_logic_pbc.vhd"
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add_file -vhdl -lib work "../../src/sreg.vhd"
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add_file -vhdl -lib work "../../src/count_delay.vhd"
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add_file -vhdl -lib work "../../src/rli_cr.vhd"
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add_file -vhdl -lib work "../../src/rli_ccu.vhd"
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add_file -vhdl -lib work "../../src/rli_coding_logic.vhd"
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add_file -vhdl -lib work "../../src/level2_4d_pbc.vhd"
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add_file -vhdl -lib work "../../src/level2_4ca.vhd"
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add_file -vhdl -lib work "../../src/DECODING_BUFFER_CU_2.vhd"
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add_file -vhdl -lib work "../../src/BUFFER_COUNTER_READ.vhd"
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add_file -vhdl -lib work "../../src/BUFFER_COUNTER_WRITE.vhd"
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add_file -vhdl -lib work "../../src/DECODING_BUFFER_32_64_2.vhd"
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add_file -vhdl -lib work "../../src/CODING_BUFFER_64_32.vhd"
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add_file -vhdl -lib work "../../src/control_reg.vhd"
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add_file -vhdl -lib work "../../src/reg_file_c.vhd"
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add_file -vhdl -lib work "../../src/reg_file_d.vhd"
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add_file -vhdl -lib work "../../src/parser.vhd"
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add_file -vhdl -lib work "../../src/parser_register.vhd"
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add_file -vhdl -lib work "../../src/parser_concatenator.vhd"
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add_file -vhdl -lib work "../../src/parsing_unit.vhd"
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add_file -vhdl -lib work "../../src/input_counter.vhd"
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add_file -vhdl -lib work "../../src/input_buffer_cu.vhd"
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add_file -vhdl -lib work "../../src/input_buffer_32_32.vhd"
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add_file -vhdl -lib work "../../src/assembler.vhd"
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add_file -vhdl -lib work "../../src/assembler_register.vhd"
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add_file -vhdl -lib work "../../src/assembling_unit.vhd"
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add_file -vhdl -lib work "../../src/output_buffer_cu.vhd"
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add_file -vhdl -lib work "../../src/output_buffer_32_32.vhd"
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add_file -vhdl -lib work "../../src/crc_unit_c.vhd"
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add_file -vhdl -lib work "../../src/crc_unit_d.vhd"
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add_file -vhdl -lib work "../../src/level1rc.vhd"
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add_file -vhdl -lib work "../../src/level1rd.vhd"
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add_file -vhdl -lib work "../../src/level1r.vhd"
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add_file -vhdl -lib work "../../src/tb_level1cr.vhd"
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#implementation: "rev_1"
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impl -add rev_1 -type fpga
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#device options
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set_option -technology VIRTEX5
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set_option -part XC5VLX110T
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set_option -package FF1136
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set_option -speed_grade -1
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set_option -part_companion ""
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#compilation/mapping options
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set_option -default_enum_encoding default
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set_option -resource_sharing 1
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set_option -use_fsm_explorer 0
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set_option -top_module "level1r"
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#map options
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set_option -frequency 140.000
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set_option -vendor_xcompatible_mode 0
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set_option -vendor_xcompatible_mode 0
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set_option -run_prop_extract 1
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set_option -fanout_limit 10000
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set_option -disable_io_insertion 0
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set_option -pipe 1
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set_option -update_models_cp 0
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set_option -enable_prepacking 0
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set_option -verification_mode 0
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set_option -retiming 0
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set_option -no_sequential_opt 0
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set_option -fixgatedclocks 3
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set_option -fixgeneratedclocks 3
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#sequential_optimizations options
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set_option -symbolic_fsm_compiler 1
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#simulation options
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set_option -write_verilog 0
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set_option -write_vhdl 0
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#VIF options
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set_option -write_vif 1
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#automatic place and route (vendor) options
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set_option -write_apr_constraint 1
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#set result format/file last
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project -result_file "./rev_1/level1r.edf"
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#
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#implementation attributes
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set_option -vlog_std v2001
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set_option -synthesis_onoff_pragma 0
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set_option -project_relative_includes 1
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#par_1 attributes
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set_option -job par_1 -add par
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set_option -job par_1 -option run_backannotation 0
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impl -active "rev_1"
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