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eejlny |
X-MatchPROvw readme file
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This release has been updated to support Xilinx V4/v5/Zynq parts. Pushbutton performance on these parts is around 100 MHz
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for V4 and 140 MHz for V5 which translates in a substained streaming compression/decompression throughput of 400 Mbytes/second
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and 560 Mbytes/second respectively.
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package contents
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directories:
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prj => create your modelsim, ise or synplify projects in the appropriate subfolder in this directory
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src => all the sources needed for the project. Fully synthesisable and targetting Altera FPGAs.
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lib => libraries needed for the project
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doc => documentation. The data sheet is the best paper to know how to use the core. xmw is the best paper to understanding
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the hardware architecture and CR_comp provides compression test results done by a third party agains the popular
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LZS algorithm
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test => test vector samples
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bin => executables to test compression/decompression performance in a Windows PC
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----modelsim
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To simulate the core create a project in the "prj/modelsim" directory. The "prj/modelsim" directory contains a script file (vw.do) that
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will do all the compilation for you.
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Once the prj has been create in the Modelsim prompt type "do vw.do" to create the required libraries and
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compile the whole project.
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Make sure that the vw.do file is located in your project directory.
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After compilation finishes successfully you can simulate the core using the testbench tb_level1cr.
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The testbench supplies sample data and checks the CRC error output for problems.
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The design is self testing in the sense that anything compressed by the compress channel will be decompressed
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by the decompress channel on the fly.
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Both channels will calculate a 32-bit CRC code that is compared at the end to detect any problems.
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----ISE
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To generate the design for the ML402 platform, create a project in the "prj/ISE" directory. This is achieved by opening the xmw2_comdec.npl
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file as a project file in ISE. ISE version 8.2 and greater will require the project file to be converted. once the conversion process
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is completed, the project can be implemented to generate the bitstream. It is important to note that a user constraint file ".ucf" is required
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in order to define how the ports of the XMW2_comdec map to the interface of the FPGA. This UCF file is not provided as it is dependant
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on user application.
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----Synplify
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Synplify_pro can be used to generate a netlist of the system. The xmw2-comdec.prj in "prj/Synplify" is the project file and when loaded
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automatically creates the project with all of the libraries in Synplify. The netlist can then be generated for a standalone implementattion
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of the system or as a module/netlist that will fit in a larger design.
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The NGC files in this "prj/Synplicity" are only required when the netlist generated in Synplify is to be ported to ISE software platform. The NGC
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files are essentially the encrypted memory module netlist required for implementation.
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The core has been fully tested using a Xilinx and Altera devices, however it can be modified for implementation in other platform.
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The core is available with a LGPL license and you can use it free of charge for commercial or research purposes.
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The supplied core implements a 16-entry dictionary that will provide limited compression.
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You are free to modify the core to increase the dictionary size although this process requires a
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good understanding of how the hardware works.
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Also available in the X-MatchPRO section of the http://seis.bris.ac.uk/~eejlny/ is the windows
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executables that can be use to test for compression results using different
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dictionary sizes.
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Contact us if you would like to discuss dictionary extensions or other type of modifications.
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email : j.l.nunez-yanez@bristol.ac.uk
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