Subversion Repositories xmatchpro

X-MatchPROvw readme file

This release has been updated to support Xilinx V4/v5/Zynq parts. Pushbutton performance on these parts is around 100 MHz

for V4 and 140 MHz for V5 which translates in a substained streaming compression/decompression throughput of 400 Mbytes/second

and 560 Mbytes/second respectively.

package contents

directories:

prj => create your modelsim, ise or synplify projects in the appropriate subfolder in this directory

src => all the sources needed for the project. Fully synthesisable and targetting Altera FPGAs.

lib => libraries needed for the project

doc => documentation. The data sheet is the best paper to know how to use the core. xmw is the best paper to understanding

       the hardware architecture and CR_comp provides compression test results done by a third party agains the popular

LZS algorithm

test => test vector samples

bin  => executables to test compression/decompression performance in a Windows PC

----modelsim

To simulate the core create a project in the "prj/modelsim" directory. The "prj/modelsim" directory contains a script file (vw.do) that

will do all the compilation for you.

Once the prj has been create in the Modelsim prompt type "do vw.do" to create the required libraries and

compile the whole project.

Make sure that the vw.do file is located in your project directory.

After compilation finishes successfully you can simulate the core using the testbench tb_level1cr.

The testbench supplies sample data and checks the CRC error output for problems.

The design is self testing in the sense that anything compressed by the compress channel will be decompressed

by the decompress channel on the fly.

Both channels will calculate a 32-bit CRC code that is compared at the end to detect any problems.

----ISE

To generate the design for the ML402 platform, create a project in the "prj/ISE" directory. This is achieved by opening the xmw2_comdec.npl

file as a project file in ISE. ISE version 8.2 and greater will require the project file to be converted. once the conversion process

is completed, the project can be implemented to generate the bitstream. It is important to note that a user constraint file ".ucf" is required

in order to define how the ports of the XMW2_comdec map to the interface of the FPGA. This UCF file is not provided as it is dependant

on user application.

----Synplify

Synplify_pro can be used to generate a netlist of the system. The xmw2-comdec.prj in "prj/Synplify" is the project file and when loaded

automatically creates the project with all of the libraries in Synplify. The netlist can then be generated for a standalone implementattion

of the system or as a module/netlist that will fit in a larger design.

The NGC files in this "prj/Synplicity" are only required when the netlist generated in Synplify is to be ported to ISE software platform. The NGC

files are essentially the encrypted memory module netlist required for implementation.

The core has been fully tested using a Xilinx and Altera devices, however it can be modified for implementation in other platform.

The core is available with a LGPL license and you can use it free of charge for commercial or research purposes.

The supplied core implements a 16-entry dictionary that will provide limited compression.

You are free to modify the core to increase the dictionary size although this process requires a

good understanding of how the hardware works.

Also available in the X-MatchPRO section of the http://seis.bris.ac.uk/~eejlny/ is the windows

executables that can be use to test for compression results using different

dictionary sizes.

Contact us if you would like to discuss dictionary extensions or other type of modifications.

email : j.l.nunez-yanez@bristol.ac.uk